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| author | Chris Wilson | 2016-04-09 11:57:57 +0200 |
|---|---|---|
| committer | Chris Wilson | 2016-04-09 13:09:59 +0200 |
| commit | 5dd8e50c27cd9294e53fc4c4b25b86abc469a4d4 (patch) | |
| tree | fe72b3bbc91993e5bf14bf5e3475746b941d079d /drivers/gpu/drm/i915/intel_ringbuffer.h | |
| parent | drm/i915: Use simplest form for flushing the single cacheline in the HWS (diff) | |
| download | kernel-qcow2-linux-5dd8e50c27cd9294e53fc4c4b25b86abc469a4d4.tar.gz kernel-qcow2-linux-5dd8e50c27cd9294e53fc4c4b25b86abc469a4d4.tar.xz kernel-qcow2-linux-5dd8e50c27cd9294e53fc4c4b25b86abc469a4d4.zip | |
drm/i915: Replace manual barrier() with READ_ONCE() in HWS accessor
When reading from the HWS page, we use barrier() to prevent the compiler
optimising away the read from the volatile (may be updated by the GPU)
memory address. This is more suited to READ_ONCE(); make it so.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460195877-20520-5-git-send-email-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 9d7b7bf9ed14..78dc46864a10 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -391,12 +391,10 @@ intel_flush_status_page(struct intel_engine_cs *engine, int reg) } static inline u32 -intel_read_status_page(struct intel_engine_cs *engine, - int reg) +intel_read_status_page(struct intel_engine_cs *engine, int reg) { /* Ensure that the compiler doesn't optimize away the load. */ - barrier(); - return engine->status_page.page_addr[reg]; + return READ_ONCE(engine->status_page.page_addr[reg]); } static inline void |