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| author | Imre Deak | 2017-06-29 17:36:58 +0200 |
|---|---|---|
| committer | Imre Deak | 2017-07-06 15:28:41 +0200 |
| commit | 846c6b26d38e56e5004f1d71d4c13226d2514750 (patch) | |
| tree | 83b820f8cd6e036b5cd70a4ec4a41b7d9216a270 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | drm/i915: Only free the oldest stale context before allocating (diff) | |
| download | kernel-qcow2-linux-846c6b26d38e56e5004f1d71d4c13226d2514750.tar.gz kernel-qcow2-linux-846c6b26d38e56e5004f1d71d4c13226d2514750.tar.xz kernel-qcow2-linux-846c6b26d38e56e5004f1d71d4c13226d2514750.zip | |
drm/i915/gen9+: Add 10 us delay after power well 1/AUX IO pw disabling
Bspec requires a 10 us delay after disabling power well 1 and - if not
toggled on-demand - the AUX IO power wells during display uninit.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1498750622-14023-2-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index efe80ed5fd4d..fd59016191ff 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2701,6 +2701,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) intel_power_well_disable(dev_priv, well); mutex_unlock(&power_domains->lock); + + usleep_range(10, 30); /* 10 us delay per Bspec */ } void bxt_display_core_init(struct drm_i915_private *dev_priv, @@ -2758,6 +2760,8 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv) intel_power_well_disable(dev_priv, well); mutex_unlock(&power_domains->lock); + + usleep_range(10, 30); /* 10 us delay per Bspec */ } #define CNL_PROCMON_IDX(val) \ @@ -2859,6 +2863,8 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) intel_power_well_disable(dev_priv, well); mutex_unlock(&power_domains->lock); + usleep_range(10, 30); /* 10 us delay per Bspec */ + /* 5. Disable Comp */ val = I915_READ(CHICKEN_MISC_2); val |= COMP_PWR_DOWN; |