diff options
| author | Oscar Mateo | 2018-05-08 23:29:26 +0200 |
|---|---|---|
| committer | Mika Kuoppala | 2018-05-11 14:55:13 +0200 |
| commit | d41bab687999793d7331b7b8906dca7e1aeb64c7 (patch) | |
| tree | 301c718d03fc90bef6a6aaf82a511bada184ff2d /drivers/gpu/drm/i915/intel_workarounds.c | |
| parent | drm/i915/icl: WaGAPZPriorityScheme (diff) | |
| download | kernel-qcow2-linux-d41bab687999793d7331b7b8906dca7e1aeb64c7.tar.gz kernel-qcow2-linux-d41bab687999793d7331b7b8906dca7e1aeb64c7.tar.xz kernel-qcow2-linux-d41bab687999793d7331b7b8906dca7e1aeb64c7.zip | |
drm/i915/icl: WaL3BankAddressHashing
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
v5:
- Added References (Mika)
- Fixed wrong mask and value (Mika)
- Do not apply together with another WA for the same
register (not worth the hassle)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#1604223664
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-5-git-send-email-oscar.mateo@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_workarounds.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_workarounds.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 44ae0b4f6079..3b037298ff99 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -705,6 +705,16 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) */ I915_WRITE(GEN8_GARBCNTL, I915_READ(GEN8_GARBCNTL) | GEN11_ARBITRATION_PRIO_ORDER_MASK); + + /* Wa_1604223664:icl + * Formerly known as WaL3BankAddressHashing + */ + I915_WRITE(GEN8_GARBCNTL, + (I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) | + GEN11_HASH_CTRL_EXCL_BIT0); + I915_WRITE(GEN11_GLBLINVL, + (I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) | + GEN11_BANK_HASH_ADDR_EXCL_BIT0); } void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) |