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| author | Lukas Wunner | 2017-09-09 20:32:41 +0200 |
|---|---|---|
| committer | Jonathan Cameron | 2017-10-09 22:01:36 +0200 |
| commit | c1375d671a352c525d76a8aba306667e0000d98a (patch) | |
| tree | 7f3d0cdb556b6f8767626dfb14c0a333857170bf /drivers/iio/adc/Kconfig | |
| parent | staging: iio: adc: ad7192: use driver private lock to protect hardware state ... (diff) | |
| download | kernel-qcow2-linux-c1375d671a352c525d76a8aba306667e0000d98a.tar.gz kernel-qcow2-linux-c1375d671a352c525d76a8aba306667e0000d98a.tar.xz kernel-qcow2-linux-c1375d671a352c525d76a8aba306667e0000d98a.zip | |
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/adc/Kconfig')
| -rw-r--r-- | drivers/iio/adc/Kconfig | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 383400b678c8..af4fc1279409 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -475,12 +475,13 @@ config MAX9611 called max9611. config MCP320X - tristate "Microchip Technology MCP3x01/02/04/08" + tristate "Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3" depends on SPI help Say yes here to build support for Microchip Technology's MCP3001, MCP3002, MCP3004, MCP3008, MCP3201, MCP3202, MCP3204, - MCP3208 or MCP3301 analog to digital converter. + MCP3208, MCP3301, MCP3550, MCP3551 and MCP3553 analog to digital + converters. This driver can also be built as a module. If so, the module will be called mcp320x. |