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author | Masahiro Yamada | 2017-03-30 08:45:49 +0200 |
---|---|---|
committer | Boris Brezillon | 2017-04-25 14:18:32 +0200 |
commit | 8927ad394b0653329184863e3d44958f67705e84 (patch) | |
tree | 2e607b0843a70fc33e6e690f21dad00c5c0fb1ab /drivers/mtd | |
parent | mtd: nand: denali: allow to override mtd->name from label DT property (diff) | |
download | kernel-qcow2-linux-8927ad394b0653329184863e3d44958f67705e84.tar.gz kernel-qcow2-linux-8927ad394b0653329184863e3d44958f67705e84.tar.xz kernel-qcow2-linux-8927ad394b0653329184863e3d44958f67705e84.zip |
mtd: nand: denali: remove meaningless pipeline read-ahead operation
The pipeline read-ahead function of the Denali IP enables continuous
reading from the device; while data is being read out by a CPU, the
controller maintains additional commands for streaming data from the
device. This will reduce the latency of the second page or later.
This feature is obviously no help for per-page accessors of Linux
NAND driver interface.
In the current implementation, the pipeline command is issued to
load a single page, then data are read out immediately. The use of
the pipeline operation is not adding any advantage, but just adding
complexity to the code. Remove.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r-- | drivers/mtd/nand/denali.c | 42 |
1 files changed, 3 insertions, 39 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 4e6d03d7a031..65cf7cccedbe 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -84,7 +84,6 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) #define SPARE_ACCESS 0x41 #define MAIN_ACCESS 0x42 #define MAIN_SPARE_ACCESS 0x43 -#define PIPELINE_ACCESS 0x2000 #define DENALI_READ 0 #define DENALI_WRITE 0x100 @@ -683,15 +682,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, int access_type, int op) { int status = PASS; - uint32_t page_count = 1; - uint32_t addr, cmd, irq_status, irq_mask; - - if (op == DENALI_READ) - irq_mask = INTR__LOAD_COMP; - else if (op == DENALI_WRITE) - irq_mask = 0; - else - BUG(); + uint32_t addr, cmd; setup_ecc_for_xfer(denali, ecc_en, transfer_spare); @@ -714,35 +705,8 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, cmd = MODE_10 | addr; index_addr(denali, cmd, access_type); - /* - * page 33 of the NAND controller spec indicates we should not - * use the pipeline commands in Spare area only mode. - * So we don't. - */ - if (access_type == SPARE_ACCESS) { - cmd = MODE_01 | addr; - iowrite32(cmd, denali->flash_mem); - } else { - index_addr(denali, cmd, - PIPELINE_ACCESS | op | page_count); - - /* - * wait for command to be accepted - * can always use status0 bit as the - * mask is identical for each bank. - */ - irq_status = wait_for_irq(denali, irq_mask); - - if (irq_status == 0) { - dev_err(denali->dev, - "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", - cmd, denali->page, addr); - status = FAIL; - } else { - cmd = MODE_01 | addr; - iowrite32(cmd, denali->flash_mem); - } - } + cmd = MODE_01 | addr; + iowrite32(cmd, denali->flash_mem); } return status; } |