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| author | Yoshihiro Shimoda | 2015-05-26 13:13:43 +0200 |
|---|---|---|
| committer | Felipe Balbi | 2015-05-26 17:21:53 +0200 |
| commit | 93fb9127cb63a3246b32d48fa273010764687862 (patch) | |
| tree | 5fee26d03eeba0683b43a9a5a2c048f2bb4223d5 /drivers/usb | |
| parent | usb: renesas_usbhs: Fix fifo unclear in usbhsf_prepare_pop (diff) | |
| download | kernel-qcow2-linux-93fb9127cb63a3246b32d48fa273010764687862.tar.gz kernel-qcow2-linux-93fb9127cb63a3246b32d48fa273010764687862.tar.xz kernel-qcow2-linux-93fb9127cb63a3246b32d48fa273010764687862.zip | |
usb: renesas_usbhs: Don't disable the pipe if Control write status stage
This patch fixes an issue that sometimes this controller is not able
to complete the Control write status stage.
This driver should enable DCPCTR.CCPL and PID_BUF to complete the status
stage. However, if this driver detects the ctrl_stage interruption first
before the control write data is received, this driver will clear the
PID_BUF wrongly in the usbhsf_pio_try_pop(). To avoid this issue, this
patch doesn't clear the PID_BUF in the usbhsf_pio_try_pop().
(Since also the privious code doesn't disable the PID_BUF after a control
transfer was finished, this patch doesn't have any side efforts.)
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb')
| -rw-r--r-- | drivers/usb/renesas_usbhs/fifo.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c index 0bad84ebe9aa..c0f5c652d272 100644 --- a/drivers/usb/renesas_usbhs/fifo.c +++ b/drivers/usb/renesas_usbhs/fifo.c @@ -678,7 +678,14 @@ static int usbhsf_pio_try_pop(struct usbhs_pkt *pkt, int *is_done) *is_done = 1; usbhsf_rx_irq_ctrl(pipe, 0); usbhs_pipe_running(pipe, 0); - usbhs_pipe_disable(pipe); /* disable pipe first */ + /* + * If function mode, since this controller is possible to enter + * Control Write status stage at this timing, this driver + * should not disable the pipe. If such a case happens, this + * controller is not able to complete the status stage. + */ + if (!usbhs_mod_is_host(priv) && !usbhs_pipe_is_dcp(pipe)) + usbhs_pipe_disable(pipe); /* disable pipe first */ } /* |