summaryrefslogtreecommitdiffstats
path: root/include/asm-generic/io.h
diff options
context:
space:
mode:
authorHoria Geantă2016-05-19 17:10:43 +0200
committerHerbert Xu2016-05-31 10:41:49 +0200
commit7a1aedba7061948eee4d188740e24ffb20ff7ab7 (patch)
tree4855ba940f8bf67f5ecbd39f4afcb17a1a57bbca /include/asm-generic/io.h
parentcrypto: qat - fix typos sizeof for ctx (diff)
downloadkernel-qcow2-linux-7a1aedba7061948eee4d188740e24ffb20ff7ab7.tar.gz
kernel-qcow2-linux-7a1aedba7061948eee4d188740e24ffb20ff7ab7.tar.xz
kernel-qcow2-linux-7a1aedba7061948eee4d188740e24ffb20ff7ab7.zip
asm-generic/io.h: allow barriers in io{read,write}{16,32}be
While reviewing the addition of io{read,write}64be accessors, Arnd -finds a potential problem: "If an architecture overrides readq/writeq to have barriers but does not override ioread64be/iowrite64be, this will lack the barriers and behave differently from the little-endian version. I think the only affected architecture is ARC, since ARM and ARM64 both override the big-endian accessors to have the correct barriers, and all others don't use barriers at all." -suggests a fix for the same problem in existing code (16/32-bit accessors); the fix leads "to a double-swap on architectures that don't override the io{read,write}{16,32}be accessors, but it will work correctly on all architectures without them having to override these accessors." Suggested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'include/asm-generic/io.h')
-rw-r--r--include/asm-generic/io.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 002b81f6f2bc..325c8908f6de 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -613,7 +613,7 @@ static inline void iowrite32(u32 value, volatile void __iomem *addr)
#define ioread16be ioread16be
static inline u16 ioread16be(const volatile void __iomem *addr)
{
- return __be16_to_cpu(__raw_readw(addr));
+ return swab16(readw(addr));
}
#endif
@@ -621,7 +621,7 @@ static inline u16 ioread16be(const volatile void __iomem *addr)
#define ioread32be ioread32be
static inline u32 ioread32be(const volatile void __iomem *addr)
{
- return __be32_to_cpu(__raw_readl(addr));
+ return swab32(readl(addr));
}
#endif
@@ -629,7 +629,7 @@ static inline u32 ioread32be(const volatile void __iomem *addr)
#define iowrite16be iowrite16be
static inline void iowrite16be(u16 value, void volatile __iomem *addr)
{
- __raw_writew(__cpu_to_be16(value), addr);
+ writew(swab16(value), addr);
}
#endif
@@ -637,7 +637,7 @@ static inline void iowrite16be(u16 value, void volatile __iomem *addr)
#define iowrite32be iowrite32be
static inline void iowrite32be(u32 value, volatile void __iomem *addr)
{
- __raw_writel(__cpu_to_be32(value), addr);
+ writel(swab32(value), addr);
}
#endif