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| author | Atsushi Nemoto | 2006-02-15 10:25:48 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2006-03-21 14:27:45 +0100 |
| commit | 37caa934af02bc01d0e1366a49e1c89360fa0f29 (patch) | |
| tree | 96f0a41a3edbd0404358a92e5af5c1739ce311ac /include/asm-mips/r4kcache.h | |
| parent | [MIPS] MIPS64 R2 optimizations for 64-bit endianess swapping. (diff) | |
| download | kernel-qcow2-linux-37caa934af02bc01d0e1366a49e1c89360fa0f29.tar.gz kernel-qcow2-linux-37caa934af02bc01d0e1366a49e1c89360fa0f29.tar.xz kernel-qcow2-linux-37caa934af02bc01d0e1366a49e1c89360fa0f29.zip | |
[MIPS] sc-rm7k.c cleanup
Use blast_scache_range, blast_inv_scache_range for rm7k scache routine.
Output code should be logically same.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/r4kcache.h')
| -rw-r--r-- | include/asm-mips/r4kcache.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 0bcb79a58ee9..90c374700977 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -303,5 +303,6 @@ __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) /* blast_inv_dcache_range */ __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) #endif /* _ASM_R4KCACHE_H */ |