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| author | Olof Johansson | 2007-12-28 05:16:29 +0100 |
|---|---|---|
| committer | Olof Johansson | 2007-12-28 16:22:25 +0100 |
| commit | d87bf3bed71375b141e95b5fdbac413ac4b65184 (patch) | |
| tree | 4920be669338029456f625e6f6a587b8e31185b0 /include/asm-powerpc | |
| parent | [POWERPC] pasemi: Implement NMI support (diff) | |
| download | kernel-qcow2-linux-d87bf3bed71375b141e95b5fdbac413ac4b65184.tar.gz kernel-qcow2-linux-d87bf3bed71375b141e95b5fdbac413ac4b65184.tar.xz kernel-qcow2-linux-d87bf3bed71375b141e95b5fdbac413ac4b65184.zip | |
[POWERPC] pasemi: Distribute interrupts evenly across cpus
By default the OpenPIC on PWRficient will bias to one core (since that
will improve changes of the other core being able to stay idle/powered
down). However, this conflicts with most irq load balancing schemes,
since setting an interrupt to be delivered to either core doesn't really
result in the load being shared. It also doesn't work well with the
soft irq disable feature of PPC, since EE will stay on until the first
interrupt is taken while soft disabled.
Set the gconf0 config bit that enables even distribution of interrupts
among the two cores.
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include/asm-powerpc')
| -rw-r--r-- | include/asm-powerpc/mpic.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index e7ac8109b6e7..943c5a3fac8a 100644 --- a/include/asm-powerpc/mpic.h +++ b/include/asm-powerpc/mpic.h @@ -22,6 +22,7 @@ #define MPIC_GREG_GLOBAL_CONF_0 0x00020 #define MPIC_GREG_GCONF_RESET 0x80000000 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 +#define MPIC_GREG_GCONF_NO_BIAS 0x10000000 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff #define MPIC_GREG_GCONF_MCK 0x08000000 #define MPIC_GREG_GLOBAL_CONF_1 0x00030 @@ -350,6 +351,8 @@ struct mpic #define MPIC_LARGE_VECTORS 0x00000100 /* Enable delivery of prio 15 interrupts as MCK instead of EE */ #define MPIC_ENABLE_MCK 0x00000200 +/* Disable bias among target selection, spread interrupts evenly */ +#define MPIC_NO_BIAS 0x00000400 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 |