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authorDave Airlie2012-06-27 09:35:52 +0200
committerDave Airlie2012-07-20 04:28:44 +0200
commitcdcac9cd7741af2c2b9255cbf060f772596907bb (patch)
tree0e8eb76992a020eb2be74aa6a57f358d0c42a036 /include/linux/pci_regs.h
parentdrm/radeon: improve GPU lockup debugging info on r6xx/r7xx/r8xx/r9xx (diff)
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pci_regs: define LNKSTA2 pcie cap + bits.
We need these for detecting the max link speed for drm drivers. Acked-by: Bjorn Helgaas <bhelgass@google.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include/linux/pci_regs.h')
-rw-r--r--include/linux/pci_regs.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 4b608f543412..7f04132eb02d 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -521,6 +521,11 @@
#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
+#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
+#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
+#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
+#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */
+#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */