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| author | Vijay Rai | 2015-01-05 16:44:42 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2015-01-09 23:33:04 +0100 |
| commit | fddceb8b5399083bcc042266f188116cc779fc80 (patch) | |
| tree | 018ed4ac4038d64d739aacdf2fbd25e29a81ede9 /include/uapi/linux/serial_core.h | |
| parent | serial: add device tree binding documentation for Conexant USART (diff) | |
| download | kernel-qcow2-linux-fddceb8b5399083bcc042266f188116cc779fc80.tar.gz kernel-qcow2-linux-fddceb8b5399083bcc042266f188116cc779fc80.tar.xz kernel-qcow2-linux-fddceb8b5399083bcc042266f188116cc779fc80.zip | |
tty: 8250: Add 64byte UART support for FSL platforms
Some of FSL SoCs like T1040 has new version of UART controller which
can support 64byte FiFo.
To enable 64 byte support, following needs to be done:
-FCR[EN64] needs to be programmed to 1 to enable it.
-Also, when FCR[EN64]==1, RTL bits to be used as below
to define various Receive Trigger Levels:
-FCR[RTL] = 00 1 byte
-FCR[RTL] = 01 16 bytes
-FCR[RTL] = 10 32 bytes
-FCR[RTL] = 11 56 bytes
-tx_loadsz is set to 63-bytes instead of 64-bytes to implement
workaround of errata A-008006 which states that tx_loadsz should
be configured less than Maximum supported fifo bytes
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/uapi/linux/serial_core.h')
| -rw-r--r-- | include/uapi/linux/serial_core.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 9124e837c181..ee628c489e47 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -55,7 +55,8 @@ #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ #define PORT_RT2880 29 /* Ralink RT2880 internal UART */ -#define PORT_MAX_8250 29 /* max port ID */ +#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ +#define PORT_MAX_8250 30 /* max port ID */ /* * ARM specific type numbers. These are not currently guaranteed |