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| author | Rakesh Ughreja | 2018-04-01 11:43:23 +0200 |
|---|---|---|
| committer | Mark Brown | 2018-04-17 12:35:30 +0200 |
| commit | 112c60b333ec9ddc7e940116f5e9fdc0d1a9706a (patch) | |
| tree | 49cd3d2a76c09e8ff0a6a42904104c016f6d1cc8 /sound/soc/intel/skylake/skl.c | |
| parent | ASoC: Intel: Skylake: Reset DSP Pipelines in prepare (diff) | |
| download | kernel-qcow2-linux-112c60b333ec9ddc7e940116f5e9fdc0d1a9706a.tar.gz kernel-qcow2-linux-112c60b333ec9ddc7e940116f5e9fdc0d1a9706a.tar.xz kernel-qcow2-linux-112c60b333ec9ddc7e940116f5e9fdc0d1a9706a.zip | |
ASoC: Intel: Skylake: Reset stream to link mapping
By default all the streams are mapped to all links after controller is
reset which causes stream to be broadcast on all the links.
This patch resets the stream-link mapping after controller reset. The
stream is mapped later to the appropriate link as part of stream setup.
Tested-by: Abhijeet Kumar <abhijeet.kumar@intel.com>
Signed-off-by: Rakesh Ughreja <rakesh.a.ughreja@intel.com>
Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/skylake/skl.c')
| -rw-r--r-- | sound/soc/intel/skylake/skl.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c index abf324747b29..f0d9793f872a 100644 --- a/sound/soc/intel/skylake/skl.c +++ b/sound/soc/intel/skylake/skl.c @@ -127,10 +127,17 @@ static void skl_clock_power_gating(struct device *dev, bool enable) */ static int skl_init_chip(struct hdac_bus *bus, bool full_reset) { + struct hdac_ext_bus *ebus = hbus_to_ebus(bus); + struct hdac_ext_link *hlink; int ret; skl_enable_miscbdcge(bus->dev, false); ret = snd_hdac_bus_init_chip(bus, full_reset); + + /* Reset stream-to-link mapping */ + list_for_each_entry(hlink, &ebus->hlink_list, list) + bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); + skl_enable_miscbdcge(bus->dev, true); return ret; |