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-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index db035374087e..f906f599a141 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,10 +11,12 @@
#include <linux/of_platform.h>
#include <linux/serial_core.h>
+#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/map.h>
+#include <mach/regs-pmu.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
@@ -91,6 +93,28 @@ static void __init exynos5250_dt_map_io(void)
static void __init exynos5250_dt_machine_init(void)
{
+ struct device_node *i2c_np;
+ const char *i2c_compat = "samsung,s3c2440-i2c";
+ unsigned int tmp;
+
+ /*
+ * Exynos5's legacy i2c controller and new high speed i2c
+ * controller have muxed interrupt sources. By default the
+ * interrupts for 4-channel HS-I2C controller are enabled.
+ * If node for first four channels of legacy i2c controller
+ * are available then re-configure the interrupts via the
+ * system register.
+ */
+ for_each_compatible_node(i2c_np, NULL, i2c_compat) {
+ if (of_device_is_available(i2c_np)) {
+ if (of_alias_get_id(i2c_np, "i2c") < 4) {
+ tmp = readl(EXYNOS5_SYS_I2C_CFG);
+ writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")),
+ EXYNOS5_SYS_I2C_CFG);
+ }
+ }
+ }
+
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
}