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-rw-r--r--arch/mips/au1000/common/prom.c24
-rw-r--r--arch/mips/au1000/common/sleeper.S5
-rw-r--r--arch/mips/kernel/cpu-bugs64.c8
-rw-r--r--arch/mips/kernel/cpu-probe.c2
-rw-r--r--arch/mips/kernel/module.c6
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mips/kernel/setup.c18
-rw-r--r--arch/mips/kernel/smp.c5
-rw-r--r--arch/mips/kernel/syscall.c3
-rw-r--r--arch/mips/kernel/traps.c19
-rw-r--r--arch/mips/math-emu/dp_fint.c4
-rw-r--r--arch/mips/math-emu/dp_flong.c4
-rw-r--r--arch/mips/math-emu/sp_fint.c4
-rw-r--r--arch/mips/math-emu/sp_flong.c4
-rw-r--r--arch/mips/mm/c-r4k.c34
-rw-r--r--arch/mips/mm/init.c2
-rw-r--r--arch/mips/oprofile/common.c8
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c32
-rw-r--r--arch/mips/oprofile/op_model_rm9000.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c4
20 files changed, 128 insertions, 62 deletions
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/au1000/common/prom.c
index 9c171afd9a53..ae7d8c57bf3f 100644
--- a/arch/mips/au1000/common/prom.c
+++ b/arch/mips/au1000/common/prom.c
@@ -1,10 +1,9 @@
/*
*
* BRIEF MODULE DESCRIPTION
- * PROM library initialisation code, assuming a version of
- * pmon is the boot code.
+ * PROM library initialisation code, assuming YAMON is the boot loader.
*
- * Copyright 2000,2001 MontaVista Software Inc.
+ * Copyright 2000, 2001, 2006 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
@@ -49,9 +48,9 @@ extern char **prom_argv, **prom_envp;
typedef struct
{
- char *name;
-/* char *val; */
-}t_env_var;
+ char *name;
+ char *val;
+} t_env_var;
char * prom_getcmdline(void)
@@ -85,21 +84,16 @@ char *prom_getenv(char *envname)
{
/*
* Return a pointer to the given environment variable.
- * Environment variables are stored in the form of "memsize=64".
*/
t_env_var *env = (t_env_var *)prom_envp;
- int i;
-
- i = strlen(envname);
- while(env->name) {
- if(strncmp(envname, env->name, i) == 0) {
- return(env->name + strlen(envname) + 1);
- }
+ while (env->name) {
+ if (strcmp(envname, env->name) == 0)
+ return env->val;
env++;
}
- return(NULL);
+ return NULL;
}
inline unsigned char str2hexnum(unsigned char c)
diff --git a/arch/mips/au1000/common/sleeper.S b/arch/mips/au1000/common/sleeper.S
index 44dac3b0df3b..683d9da84b66 100644
--- a/arch/mips/au1000/common/sleeper.S
+++ b/arch/mips/au1000/common/sleeper.S
@@ -112,6 +112,11 @@ sdsleep:
mtc0 k0, CP0_PAGEMASK
lw k0, 0x14(sp)
mtc0 k0, CP0_CONFIG
+
+ /* We need to catch the ealry Alchemy SOCs with
+ * the write-only Config[OD] bit and set it back to one...
+ */
+ jal au1x00_fixup_config_od
lw $1, PT_R1(sp)
lw $2, PT_R2(sp)
lw $3, PT_R3(sp)
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 47a087b6c11b..d268827c62bd 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -206,7 +206,7 @@ static inline void check_daddi(void)
"daddi %0, %1, %3\n\t"
".set pop"
: "=r" (v), "=&r" (tmp)
- : "I" (0xffffffffffffdb9a), "I" (0x1234));
+ : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
set_except_vector(12, handler);
local_irq_restore(flags);
@@ -224,7 +224,7 @@ static inline void check_daddi(void)
"dsrl %1, %1, 1\n\t"
"daddi %0, %1, %3"
: "=r" (v), "=&r" (tmp)
- : "I" (0xffffffffffffdb9a), "I" (0x1234));
+ : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
set_except_vector(12, handler);
local_irq_restore(flags);
@@ -280,7 +280,7 @@ static inline void check_daddiu(void)
"daddu %1, %2\n\t"
".set pop"
: "=&r" (v), "=&r" (w), "=&r" (tmp)
- : "I" (0xffffffffffffdb9a), "I" (0x1234));
+ : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
if (v == w) {
printk("no.\n");
@@ -296,7 +296,7 @@ static inline void check_daddiu(void)
"addiu %1, $0, %4\n\t"
"daddu %1, %2"
: "=&r" (v), "=&r" (w), "=&r" (tmp)
- : "I" (0xffffffffffffdb9a), "I" (0x1234));
+ : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
if (v == w) {
printk("yes.\n");
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bef3e2dc7c52..8c2c359a05f4 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -655,7 +655,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
case PRID_IMP_SB1:
c->cputype = CPU_SB1;
/* FPU in pass1 is known to have issues. */
- if ((c->processor_id & 0xff) < 0x20)
+ if ((c->processor_id & 0xff) < 0x02)
c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
break;
case PRID_IMP_SB1A:
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index e54a7f442f8a..d7bf0215bc1d 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -288,6 +288,9 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
sym = (Elf_Sym *)sechdrs[symindex].sh_addr
+ ELF_MIPS_R_SYM(rel[i]);
if (!sym->st_value) {
+ /* Ignore unresolved weak symbol */
+ if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
+ continue;
printk(KERN_WARNING "%s: Unknown symbol %s\n",
me->name, strtab + sym->st_name);
return -ENOENT;
@@ -325,6 +328,9 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
sym = (Elf_Sym *)sechdrs[symindex].sh_addr
+ ELF_MIPS_R_SYM(rel[i]);
if (!sym->st_value) {
+ /* Ignore unresolved weak symbol */
+ if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
+ continue;
printk(KERN_WARNING "%s: Unknown symbol %s\n",
me->name, strtab + sym->st_name);
return -ENOENT;
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index b53a9207f530..8efb23a84131 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -209,7 +209,7 @@ sys_call_table:
PTR sys_fork
PTR sys_read
PTR sys_write
- PTR sys_open /* 4005 */
+ PTR compat_sys_open /* 4005 */
PTR sys_close
PTR sys_waitpid
PTR sys_creat
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index bcf1b10e518f..397a70e651b5 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -246,7 +246,7 @@ static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_en
#ifdef CONFIG_64BIT
/* HACK: Guess if the sign extension was forgotten */
if (start > 0x0000000080000000 && start < 0x00000000ffffffff)
- start |= 0xffffffff00000000;
+ start |= 0xffffffff00000000UL;
#endif
end = start + size;
@@ -355,8 +355,6 @@ static inline void bootmem_init(void)
}
#endif
- memory_present(0, first_usable_pfn, max_low_pfn);
-
/* Initialize the boot-time allocator with low memory only. */
bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
@@ -410,6 +408,7 @@ static inline void bootmem_init(void)
/* Register lowmem ranges */
free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
+ memory_present(0, curr_pfn, curr_pfn + size - 1);
}
/* Reserve the bootmap memory. */
@@ -419,17 +418,20 @@ static inline void bootmem_init(void)
#ifdef CONFIG_BLK_DEV_INITRD
initrd_below_start_ok = 1;
if (initrd_start) {
- unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start);
+ unsigned long initrd_size = ((unsigned char *)initrd_end) -
+ ((unsigned char *)initrd_start);
+ const int width = sizeof(long) * 2;
+
printk("Initial ramdisk at: 0x%p (%lu bytes)\n",
(void *)initrd_start, initrd_size);
if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) {
printk("initrd extends beyond end of memory "
"(0x%0*Lx > 0x%0*Lx)\ndisabling initrd\n",
- sizeof(long) * 2,
- (unsigned long long)CPHYSADDR(initrd_end),
- sizeof(long) * 2,
- (unsigned long long)PFN_PHYS(max_low_pfn));
+ width,
+ (unsigned long long) CPHYSADDR(initrd_end),
+ width,
+ (unsigned long long) PFN_PHYS(max_low_pfn));
initrd_start = initrd_end = 0;
initrd_reserve_bootmem = 0;
}
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index d42f358754ad..298f82fe8440 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -247,6 +247,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
current_thread_info()->cpu = 0;
smp_tune_scheduling();
plat_prepare_cpus(max_cpus);
+#ifndef CONFIG_HOTPLUG_CPU
+ cpu_present_map = cpu_possible_map;
+#endif
}
/* preload SMP state for boot cpu */
@@ -442,7 +445,7 @@ static int __init topology_init(void)
int cpu;
int ret;
- for_each_cpu(cpu) {
+ for_each_present_cpu(cpu) {
ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL);
if (ret)
printk(KERN_WARNING "topology_init: register_cpu %d "
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 8f4fdd94dbd0..5e8a18a8e2bd 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -276,8 +276,7 @@ void sys_set_thread_area(unsigned long addr)
asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
{
- int tmp, len;
- char __user *name;
+ int tmp;
switch(cmd) {
case MIPS_ATOMIC_SET:
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 35cb08da3820..a7564b08eb4d 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -819,15 +819,30 @@ asmlinkage void do_watch(struct pt_regs *regs)
asmlinkage void do_mcheck(struct pt_regs *regs)
{
+ const int field = 2 * sizeof(unsigned long);
+ int multi_match = regs->cp0_status & ST0_TS;
+
show_regs(regs);
- dump_tlb_all();
+
+ if (multi_match) {
+ printk("Index : %0x\n", read_c0_index());
+ printk("Pagemask: %0x\n", read_c0_pagemask());
+ printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
+ printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
+ printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
+ printk("\n");
+ dump_tlb_all();
+ }
+
+ show_code((unsigned int *) regs->cp0_epc);
+
/*
* Some chips may have other causes of machine check (e.g. SB1
* graduation timer)
*/
panic("Caught Machine Check exception - %scaused by multiple "
"matching entries in the TLB.",
- (regs->cp0_status & ST0_TS) ? "" : "not ");
+ (multi_match) ? "" : "not ");
}
asmlinkage void do_mt(struct pt_regs *regs)
diff --git a/arch/mips/math-emu/dp_fint.c b/arch/mips/math-emu/dp_fint.c
index a1962eb460f8..39a71de16f47 100644
--- a/arch/mips/math-emu/dp_fint.c
+++ b/arch/mips/math-emu/dp_fint.c
@@ -29,7 +29,9 @@
ieee754dp ieee754dp_fint(int x)
{
- COMPXDP;
+ u64 xm;
+ int xe;
+ int xs;
CLEARCX;
diff --git a/arch/mips/math-emu/dp_flong.c b/arch/mips/math-emu/dp_flong.c
index eae90a866aa1..f08f223e488a 100644
--- a/arch/mips/math-emu/dp_flong.c
+++ b/arch/mips/math-emu/dp_flong.c
@@ -29,7 +29,9 @@
ieee754dp ieee754dp_flong(s64 x)
{
- COMPXDP;
+ u64 xm;
+ int xe;
+ int xs;
CLEARCX;
diff --git a/arch/mips/math-emu/sp_fint.c b/arch/mips/math-emu/sp_fint.c
index 7aac13afb09a..e88e125e01c2 100644
--- a/arch/mips/math-emu/sp_fint.c
+++ b/arch/mips/math-emu/sp_fint.c
@@ -29,7 +29,9 @@
ieee754sp ieee754sp_fint(int x)
{
- COMPXSP;
+ unsigned xm;
+ int xe;
+ int xs;
CLEARCX;
diff --git a/arch/mips/math-emu/sp_flong.c b/arch/mips/math-emu/sp_flong.c
index 3d6c1d11c178..26d6919a269a 100644
--- a/arch/mips/math-emu/sp_flong.c
+++ b/arch/mips/math-emu/sp_flong.c
@@ -29,7 +29,9 @@
ieee754sp ieee754sp_flong(s64 x)
{
- COMPXDP; /* <--- need 64-bit mantissa temp */
+ u64 xm; /* <--- need 64-bit mantissa temp */
+ int xe;
+ int xs;
CLEARCX;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6b3541769602..4a43924cd4fc 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1161,6 +1161,31 @@ static void __init setup_scache(void)
c->options |= MIPS_CPU_SUBSET_CACHES;
}
+void au1x00_fixup_config_od(void)
+{
+ /*
+ * c0_config.od (bit 19) was write only (and read as 0)
+ * on the early revisions of Alchemy SOCs. It disables the bus
+ * transaction overlapping and needs to be set to fix various errata.
+ */
+ switch (read_c0_prid()) {
+ case 0x00030100: /* Au1000 DA */
+ case 0x00030201: /* Au1000 HA */
+ case 0x00030202: /* Au1000 HB */
+ case 0x01030200: /* Au1500 AB */
+ /*
+ * Au1100 errata actually keeps silence about this bit, so we set it
+ * just in case for those revisions that require it to be set according
+ * to arch/mips/au1000/common/cputable.c
+ */
+ case 0x02030200: /* Au1100 AB */
+ case 0x02030201: /* Au1100 BA */
+ case 0x02030202: /* Au1100 BC */
+ set_c0_config(1 << 19);
+ break;
+ }
+}
+
static inline void coherency_setup(void)
{
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
@@ -1181,6 +1206,15 @@ static inline void coherency_setup(void)
case CPU_R4400MC:
clear_c0_config(CONF_CU);
break;
+ /*
+ * We need to catch the ealry Alchemy SOCs with
+ * the write-only co_config.od bit and set it back to one...
+ */
+ case CPU_AU1000: /* rev. DA, HA, HB */
+ case CPU_AU1100: /* rev. AB, BA, BC ?? */
+ case CPU_AU1500: /* rev. AB */
+ au1x00_fixup_config_od();
+ break;
}
}
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index c22308b93ff0..33f6e1cdfd5b 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -227,7 +227,7 @@ void __init mem_init(void)
for (tmp = 0; tmp < max_low_pfn; tmp++)
if (page_is_ram(tmp)) {
ram++;
- if (PageReserved(mem_map+tmp))
+ if (PageReserved(pfn_to_page(tmp)))
reservedpages++;
}
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 91b799d2cd88..c31e4cff64e0 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -14,8 +14,8 @@
#include "op_impl.h"
-extern struct op_mips_model op_model_mipsxx __attribute__((weak));
-extern struct op_mips_model op_model_rm9000 __attribute__((weak));
+extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak));
+extern struct op_mips_model op_model_rm9000_ops __attribute__((weak));
static struct op_mips_model *model;
@@ -83,11 +83,11 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
case CPU_74K:
case CPU_SB1:
case CPU_SB1A:
- lmodel = &op_model_mipsxx;
+ lmodel = &op_model_mipsxx_ops;
break;
case CPU_RM9000:
- lmodel = &op_model_rm9000;
+ lmodel = &op_model_rm9000_ops;
break;
};
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index e7ce92391303..f26a00e13204 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -23,7 +23,7 @@
#define M_COUNTER_OVERFLOW (1UL << 31)
-struct op_mips_model op_model_mipsxx;
+struct op_mips_model op_model_mipsxx_ops;
static struct mipsxx_register_config {
unsigned int control[4];
@@ -34,7 +34,7 @@ static struct mipsxx_register_config {
static void mipsxx_reg_setup(struct op_counter_config *ctr)
{
- unsigned int counters = op_model_mipsxx.num_counters;
+ unsigned int counters = op_model_mipsxx_ops.num_counters;
int i;
/* Compute the performance counter control word. */
@@ -62,7 +62,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
static void mipsxx_cpu_setup (void *args)
{
- unsigned int counters = op_model_mipsxx.num_counters;
+ unsigned int counters = op_model_mipsxx_ops.num_counters;
switch (counters) {
case 4:
@@ -83,7 +83,7 @@ static void mipsxx_cpu_setup (void *args)
/* Start all counters on current CPU */
static void mipsxx_cpu_start(void *args)
{
- unsigned int counters = op_model_mipsxx.num_counters;
+ unsigned int counters = op_model_mipsxx_ops.num_counters;
switch (counters) {
case 4:
@@ -100,7 +100,7 @@ static void mipsxx_cpu_start(void *args)
/* Stop all counters on current CPU */
static void mipsxx_cpu_stop(void *args)
{
- unsigned int counters = op_model_mipsxx.num_counters;
+ unsigned int counters = op_model_mipsxx_ops.num_counters;
switch (counters) {
case 4:
@@ -116,7 +116,7 @@ static void mipsxx_cpu_stop(void *args)
static int mipsxx_perfcount_handler(struct pt_regs *regs)
{
- unsigned int counters = op_model_mipsxx.num_counters;
+ unsigned int counters = op_model_mipsxx_ops.num_counters;
unsigned int control;
unsigned int counter;
int handled = 0;
@@ -187,37 +187,37 @@ static int __init mipsxx_init(void)
reset_counters(counters);
- op_model_mipsxx.num_counters = counters;
+ op_model_mipsxx_ops.num_counters = counters;
switch (current_cpu_data.cputype) {
case CPU_20KC:
- op_model_mipsxx.cpu_type = "mips/20K";
+ op_model_mipsxx_ops.cpu_type = "mips/20K";
break;
case CPU_24K:
- op_model_mipsxx.cpu_type = "mips/24K";
+ op_model_mipsxx_ops.cpu_type = "mips/24K";
break;
case CPU_25KF:
- op_model_mipsxx.cpu_type = "mips/25K";
+ op_model_mipsxx_ops.cpu_type = "mips/25K";
break;
#ifndef CONFIG_SMP
case CPU_34K:
- op_model_mipsxx.cpu_type = "mips/34K";
+ op_model_mipsxx_ops.cpu_type = "mips/34K";
break;
case CPU_74K:
- op_model_mipsxx.cpu_type = "mips/74K";
+ op_model_mipsxx_ops.cpu_type = "mips/74K";
break;
#endif
case CPU_5KC:
- op_model_mipsxx.cpu_type = "mips/5K";
+ op_model_mipsxx_ops.cpu_type = "mips/5K";
break;
case CPU_SB1:
case CPU_SB1A:
- op_model_mipsxx.cpu_type = "mips/sb1";
+ op_model_mipsxx_ops.cpu_type = "mips/sb1";
break;
default:
@@ -233,12 +233,12 @@ static int __init mipsxx_init(void)
static void mipsxx_exit(void)
{
- reset_counters(op_model_mipsxx.num_counters);
+ reset_counters(op_model_mipsxx_ops.num_counters);
perf_irq = null_perf_irq;
}
-struct op_mips_model op_model_mipsxx = {
+struct op_mips_model op_model_mipsxx_ops = {
.reg_setup = mipsxx_reg_setup,
.cpu_setup = mipsxx_cpu_setup,
.init = mipsxx_init,
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
index 9b75e41c78ef..b7063fefa65b 100644
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -126,7 +126,7 @@ static void rm9000_exit(void)
free_irq(rm9000_perfcount_irq, NULL);
}
-struct op_mips_model op_model_rm9000 = {
+struct op_mips_model op_model_rm9000_ops = {
.reg_setup = rm9000_reg_setup,
.cpu_setup = rm9000_cpu_setup,
.init = rm9000_init,
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index de01c9815bdd..8ba08047d164 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -31,12 +31,12 @@
/* issue a PIO read to make sure no PIO writes are pending */
static void inline flush_crime_bus(void)
{
- volatile unsigned long junk = crime->control;
+ crime->control;
}
static void inline flush_mace_bus(void)
{
- volatile unsigned long junk = mace->perif.ctrl.misc;
+ mace->perif.ctrl.misc;
}
#undef DEBUG_IRQ
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-09-06 04:04:40 +0200