diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 275 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 35 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu72.h | 24 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h | 24 |
7 files changed, 56 insertions, 312 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 95932cc88460..152e70db4a81 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -29,280 +29,7 @@ #include "amd_shared.h" #include "cgs_common.h" #include "dm_pp_interface.h" - -extern const struct amd_ip_funcs pp_ip_funcs; -extern const struct amd_pm_funcs pp_dpm_funcs; - -enum amd_pp_sensors { - AMDGPU_PP_SENSOR_GFX_SCLK = 0, - AMDGPU_PP_SENSOR_VDDNB, - AMDGPU_PP_SENSOR_VDDGFX, - AMDGPU_PP_SENSOR_UVD_VCLK, - AMDGPU_PP_SENSOR_UVD_DCLK, - AMDGPU_PP_SENSOR_VCE_ECCLK, - AMDGPU_PP_SENSOR_GPU_LOAD, - AMDGPU_PP_SENSOR_GFX_MCLK, - AMDGPU_PP_SENSOR_GPU_TEMP, - AMDGPU_PP_SENSOR_VCE_POWER, - AMDGPU_PP_SENSOR_UVD_POWER, - AMDGPU_PP_SENSOR_GPU_POWER, -}; - -enum amd_pp_task { - AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, - AMD_PP_TASK_ENABLE_USER_STATE, - AMD_PP_TASK_READJUST_POWER_STATE, - AMD_PP_TASK_COMPLETE_INIT, - AMD_PP_TASK_MAX -}; - -struct amd_pp_init { - struct cgs_device *device; - uint32_t chip_family; - uint32_t chip_id; - bool pm_en; - uint32_t feature_mask; -}; - -enum amd_pp_display_config_type{ - AMD_PP_DisplayConfigType_None = 0, - AMD_PP_DisplayConfigType_DP54 , - AMD_PP_DisplayConfigType_DP432 , - AMD_PP_DisplayConfigType_DP324 , - AMD_PP_DisplayConfigType_DP27, - AMD_PP_DisplayConfigType_DP243, - AMD_PP_DisplayConfigType_DP216, - AMD_PP_DisplayConfigType_DP162, - AMD_PP_DisplayConfigType_HDMI6G , - AMD_PP_DisplayConfigType_HDMI297 , - AMD_PP_DisplayConfigType_HDMI162, - AMD_PP_DisplayConfigType_LVDS, - AMD_PP_DisplayConfigType_DVI, - AMD_PP_DisplayConfigType_WIRELESS, - AMD_PP_DisplayConfigType_VGA -}; - -struct single_display_configuration -{ - uint32_t controller_index; - uint32_t controller_id; - uint32_t signal_type; - uint32_t display_state; - /* phy id for the primary internal transmitter */ - uint8_t primary_transmitter_phyi_d; - /* bitmap with the active lanes */ - uint8_t primary_transmitter_active_lanemap; - /* phy id for the secondary internal transmitter (for dual-link dvi) */ - uint8_t secondary_transmitter_phy_id; - /* bitmap with the active lanes */ - uint8_t secondary_transmitter_active_lanemap; - /* misc phy settings for SMU. */ - uint32_t config_flags; - uint32_t display_type; - uint32_t view_resolution_cx; - uint32_t view_resolution_cy; - enum amd_pp_display_config_type displayconfigtype; - uint32_t vertical_refresh; /* for active display */ -}; - -#define MAX_NUM_DISPLAY 32 - -struct amd_pp_display_configuration { - bool nb_pstate_switch_disable;/* controls NB PState switch */ - bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ - bool cpu_pstate_disable; - uint32_t cpu_pstate_separation_time; - - uint32_t num_display; /* total number of display*/ - uint32_t num_path_including_non_display; - uint32_t crossfire_display_index; - uint32_t min_mem_set_clock; - uint32_t min_core_set_clock; - /* unit 10KHz x bit*/ - uint32_t min_bus_bandwidth; - /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ - uint32_t min_core_set_clock_in_sr; - - struct single_display_configuration displays[MAX_NUM_DISPLAY]; - - uint32_t vrefresh; /* for active display*/ - - uint32_t min_vblank_time; /* for active display*/ - bool multi_monitor_in_sync; - /* Controller Index of primary display - used in MCLK SMC switching hang - * SW Workaround*/ - uint32_t crtc_index; - /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ - uint32_t line_time_in_us; - bool invalid_vblank_time; - - uint32_t display_clk; - /* - * for given display configuration if multimonitormnsync == false then - * Memory clock DPMS with this latency or below is allowed, DPMS with - * higher latency not allowed. - */ - uint32_t dce_tolerable_mclk_in_active_latency; - uint32_t min_dcef_set_clk; - uint32_t min_dcef_deep_sleep_set_clk; -}; - -struct amd_pp_simple_clock_info { - uint32_t engine_max_clock; - uint32_t memory_max_clock; - uint32_t level; -}; - -enum PP_DAL_POWERLEVEL { - PP_DAL_POWERLEVEL_INVALID = 0, - PP_DAL_POWERLEVEL_ULTRALOW, - PP_DAL_POWERLEVEL_LOW, - PP_DAL_POWERLEVEL_NOMINAL, - PP_DAL_POWERLEVEL_PERFORMANCE, - - PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, - PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, - PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, - PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, - PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, - PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, - PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, - PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, -}; - -struct amd_pp_clock_info { - uint32_t min_engine_clock; - uint32_t max_engine_clock; - uint32_t min_memory_clock; - uint32_t max_memory_clock; - uint32_t min_bus_bandwidth; - uint32_t max_bus_bandwidth; - uint32_t max_engine_clock_in_sr; - uint32_t min_engine_clock_in_sr; - enum PP_DAL_POWERLEVEL max_clocks_state; -}; - -enum amd_pp_clock_type { - amd_pp_disp_clock = 1, - amd_pp_sys_clock, - amd_pp_mem_clock, - amd_pp_dcef_clock, - amd_pp_soc_clock, - amd_pp_pixel_clock, - amd_pp_phy_clock, - amd_pp_dcf_clock, - amd_pp_dpp_clock, - amd_pp_f_clock = amd_pp_dcef_clock, -}; - -#define MAX_NUM_CLOCKS 16 - -struct amd_pp_clocks { - uint32_t count; - uint32_t clock[MAX_NUM_CLOCKS]; - uint32_t latency[MAX_NUM_CLOCKS]; -}; - - -enum { - PP_GROUP_UNKNOWN = 0, - PP_GROUP_GFX = 1, - PP_GROUP_SYS, - PP_GROUP_MAX -}; - -struct pp_states_info { - uint32_t nums; - uint32_t states[16]; -}; - -struct pp_gpu_power { - uint32_t vddc_power; - uint32_t vddci_power; - uint32_t max_gpu_power; - uint32_t average_gpu_power; -}; - -struct pp_display_clock_request { - enum amd_pp_clock_type clock_type; - uint32_t clock_freq_in_khz; -}; - -#define PP_GROUP_MASK 0xF0000000 -#define PP_GROUP_SHIFT 28 - -#define PP_BLOCK_MASK 0x0FFFFF00 -#define PP_BLOCK_SHIFT 8 - -#define PP_BLOCK_GFX_CG 0x01 -#define PP_BLOCK_GFX_MG 0x02 -#define PP_BLOCK_GFX_3D 0x04 -#define PP_BLOCK_GFX_RLC 0x08 -#define PP_BLOCK_GFX_CP 0x10 -#define PP_BLOCK_SYS_BIF 0x01 -#define PP_BLOCK_SYS_MC 0x02 -#define PP_BLOCK_SYS_ROM 0x04 -#define PP_BLOCK_SYS_DRM 0x08 -#define PP_BLOCK_SYS_HDP 0x10 -#define PP_BLOCK_SYS_SDMA 0x20 - -#define PP_STATE_MASK 0x0000000F -#define PP_STATE_SHIFT 0 -#define PP_STATE_SUPPORT_MASK 0x000000F0 -#define PP_STATE_SUPPORT_SHIFT 0 - -#define PP_STATE_CG 0x01 -#define PP_STATE_LS 0x02 -#define PP_STATE_DS 0x04 -#define PP_STATE_SD 0x08 -#define PP_STATE_SUPPORT_CG 0x10 -#define PP_STATE_SUPPORT_LS 0x20 -#define PP_STATE_SUPPORT_DS 0x40 -#define PP_STATE_SUPPORT_SD 0x80 - -#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\ - block << PP_BLOCK_SHIFT |\ - support << PP_STATE_SUPPORT_SHIFT |\ - state << PP_STATE_SHIFT) - -struct amd_powerplay { - struct cgs_device *cgs_device; - void *pp_handle; - const struct amd_ip_funcs *ip_funcs; - const struct amd_pm_funcs *pp_funcs; -}; - -int amd_powerplay_reset(void *handle); - -int amd_powerplay_display_configuration_change(void *handle, - const struct amd_pp_display_configuration *input); - -int amd_powerplay_get_display_power_level(void *handle, - struct amd_pp_simple_clock_info *output); - -int amd_powerplay_get_current_clocks(void *handle, - struct amd_pp_clock_info *output); - -int amd_powerplay_get_clock_by_type(void *handle, - enum amd_pp_clock_type type, - struct amd_pp_clocks *clocks); - -int amd_powerplay_get_clock_by_type_with_latency(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks); - -int amd_powerplay_get_clock_by_type_with_voltage(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks); - -int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); - -int amd_powerplay_display_clock_voltage_request(void *handle, - struct pp_display_clock_request *clock); - -int amd_powerplay_get_display_mode_validation_clocks(void *handle, - struct amd_pp_simple_clock_info *output); +#include "kgd_pp_interface.h" #endif /* _AMD_POWERPLAY_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h index 57a0467b7267..5716b937a6ad 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h @@ -437,5 +437,6 @@ extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr, extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr); +extern int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr); #endif /* _HARDWARE_MANAGER_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 004a40e88bde..565fe0832f41 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -105,36 +105,6 @@ struct phm_set_power_state_input { const struct pp_hw_power_state *pnew_state; }; -struct phm_acp_arbiter { - uint32_t acpclk; -}; - -struct phm_uvd_arbiter { - uint32_t vclk; - uint32_t dclk; - uint32_t vclk_ceiling; - uint32_t dclk_ceiling; - uint32_t vclk_soft_min; - uint32_t dclk_soft_min; -}; - -struct phm_vce_arbiter { - uint32_t evclk; - uint32_t ecclk; -}; - -struct phm_gfx_arbiter { - uint32_t sclk; - uint32_t sclk_hard_min; - uint32_t mclk; - uint32_t sclk_over_drive; - uint32_t mclk_over_drive; - uint32_t sclk_threshold; - uint32_t num_cus; - uint32_t gfxclk; - uint32_t fclk; -}; - struct phm_clock_array { uint32_t count; uint32_t values[1]; @@ -722,6 +692,7 @@ enum PP_TABLE_VERSION { struct pp_hwmgr { uint32_t chip_family; uint32_t chip_id; + uint32_t smu_version; uint32_t pp_table_version; void *device; @@ -737,10 +708,6 @@ struct pp_hwmgr { enum amd_dpm_forced_level dpm_level; enum amd_dpm_forced_level saved_dpm_level; enum amd_dpm_forced_level request_dpm_level; - struct phm_gfx_arbiter gfx_arbiter; - struct phm_acp_arbiter acp_arbiter; - struct phm_uvd_arbiter uvd_arbiter; - struct phm_vce_arbiter vce_arbiter; uint32_t usec_timeout; void *pptable; struct phm_platform_descriptor platform_descriptor; diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h index a511611ec7e0..b7ab69e4c254 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h @@ -23,7 +23,7 @@ #ifndef PP_SOC15_H #define PP_SOC15_H -#include "vega10/soc15ip.h" +#include "soc15ip.h" inline static uint32_t soc15_get_register_offset( uint32_t hw_id, diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h index 2b3497135bbd..f15f4df9d0a9 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h @@ -75,7 +75,12 @@ #define PPSMC_MSG_GetMinGfxclkFrequency 0x2C #define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D #define PPSMC_MSG_SoftReset 0x2E -#define PPSMC_Message_Count 0x2F +#define PPSMC_MSG_SetSoftMaxGfxClk 0x30 +#define PPSMC_MSG_SetHardMinGfxClk 0x31 +#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x32 +#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x33 +#define PPSMC_MSG_SetSoftMaxVcn 0x34 +#define PPSMC_Message_Count 0x35 typedef uint16_t PPSMC_Result; diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72.h b/drivers/gpu/drm/amd/powerplay/inc/smu72.h index 08cd70c75d8b..9ad1cefff79f 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_H #define SMU72_H diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h index b2edbc0c3c4d..2aefbb85f620 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_DISCRETE_H #define SMU72_DISCRETE_H |