diff options
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
53 files changed, 2445 insertions, 5188 deletions
diff --git a/drivers/gpu/drm/omapdrm/Makefile b/drivers/gpu/drm/omapdrm/Makefile index 48b7b750c05c..b391be7ecb6c 100644 --- a/drivers/gpu/drm/omapdrm/Makefile +++ b/drivers/gpu/drm/omapdrm/Makefile @@ -6,7 +6,6 @@ obj-y += dss/ obj-y += displays/ -ccflags-y := -Iinclude/drm omapdrm-y := omap_drv.o \ omap_irq.o \ omap_debugfs.o \ diff --git a/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c b/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c index aaa8a58390f1..542a76503fbd 100644 --- a/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c +++ b/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c @@ -14,8 +14,6 @@ #include <linux/platform_device.h> #include <linux/of.h> -#include <video/omap-panel-data.h> - #include "../dss/omapdss.h" struct panel_drv_data { @@ -25,8 +23,6 @@ struct panel_drv_data { struct device *dev; struct videomode vm; - - bool invert_polarity; }; static const struct videomode tvc_pal_vm = { @@ -95,13 +91,6 @@ static int tvc_enable(struct omap_dss_device *dssdev) in->ops.atv->set_timings(in, &ddata->vm); - if (!ddata->dev->of_node) { - in->ops.atv->set_type(in, OMAP_DSS_VENC_TYPE_COMPOSITE); - - in->ops.atv->invert_vid_out_polarity(in, - ddata->invert_polarity); - } - r = in->ops.atv->enable(in); if (r) return r; @@ -182,36 +171,10 @@ static struct omap_dss_driver tvc_driver = { .get_timings = tvc_get_timings, .check_timings = tvc_check_timings, - .get_resolution = omapdss_default_get_resolution, - .get_wss = tvc_get_wss, .set_wss = tvc_set_wss, }; -static int tvc_probe_pdata(struct platform_device *pdev) -{ - struct panel_drv_data *ddata = platform_get_drvdata(pdev); - struct connector_atv_platform_data *pdata; - struct omap_dss_device *in, *dssdev; - - pdata = dev_get_platdata(&pdev->dev); - - in = omap_dss_find_output(pdata->source); - if (in == NULL) { - dev_err(&pdev->dev, "Failed to find video source\n"); - return -EPROBE_DEFER; - } - - ddata->in = in; - - ddata->invert_polarity = pdata->invert_polarity; - - dssdev = &ddata->dssdev; - dssdev->name = pdata->name; - - return 0; -} - static int tvc_probe_of(struct platform_device *pdev) { struct panel_drv_data *ddata = platform_get_drvdata(pdev); @@ -235,6 +198,9 @@ static int tvc_probe(struct platform_device *pdev) struct omap_dss_device *dssdev; int r; + if (!pdev->dev.of_node) + return -ENODEV; + ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); if (!ddata) return -ENOMEM; @@ -242,17 +208,9 @@ static int tvc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ddata); ddata->dev = &pdev->dev; - if (dev_get_platdata(&pdev->dev)) { - r = tvc_probe_pdata(pdev); - if (r) - return r; - } else if (pdev->dev.of_node) { - r = tvc_probe_of(pdev); - if (r) - return r; - } else { - return -ENODEV; - } + r = tvc_probe_of(pdev); + if (r) + return r; ddata->vm = tvc_pal_vm; diff --git a/drivers/gpu/drm/omapdrm/displays/connector-dvi.c b/drivers/gpu/drm/omapdrm/displays/connector-dvi.c index d6875d9fcefa..05fa24a518c8 100644 --- a/drivers/gpu/drm/omapdrm/displays/connector-dvi.c +++ b/drivers/gpu/drm/omapdrm/displays/connector-dvi.c @@ -15,7 +15,6 @@ #include <linux/slab.h> #include <drm/drm_edid.h> -#include <video/omap-panel-data.h> #include "../dss/omapdss.h" @@ -228,8 +227,6 @@ static struct omap_dss_driver dvic_driver = { .get_timings = dvic_get_timings, .check_timings = dvic_check_timings, - .get_resolution = omapdss_default_get_resolution, - .read_edid = dvic_read_edid, .detect = dvic_detect, }; diff --git a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c index 1ef130641bae..d9d25df6fc1b 100644 --- a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c +++ b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c @@ -15,9 +15,9 @@ #include <linux/platform_device.h> #include <linux/of.h> #include <linux/of_gpio.h> +#include <linux/mutex.h> #include <drm/drm_edid.h> -#include <video/omap-panel-data.h> #include "../dss/omapdss.h" @@ -38,6 +38,10 @@ static const struct videomode hdmic_default_vm = { struct panel_drv_data { struct omap_dss_device dssdev; struct omap_dss_device *in; + void (*hpd_cb)(void *cb_data, enum drm_connector_status status); + void *hpd_cb_data; + bool hpd_enabled; + struct mutex hpd_lock; struct device *dev; @@ -168,6 +172,70 @@ static bool hdmic_detect(struct omap_dss_device *dssdev) return in->ops.hdmi->detect(in); } +static int hdmic_register_hpd_cb(struct omap_dss_device *dssdev, + void (*cb)(void *cb_data, + enum drm_connector_status status), + void *cb_data) +{ + struct panel_drv_data *ddata = to_panel_data(dssdev); + struct omap_dss_device *in = ddata->in; + + if (gpio_is_valid(ddata->hpd_gpio)) { + mutex_lock(&ddata->hpd_lock); + ddata->hpd_cb = cb; + ddata->hpd_cb_data = cb_data; + mutex_unlock(&ddata->hpd_lock); + return 0; + } else if (in->ops.hdmi->register_hpd_cb) { + return in->ops.hdmi->register_hpd_cb(in, cb, cb_data); + } + + return -ENOTSUPP; +} + +static void hdmic_unregister_hpd_cb(struct omap_dss_device *dssdev) +{ + struct panel_drv_data *ddata = to_panel_data(dssdev); + struct omap_dss_device *in = ddata->in; + + if (gpio_is_valid(ddata->hpd_gpio)) { + mutex_lock(&ddata->hpd_lock); + ddata->hpd_cb = NULL; + ddata->hpd_cb_data = NULL; + mutex_unlock(&ddata->hpd_lock); + } else if (in->ops.hdmi->unregister_hpd_cb) { + in->ops.hdmi->unregister_hpd_cb(in); + } +} + +static void hdmic_enable_hpd(struct omap_dss_device *dssdev) +{ + struct panel_drv_data *ddata = to_panel_data(dssdev); + struct omap_dss_device *in = ddata->in; + + if (gpio_is_valid(ddata->hpd_gpio)) { + mutex_lock(&ddata->hpd_lock); + ddata->hpd_enabled = true; + mutex_unlock(&ddata->hpd_lock); + } else if (in->ops.hdmi->enable_hpd) { + in->ops.hdmi->enable_hpd(in); + } +} + +static void hdmic_disable_hpd(struct omap_dss_device *dssdev) +{ + struct panel_drv_data *ddata = to_panel_data(dssdev); + struct omap_dss_device *in = ddata->in; + + if (gpio_is_valid(ddata->hpd_gpio)) { + mutex_lock(&ddata->hpd_lock); + ddata->hpd_enabled = false; + mutex_unlock(&ddata->hpd_lock); + } else if (in->ops.hdmi->disable_hpd) { + in->ops.hdmi->disable_hpd(in); + } +} + static int hdmic_set_hdmi_mode(struct omap_dss_device *dssdev, bool hdmi_mode) { struct panel_drv_data *ddata = to_panel_data(dssdev); @@ -196,14 +264,36 @@ static struct omap_dss_driver hdmic_driver = { .get_timings = hdmic_get_timings, .check_timings = hdmic_check_timings, - .get_resolution = omapdss_default_get_resolution, - .read_edid = hdmic_read_edid, .detect = hdmic_detect, + .register_hpd_cb = hdmic_register_hpd_cb, + .unregister_hpd_cb = hdmic_unregister_hpd_cb, + .enable_hpd = hdmic_enable_hpd, + .disable_hpd = hdmic_disable_hpd, .set_hdmi_mode = hdmic_set_hdmi_mode, .set_hdmi_infoframe = hdmic_set_infoframe, }; +static irqreturn_t hdmic_hpd_isr(int irq, void *data) +{ + struct panel_drv_data *ddata = data; + + mutex_lock(&ddata->hpd_lock); + if (ddata->hpd_enabled && ddata->hpd_cb) { + enum drm_connector_status status; + + if (hdmic_detect(&ddata->dssdev)) + status = connector_status_connected; + else + status = connector_status_disconnected; + + ddata->hpd_cb(ddata->hpd_cb_data, status); + } + mutex_unlock(&ddata->hpd_lock); + + return IRQ_HANDLED; +} + static int hdmic_probe_of(struct platform_device *pdev) { struct panel_drv_data *ddata = platform_get_drvdata(pdev); @@ -249,11 +339,22 @@ static int hdmic_probe(struct platform_device *pdev) if (r) return r; + mutex_init(&ddata->hpd_lock); + if (gpio_is_valid(ddata->hpd_gpio)) { r = devm_gpio_request_one(&pdev->dev, ddata->hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd"); if (r) goto err_reg; + + r = devm_request_threaded_irq(&pdev->dev, + gpio_to_irq(ddata->hpd_gpio), + NULL, hdmic_hpd_isr, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_ONESHOT, + "hdmic hpd", ddata); + if (r) + goto err_reg; } ddata->vm = hdmic_default_vm; diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c b/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c index f7a5731492d0..b1f6aa09f699 100644 --- a/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c +++ b/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c @@ -157,14 +157,6 @@ static int opa362_check_timings(struct omap_dss_device *dssdev, return in->ops.atv->check_timings(in, vm); } -static void opa362_set_type(struct omap_dss_device *dssdev, - enum omap_dss_venc_type type) -{ - /* we can only drive a COMPOSITE output */ - WARN_ON(type != OMAP_DSS_VENC_TYPE_COMPOSITE); - -} - static const struct omapdss_atv_ops opa362_atv_ops = { .connect = opa362_connect, .disconnect = opa362_disconnect, @@ -175,8 +167,6 @@ static const struct omapdss_atv_ops opa362_atv_ops = { .check_timings = opa362_check_timings, .set_timings = opa362_set_timings, .get_timings = opa362_get_timings, - - .set_type = opa362_set_type, }; static int opa362_probe(struct platform_device *pdev) diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c b/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c index 13e32d02c884..947295f9e30f 100644 --- a/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c +++ b/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c @@ -22,7 +22,6 @@ struct panel_drv_data { struct omap_dss_device *in; int pd_gpio; - int data_lines; struct videomode vm; }; @@ -82,8 +81,6 @@ static int tfp410_enable(struct omap_dss_device *dssdev) return 0; in->ops.dpi->set_timings(in, &ddata->vm); - if (ddata->data_lines) - in->ops.dpi->set_data_lines(in, ddata->data_lines); r = in->ops.dpi->enable(in); if (r) @@ -226,7 +223,6 @@ static int tfp410_probe(struct platform_device *pdev) dssdev->type = OMAP_DISPLAY_TYPE_DPI; dssdev->output_type = OMAP_DISPLAY_TYPE_DVI; dssdev->owner = THIS_MODULE; - dssdev->phy.dpi.data_lines = ddata->data_lines; dssdev->port_num = 1; r = omapdss_register_output(dssdev); diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c index 58276a48112e..a9e9d667c55e 100644 --- a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c +++ b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c @@ -15,12 +15,17 @@ #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/gpio/consumer.h> +#include <linux/mutex.h> #include "../dss/omapdss.h" struct panel_drv_data { struct omap_dss_device dssdev; struct omap_dss_device *in; + void (*hpd_cb)(void *cb_data, enum drm_connector_status status); + void *hpd_cb_data; + bool hpd_enabled; + struct mutex hpd_lock; struct gpio_desc *ct_cp_hpd_gpio; struct gpio_desc *ls_oe_gpio; @@ -162,6 +167,49 @@ static bool tpd_detect(struct omap_dss_device *dssdev) return gpiod_get_value_cansleep(ddata->hpd_gpio); } +static int tpd_register_hpd_cb(struct omap_dss_device *dssdev, + void (*cb)(void *cb_data, + enum drm_connector_status status), + void *cb_data) +{ + struct panel_drv_data *ddata = to_panel_data(dssdev); + + mutex_lock(&ddata->hpd_lock); + ddata->hpd_cb = cb; + ddata->hpd_cb_data = cb_data; + mutex_unlock(&ddata->hpd_lock); + + return 0; +} + +static void tpd_unregister_hpd_cb(struct omap_dss_device *dssdev) +{ + struct panel_drv_data *ddata = to_panel_data(dssdev); + + mutex_lock(&ddata->hpd_lock); + ddata->hpd_cb = NULL; + ddata->hpd_cb_data = NULL; + mutex_unlock(&ddata->hpd_lock); +} + +static void tpd_enable_hpd(struct omap_dss_device *dssdev) +{ + struct panel_drv_data *ddata = to_panel_data(dssdev); + + mutex_lock(&ddata->hpd_lock); + ddata->hpd_enabled = true; + mutex_unlock(&ddata->hpd_lock); +} + +static void tpd_disable_hpd(struct omap_dss_device *dssdev) +{ + struct panel_drv_data *ddata = to_panel_data(dssdev); + + mutex_lock(&ddata->hpd_lock); + ddata->hpd_enabled = false; + mutex_unlock(&ddata->hpd_lock); +} + static int tpd_set_infoframe(struct omap_dss_device *dssdev, const struct hdmi_avi_infoframe *avi) { @@ -193,10 +241,34 @@ static const struct omapdss_hdmi_ops tpd_hdmi_ops = { .read_edid = tpd_read_edid, .detect = tpd_detect, + .register_hpd_cb = tpd_register_hpd_cb, + .unregister_hpd_cb = tpd_unregister_hpd_cb, + .enable_hpd = tpd_enable_hpd, + .disable_hpd = tpd_disable_hpd, .set_infoframe = tpd_set_infoframe, .set_hdmi_mode = tpd_set_hdmi_mode, }; +static irqreturn_t tpd_hpd_isr(int irq, void *data) +{ + struct panel_drv_data *ddata = data; + + mutex_lock(&ddata->hpd_lock); + if (ddata->hpd_enabled && ddata->hpd_cb) { + enum drm_connector_status status; + + if (tpd_detect(&ddata->dssdev)) + status = connector_status_connected; + else + status = connector_status_disconnected; + + ddata->hpd_cb(ddata->hpd_cb_data, status); + } + mutex_unlock(&ddata->hpd_lock); + + return IRQ_HANDLED; +} + static int tpd_probe_of(struct platform_device *pdev) { struct panel_drv_data *ddata = platform_get_drvdata(pdev); @@ -261,6 +333,15 @@ static int tpd_probe(struct platform_device *pdev) ddata->hpd_gpio = gpio; + mutex_init(&ddata->hpd_lock); + + r = devm_request_threaded_irq(&pdev->dev, gpiod_to_irq(ddata->hpd_gpio), + NULL, tpd_hpd_isr, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "tpd12s015 hpd", ddata); + if (r) + goto err_gpio; + dssdev = &ddata->dssdev; dssdev->ops.hdmi = &tpd_hdmi_ops; dssdev->dev = &pdev->dev; diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c index 04ce8c5f2954..e065f7e10cca 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c @@ -14,11 +14,9 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/of.h> -#include <linux/of_gpio.h> #include <linux/regulator/consumer.h> #include <linux/backlight.h> -#include <video/omap-panel-data.h> #include <video/of_display_timing.h> #include "../dss/omapdss.h" @@ -27,15 +25,10 @@ struct panel_drv_data { struct omap_dss_device dssdev; struct omap_dss_device *in; - int data_lines; - struct videomode vm; struct backlight_device *backlight; - /* used for non-DT boot, to be removed */ - int backlight_gpio; - struct gpio_desc *enable_gpio; struct regulator *vcc_supply; }; @@ -81,8 +74,6 @@ static int panel_dpi_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - if (ddata->data_lines) - in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->vm); r = in->ops.dpi->enable(in); @@ -97,9 +88,6 @@ static int panel_dpi_enable(struct omap_dss_device *dssdev) gpiod_set_value_cansleep(ddata->enable_gpio, 1); - if (gpio_is_valid(ddata->backlight_gpio)) - gpio_set_value_cansleep(ddata->backlight_gpio, 1); - if (ddata->backlight) { ddata->backlight->props.power = FB_BLANK_UNBLANK; backlight_update_status(ddata->backlight); @@ -118,9 +106,6 @@ static void panel_dpi_disable(struct omap_dss_device *dssdev) if (!omapdss_device_is_enabled(dssdev)) return; - if (gpio_is_valid(ddata->backlight_gpio)) - gpio_set_value_cansleep(ddata->backlight_gpio, 0); - if (ddata->backlight) { ddata->backlight->props.power = FB_BLANK_POWERDOWN; backlight_update_status(ddata->backlight); @@ -173,51 +158,8 @@ static struct omap_dss_driver panel_dpi_ops = { .set_timings = panel_dpi_set_timings, .get_timings = panel_dpi_get_timings, .check_timings = panel_dpi_check_timings, - - .get_resolution = omapdss_default_get_resolution, }; -static int panel_dpi_probe_pdata(struct platform_device *pdev) -{ - const struct panel_dpi_platform_data *pdata; - struct panel_drv_data *ddata = platform_get_drvdata(pdev); - struct omap_dss_device *dssdev, *in; - int r; - - pdata = dev_get_platdata(&pdev->dev); - - in = omap_dss_find_output(pdata->source); - if (in == NULL) { - dev_err(&pdev->dev, "failed to find video source '%s'\n", - pdata->source); - return -EPROBE_DEFER; - } - - ddata->in = in; - - ddata->data_lines = pdata->data_lines; - - videomode_from_timing(pdata->display_timing, &ddata->vm); - - dssdev = &ddata->dssdev; - dssdev->name = pdata->name; - - r = devm_gpio_request_one(&pdev->dev, pdata->enable_gpio, - GPIOF_OUT_INIT_LOW, "panel enable"); - if (r) - goto err_gpio; - - ddata->enable_gpio = gpio_to_desc(pdata->enable_gpio); - - ddata->backlight_gpio = pdata->backlight_gpio; - - return 0; - -err_gpio: - omap_dss_put_device(ddata->in); - return r; -} - static int panel_dpi_probe_of(struct platform_device *pdev) { struct panel_drv_data *ddata = platform_get_drvdata(pdev); @@ -248,8 +190,6 @@ static int panel_dpi_probe_of(struct platform_device *pdev) if (IS_ERR(ddata->vcc_supply)) return PTR_ERR(ddata->vcc_supply); - ddata->backlight_gpio = -ENOENT; - bl_node = of_parse_phandle(node, "backlight", 0); if (bl_node) { ddata->backlight = of_find_backlight_by_node(bl_node); @@ -291,30 +231,18 @@ static int panel_dpi_probe(struct platform_device *pdev) struct omap_dss_device *dssdev; int r; + if (!pdev->dev.of_node) + return -ENODEV; + ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); if (ddata == NULL) return -ENOMEM; platform_set_drvdata(pdev, ddata); - if (dev_get_platdata(&pdev->dev)) { - r = panel_dpi_probe_pdata(pdev); - if (r) - return r; - } else if (pdev->dev.of_node) { - r = panel_dpi_probe_of(pdev); - if (r) - return r; - } else { - return -ENODEV; - } - - if (gpio_is_valid(ddata->backlight_gpio)) { - r = devm_gpio_request_one(&pdev->dev, ddata->backlight_gpio, - GPIOF_OUT_INIT_LOW, "panel backlight"); - if (r) - goto err_gpio; - } + r = panel_dpi_probe_of(pdev); + if (r) + return r; dssdev = &ddata->dssdev; dssdev->dev = &pdev->dev; @@ -322,7 +250,6 @@ static int panel_dpi_probe(struct platform_device *pdev) dssdev->type = OMAP_DISPLAY_TYPE_DPI; dssdev->owner = THIS_MODULE; dssdev->panel.vm = ddata->vm; - dssdev->phy.dpi.data_lines = ddata->data_lines; r = omapdss_register_display(dssdev); if (r) { @@ -333,7 +260,6 @@ static int panel_dpi_probe(struct platform_device *pdev) return 0; err_reg: -err_gpio: omap_dss_put_device(ddata->in); return r; } diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c index ac5800c72cb4..92c556ac22c7 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c @@ -379,13 +379,6 @@ static const struct backlight_ops dsicm_bl_ops = { .update_status = dsicm_bl_update_status, }; -static void dsicm_get_resolution(struct omap_dss_device *dssdev, - u16 *xres, u16 *yres) -{ - *xres = dssdev->panel.vm.hactive; - *yres = dssdev->panel.vm.vactive; -} - static ssize_t dsicm_num_errors_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -561,7 +554,7 @@ static struct attribute *dsicm_attrs[] = { NULL, }; -static struct attribute_group dsicm_attr_group = { +static const struct attribute_group dsicm_attr_group = { .attrs = dsicm_attrs, }; @@ -1116,9 +1109,6 @@ static struct omap_dss_driver dsicm_ops = { .update = dsicm_update, .sync = dsicm_sync, - .get_resolution = dsicm_get_resolution, - .get_recommended_bpp = omapdss_default_get_recommended_bpp, - .enable_te = dsicm_enable_te, .get_te = dsicm_get_te, diff --git a/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c b/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c index 43d21edb51f5..74d13969b9ca 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c @@ -19,7 +19,7 @@ #include "../dss/omapdss.h" -static struct videomode lb035q02_vm = { +static const struct videomode lb035q02_vm = { .hactive = 320, .vactive = 240, @@ -49,8 +49,6 @@ struct panel_drv_data { struct spi_device *spi; - int data_lines; - struct videomode vm; struct gpio_desc *enable_gpio; @@ -159,8 +157,6 @@ static int lb035q02_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - if (ddata->data_lines) - in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->vm); r = in->ops.dpi->enable(in); @@ -230,8 +226,6 @@ static struct omap_dss_driver lb035q02_ops = { .set_timings = lb035q02_set_timings, .get_timings = lb035q02_get_timings, .check_timings = lb035q02_check_timings, - - .get_resolution = omapdss_default_get_resolution, }; static int lb035q02_probe_of(struct spi_device *spi) @@ -289,7 +283,6 @@ static int lb035q02_panel_spi_probe(struct spi_device *spi) dssdev->type = OMAP_DISPLAY_TYPE_DPI; dssdev->owner = THIS_MODULE; dssdev->panel.vm = ddata->vm; - dssdev->phy.dpi.data_lines = ddata->data_lines; r = omapdss_register_display(dssdev); if (r) { diff --git a/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c b/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c index 2de27ba01552..df8132d3b9c6 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c @@ -25,8 +25,6 @@ struct panel_drv_data { struct videomode vm; - int data_lines; - int res_gpio; int qvga_gpio; @@ -153,8 +151,6 @@ static int nec_8048_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - if (ddata->data_lines) - in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->vm); r = in->ops.dpi->enable(in); @@ -224,8 +220,6 @@ static struct omap_dss_driver nec_8048_ops = { .set_timings = nec_8048_set_timings, .get_timings = nec_8048_get_timings, .check_timings = nec_8048_check_timings, - - .get_resolution = omapdss_default_get_resolution, }; static int nec_8048_probe_of(struct spi_device *spi) diff --git a/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c b/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c index 04fe235b7cac..98d170aecaba 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c @@ -24,8 +24,6 @@ struct panel_drv_data { struct omap_dss_device *in; struct regulator *vcc; - int data_lines; - struct videomode vm; struct gpio_desc *resb_gpio; /* low = reset active min 20 us */ @@ -99,8 +97,6 @@ static int sharp_ls_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - if (ddata->data_lines) - in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->vm); if (ddata->vcc) { @@ -194,8 +190,6 @@ static struct omap_dss_driver sharp_ls_ops = { .set_timings = sharp_ls_set_timings, .get_timings = sharp_ls_get_timings, .check_timings = sharp_ls_check_timings, - - .get_resolution = omapdss_default_get_resolution, }; static int sharp_ls_get_gpio_of(struct device *dev, int index, int val, @@ -289,7 +283,6 @@ static int sharp_ls_probe(struct platform_device *pdev) dssdev->type = OMAP_DISPLAY_TYPE_DPI; dssdev->owner = THIS_MODULE; dssdev->panel.vm = ddata->vm; - dssdev->phy.dpi.data_lines = ddata->data_lines; r = omapdss_register_display(dssdev); if (r) { diff --git a/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c b/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c index 5ab39e0060f2..8e5bff4e5226 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c @@ -32,8 +32,6 @@ #include <linux/of.h> #include <linux/of_gpio.h> -#include <video/omap-panel-data.h> - #include "../dss/omapdss.h" #define MIPID_CMD_READ_DISP_ID 0x04 @@ -69,7 +67,6 @@ struct panel_drv_data { struct omap_dss_device *in; int reset_gpio; - int datapairs; struct videomode vm; @@ -506,7 +503,7 @@ static struct attribute *bldev_attrs[] = { NULL, }; -static struct attribute_group bldev_attr_group = { +static const struct attribute_group bldev_attr_group = { .attrs = bldev_attrs, }; @@ -547,9 +544,6 @@ static int acx565akm_panel_power_on(struct omap_dss_device *dssdev) in->ops.sdi->set_timings(in, &ddata->vm); - if (ddata->datapairs > 0) - in->ops.sdi->set_datapairs(in, ddata->datapairs); - r = in->ops.sdi->enable(in); if (r) { pr_err("%s sdi enable failed\n", __func__); @@ -697,36 +691,8 @@ static struct omap_dss_driver acx565akm_ops = { .set_timings = acx565akm_set_timings, .get_timings = acx565akm_get_timings, .check_timings = acx565akm_check_timings, - - .get_resolution = omapdss_default_get_resolution, }; -static int acx565akm_probe_pdata(struct spi_device *spi) -{ - const struct panel_acx565akm_platform_data *pdata; - struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); - struct omap_dss_device *dssdev, *in; - - pdata = dev_get_platdata(&spi->dev); - - ddata->reset_gpio = pdata->reset_gpio; - - in = omap_dss_find_output(pdata->source); - if (in == NULL) { - dev_err(&spi->dev, "failed to find video source '%s'\n", - pdata->source); - return -EPROBE_DEFER; - } - ddata->in = in; - - ddata->datapairs = pdata->datapairs; - - dssdev = &ddata->dssdev; - dssdev->name = pdata->name; - - return 0; -} - static int acx565akm_probe_of(struct spi_device *spi) { struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); @@ -754,6 +720,9 @@ static int acx565akm_probe(struct spi_device *spi) dev_dbg(&spi->dev, "%s\n", __func__); + if (!spi->dev.of_node) + return -ENODEV; + spi->mode = SPI_MODE_3; ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL); @@ -766,18 +735,9 @@ static int acx565akm_probe(struct spi_device *spi) mutex_init(&ddata->mutex); - if (dev_get_platdata(&spi->dev)) { - r = acx565akm_probe_pdata(spi); - if (r) - return r; - } else if (spi->dev.of_node) { - r = acx565akm_probe_of(spi); - if (r) - return r; - } else { - dev_err(&spi->dev, "platform data missing!\n"); - return -ENODEV; - } + r = acx565akm_probe_of(spi); + if (r) + return r; if (gpio_is_valid(ddata->reset_gpio)) { r = devm_gpio_request_one(&spi->dev, ddata->reset_gpio, diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c index f313dbfcbacb..0a38a0e8c925 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c @@ -35,14 +35,12 @@ struct panel_drv_data { struct omap_dss_device dssdev; struct omap_dss_device *in; - int data_lines; - struct videomode vm; struct spi_device *spi_dev; }; -static struct videomode td028ttec1_panel_vm = { +static const struct videomode td028ttec1_panel_vm = { .hactive = 480, .vactive = 640, .pixelclock = 22153000, @@ -207,8 +205,6 @@ static int td028ttec1_panel_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - if (ddata->data_lines) - in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->vm); r = in->ops.dpi->enable(in); @@ -423,7 +419,6 @@ static int td028ttec1_panel_probe(struct spi_device *spi) dssdev->type = OMAP_DISPLAY_TYPE_DPI; dssdev->owner = THIS_MODULE; dssdev->panel.vm = ddata->vm; - dssdev->phy.dpi.data_lines = ddata->data_lines; r = omapdss_register_display(dssdev); if (r) { diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c index 0787dba44faa..ac4a6d4d134c 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c @@ -58,8 +58,6 @@ struct panel_drv_data { struct videomode vm; - int data_lines; - struct spi_device *spi; struct regulator *vcc_reg; int nreset_gpio; @@ -284,7 +282,7 @@ static struct attribute *tpo_td043_attrs[] = { NULL, }; -static struct attribute_group tpo_td043_attr_group = { +static const struct attribute_group tpo_td043_attr_group = { .attrs = tpo_td043_attrs, }; @@ -378,8 +376,6 @@ static int tpo_td043_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - if (ddata->data_lines) - in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->vm); r = in->ops.dpi->enable(in); @@ -461,8 +457,6 @@ static struct omap_dss_driver tpo_td043_ops = { .set_mirror = tpo_td043_set_hmirror, .get_mirror = tpo_td043_get_hmirror, - - .get_resolution = omapdss_default_get_resolution, }; static int tpo_td043_probe_of(struct spi_device *spi) diff --git a/drivers/gpu/drm/omapdrm/dss/Kconfig b/drivers/gpu/drm/omapdrm/dss/Kconfig index f53adb944a0d..8b87d5cf45fc 100644 --- a/drivers/gpu/drm/omapdrm/dss/Kconfig +++ b/drivers/gpu/drm/omapdrm/dss/Kconfig @@ -49,19 +49,6 @@ config OMAP2_DSS_DPI help DPI Interface. This is the Parallel Display Interface. -config OMAP2_DSS_RFBI - bool "RFBI support" - depends on BROKEN - default n - help - MIPI DBI support (RFBI, Remote Framebuffer Interface, in Texas - Instrument's terminology). - - DBI is a bus between the host processor and a peripheral, - such as a display or a framebuffer chip. - - See http://www.mipi.org/ for DBI specifications. - config OMAP2_DSS_VENC bool "VENC support" default y diff --git a/drivers/gpu/drm/omapdrm/dss/Makefile b/drivers/gpu/drm/omapdrm/dss/Makefile index 75ec30f231c7..142ce5a02542 100644 --- a/drivers/gpu/drm/omapdrm/dss/Makefile +++ b/drivers/gpu/drm/omapdrm/dss/Makefile @@ -5,10 +5,9 @@ omapdss-base-y := base.o display.o dss-of.o output.o obj-$(CONFIG_OMAP2_DSS) += omapdss.o # Core DSS files -omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o \ +omapdss-y := core.o dss.o dispc.o dispc_coefs.o \ pll.o video-pll.o omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o -omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o diff --git a/drivers/gpu/drm/omapdrm/dss/core.c b/drivers/gpu/drm/omapdrm/dss/core.c index 6a3ebfcd7223..197ddbc1512b 100644 --- a/drivers/gpu/drm/omapdrm/dss/core.c +++ b/drivers/gpu/drm/omapdrm/dss/core.c @@ -24,205 +24,10 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/clk.h> -#include <linux/err.h> #include <linux/platform_device.h> -#include <linux/seq_file.h> -#include <linux/debugfs.h> -#include <linux/io.h> -#include <linux/device.h> -#include <linux/regulator/consumer.h> -#include <linux/suspend.h> -#include <linux/slab.h> #include "omapdss.h" #include "dss.h" -#include "dss_features.h" - -static struct { - struct platform_device *pdev; - - const char *default_display_name; -} core; - -static char *def_disp_name; -module_param_named(def_disp, def_disp_name, charp, 0); -MODULE_PARM_DESC(def_disp, "default display name"); - -const char *omapdss_get_default_display_name(void) -{ - return core.default_display_name; -} -EXPORT_SYMBOL(omapdss_get_default_display_name); - -enum omapdss_version omapdss_get_version(void) -{ - struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; - return pdata->version; -} -EXPORT_SYMBOL(omapdss_get_version); - -struct platform_device *dss_get_core_pdev(void) -{ - return core.pdev; -} - -int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask) -{ - struct omap_dss_board_info *board_data = core.pdev->dev.platform_data; - - if (!board_data->dsi_enable_pads) - return -ENOENT; - - return board_data->dsi_enable_pads(dsi_id, lane_mask); -} - -void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask) -{ - struct omap_dss_board_info *board_data = core.pdev->dev.platform_data; - - if (!board_data->dsi_disable_pads) - return; - - return board_data->dsi_disable_pads(dsi_id, lane_mask); -} - -int dss_set_min_bus_tput(struct device *dev, unsigned long tput) -{ - struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; - - if (pdata->set_min_bus_tput) - return pdata->set_min_bus_tput(dev, tput); - else - return 0; -} - -#if defined(CONFIG_OMAP2_DSS_DEBUGFS) -static int dss_debug_show(struct seq_file *s, void *unused) -{ - void (*func)(struct seq_file *) = s->private; - func(s); - return 0; -} - -static int dss_debug_open(struct inode *inode, struct file *file) -{ - return single_open(file, dss_debug_show, inode->i_private); -} - -static const struct file_operations dss_debug_fops = { - .open = dss_debug_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static struct dentry *dss_debugfs_dir; - -static int dss_initialize_debugfs(void) -{ - dss_debugfs_dir = debugfs_create_dir("omapdss", NULL); - if (IS_ERR(dss_debugfs_dir)) { - int err = PTR_ERR(dss_debugfs_dir); - dss_debugfs_dir = NULL; - return err; - } - - debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir, - &dss_debug_dump_clocks, &dss_debug_fops); - - return 0; -} - -static void dss_uninitialize_debugfs(void) -{ - if (dss_debugfs_dir) - debugfs_remove_recursive(dss_debugfs_dir); -} - -int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)) -{ - struct dentry *d; - - d = debugfs_create_file(name, S_IRUGO, dss_debugfs_dir, - write, &dss_debug_fops); - - return PTR_ERR_OR_ZERO(d); -} -#else /* CONFIG_OMAP2_DSS_DEBUGFS */ -static inline int dss_initialize_debugfs(void) -{ - return 0; -} -static inline void dss_uninitialize_debugfs(void) -{ -} -int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)) -{ - return 0; -} -#endif /* CONFIG_OMAP2_DSS_DEBUGFS */ - -/* PLATFORM DEVICE */ - -static void dss_disable_all_devices(void) -{ - struct omap_dss_device *dssdev = NULL; - - for_each_dss_dev(dssdev) { - if (!dssdev->driver) - continue; - - if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) - dssdev->driver->disable(dssdev); - } -} - -static int __init omap_dss_probe(struct platform_device *pdev) -{ - struct omap_dss_board_info *pdata = pdev->dev.platform_data; - int r; - - core.pdev = pdev; - - dss_features_init(omapdss_get_version()); - - r = dss_initialize_debugfs(); - if (r) - goto err_debugfs; - - if (def_disp_name) - core.default_display_name = def_disp_name; - else if (pdata->default_display_name) - core.default_display_name = pdata->default_display_name; - - return 0; - -err_debugfs: - - return r; -} - -static int omap_dss_remove(struct platform_device *pdev) -{ - dss_uninitialize_debugfs(); - - return 0; -} - -static void omap_dss_shutdown(struct platform_device *pdev) -{ - DSSDBG("shutdown\n"); - dss_disable_all_devices(); -} - -static struct platform_driver omap_dss_driver = { - .remove = omap_dss_remove, - .shutdown = omap_dss_shutdown, - .driver = { - .name = "omapdss", - }, -}; /* INIT */ static int (*dss_output_drv_reg_funcs[])(void) __initdata = { @@ -231,15 +36,6 @@ static int (*dss_output_drv_reg_funcs[])(void) __initdata = { #ifdef CONFIG_OMAP2_DSS_DSI dsi_init_platform_driver, #endif -#ifdef CONFIG_OMAP2_DSS_DPI - dpi_init_platform_driver, -#endif -#ifdef CONFIG_OMAP2_DSS_SDI - sdi_init_platform_driver, -#endif -#ifdef CONFIG_OMAP2_DSS_RFBI - rfbi_init_platform_driver, -#endif #ifdef CONFIG_OMAP2_DSS_VENC venc_init_platform_driver, #endif @@ -261,15 +57,6 @@ static void (*dss_output_drv_unreg_funcs[])(void) = { #ifdef CONFIG_OMAP2_DSS_VENC venc_uninit_platform_driver, #endif -#ifdef CONFIG_OMAP2_DSS_RFBI - rfbi_uninit_platform_driver, -#endif -#ifdef CONFIG_OMAP2_DSS_SDI - sdi_uninit_platform_driver, -#endif -#ifdef CONFIG_OMAP2_DSS_DPI - dpi_uninit_platform_driver, -#endif #ifdef CONFIG_OMAP2_DSS_DSI dsi_uninit_platform_driver, #endif @@ -277,21 +64,25 @@ static void (*dss_output_drv_unreg_funcs[])(void) = { dss_uninit_platform_driver, }; +static struct platform_device *omap_drm_device; + static int __init omap_dss_init(void) { int r; int i; - r = platform_driver_probe(&omap_dss_driver, omap_dss_probe); - if (r) - return r; - for (i = 0; i < ARRAY_SIZE(dss_output_drv_reg_funcs); ++i) { r = dss_output_drv_reg_funcs[i](); if (r) goto err_reg; } + omap_drm_device = platform_device_register_simple("omapdrm", 0, NULL, 0); + if (IS_ERR(omap_drm_device)) { + r = PTR_ERR(omap_drm_device); + goto err_reg; + } + return 0; err_reg: @@ -300,8 +91,6 @@ err_reg: ++i) dss_output_drv_unreg_funcs[i](); - platform_driver_unregister(&omap_dss_driver); - return r; } @@ -309,10 +98,10 @@ static void __exit omap_dss_exit(void) { int i; + platform_device_unregister(omap_drm_device); + for (i = 0; i < ARRAY_SIZE(dss_output_drv_unreg_funcs); ++i) dss_output_drv_unreg_funcs[i](); - - platform_driver_unregister(&omap_dss_driver); } module_init(omap_dss_init); diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 5ac0145fbae6..0f4fdb221498 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -39,11 +39,14 @@ #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/component.h> +#include <linux/sys_soc.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_blend.h> #include "omapdss.h" #include "dss.h" -#include "dss_features.h" #include "dispc.h" /* DISPC */ @@ -61,6 +64,33 @@ enum omap_burst_size { #define REG_FLD_MOD(idx, val, start, end) \ dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) +/* DISPC has feature id */ +enum dispc_feature_id { + FEAT_LCDENABLEPOL, + FEAT_LCDENABLESIGNAL, + FEAT_PCKFREEENABLE, + FEAT_FUNCGATED, + FEAT_MGR_LCD2, + FEAT_MGR_LCD3, + FEAT_LINEBUFFERSPLIT, + FEAT_ROWREPEATENABLE, + FEAT_RESIZECONF, + /* Independent core clk divider */ + FEAT_CORE_CLK_DIV, + FEAT_HANDLE_UV_SEPARATE, + FEAT_ATTR2, + FEAT_CPR, + FEAT_PRELOAD, + FEAT_FIR_COEF_V, + FEAT_ALPHA_FIXED_ZORDER, + FEAT_ALPHA_FREE_ZORDER, + FEAT_FIFO_MERGE, + /* An unknown HW bug causing the normal FIFO thresholds not to work */ + FEAT_OMAP3_DSI_FIFO_BUG, + FEAT_BURST_2D, + FEAT_MFLAG, +}; + struct dispc_features { u8 sw_start; u8 fp_start; @@ -74,16 +104,29 @@ struct dispc_features { u16 mgr_height_max; unsigned long max_lcd_pclk; unsigned long max_tv_pclk; + unsigned int max_downscale; + unsigned int max_line_width; + unsigned int min_pcd; int (*calc_scaling) (unsigned long pclk, unsigned long lclk, const struct videomode *vm, u16 width, u16 height, u16 out_width, u16 out_height, - enum omap_color_mode color_mode, bool *five_taps, + u32 fourcc, bool *five_taps, int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, u16 pos_x, unsigned long *core_clk, bool mem_to_mem); unsigned long (*calc_core_clk) (unsigned long pclk, u16 width, u16 height, u16 out_width, u16 out_height, bool mem_to_mem); u8 num_fifos; + const enum dispc_feature_id *features; + unsigned int num_features; + const struct dss_reg_field *reg_fields; + const unsigned int num_reg_fields; + const enum omap_overlay_caps *overlay_caps; + const u32 **supported_color_modes; + unsigned int num_mgrs; + unsigned int num_ovls; + unsigned int buffer_size_unit; + unsigned int burst_size_unit; /* swap GFX & WB fifos */ bool gfx_fifo_workaround:1; @@ -158,7 +201,7 @@ enum omap_color_component { */ DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, /* used for UV component for - * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 + * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12 * color formats on OMAP4 */ DISPC_COLOR_COMPONENT_UV = 1 << 1, @@ -178,6 +221,17 @@ enum mgr_reg_fields { DISPC_MGR_FLD_NUM, }; +/* DISPC register field id */ +enum dispc_feat_reg_field { + FEAT_REG_FIRHINC, + FEAT_REG_FIRVINC, + FEAT_REG_FIFOHIGHTHRESHOLD, + FEAT_REG_FIFOLOWTHRESHOLD, + FEAT_REG_FIFOSIZE, + FEAT_REG_HORIZONTALACCU, + FEAT_REG_VERTICALACCU, +}; + struct dispc_reg_field { u16 reg; u8 high; @@ -341,6 +395,38 @@ static void mgr_fld_write(enum omap_channel channel, spin_unlock_irqrestore(&dispc.control_lock, flags); } +static int dispc_get_num_ovls(void) +{ + return dispc.feat->num_ovls; +} + +static int dispc_get_num_mgrs(void) +{ + return dispc.feat->num_mgrs; +} + +static void dispc_get_reg_field(enum dispc_feat_reg_field id, + u8 *start, u8 *end) +{ + if (id >= dispc.feat->num_reg_fields) + BUG(); + + *start = dispc.feat->reg_fields[id].start; + *end = dispc.feat->reg_fields[id].end; +} + +static bool dispc_has_feature(enum dispc_feature_id id) +{ + unsigned int i; + + for (i = 0; i < dispc.feat->num_features; i++) { + if (dispc.feat->features[i] == id) + return true; + } + + return false; +} + #define SR(reg) \ dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) #define RR(reg) \ @@ -356,19 +442,19 @@ static void dispc_save_context(void) SR(CONTROL); SR(CONFIG); SR(LINE_NUMBER); - if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || - dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) + if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || + dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) SR(GLOBAL_ALPHA); - if (dss_has_feature(FEAT_MGR_LCD2)) { + if (dispc_has_feature(FEAT_MGR_LCD2)) { SR(CONTROL2); SR(CONFIG2); } - if (dss_has_feature(FEAT_MGR_LCD3)) { + if (dispc_has_feature(FEAT_MGR_LCD3)) { SR(CONTROL3); SR(CONFIG3); } - for (i = 0; i < dss_feat_get_num_mgrs(); i++) { + for (i = 0; i < dispc_get_num_mgrs(); i++) { SR(DEFAULT_COLOR(i)); SR(TRANS_COLOR(i)); SR(SIZE_MGR(i)); @@ -383,14 +469,14 @@ static void dispc_save_context(void) SR(DATA_CYCLE2(i)); SR(DATA_CYCLE3(i)); - if (dss_has_feature(FEAT_CPR)) { + if (dispc_has_feature(FEAT_CPR)) { SR(CPR_COEF_R(i)); SR(CPR_COEF_G(i)); SR(CPR_COEF_B(i)); } } - for (i = 0; i < dss_feat_get_num_ovls(); i++) { + for (i = 0; i < dispc_get_num_ovls(); i++) { SR(OVL_BA0(i)); SR(OVL_BA1(i)); SR(OVL_POSITION(i)); @@ -399,7 +485,7 @@ static void dispc_save_context(void) SR(OVL_FIFO_THRESHOLD(i)); SR(OVL_ROW_INC(i)); SR(OVL_PIXEL_INC(i)); - if (dss_has_feature(FEAT_PRELOAD)) + if (dispc_has_feature(FEAT_PRELOAD)) SR(OVL_PRELOAD(i)); if (i == OMAP_DSS_GFX) { SR(OVL_WINDOW_SKIP(i)); @@ -420,12 +506,12 @@ static void dispc_save_context(void) for (j = 0; j < 5; j++) SR(OVL_CONV_COEF(i, j)); - if (dss_has_feature(FEAT_FIR_COEF_V)) { + if (dispc_has_feature(FEAT_FIR_COEF_V)) { for (j = 0; j < 8; j++) SR(OVL_FIR_COEF_V(i, j)); } - if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { + if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { SR(OVL_BA0_UV(i)); SR(OVL_BA1_UV(i)); SR(OVL_FIR2(i)); @@ -441,11 +527,11 @@ static void dispc_save_context(void) for (j = 0; j < 8; j++) SR(OVL_FIR_COEF_V2(i, j)); } - if (dss_has_feature(FEAT_ATTR2)) + if (dispc_has_feature(FEAT_ATTR2)) SR(OVL_ATTRIBUTES2(i)); } - if (dss_has_feature(FEAT_CORE_CLK_DIV)) + if (dispc_has_feature(FEAT_CORE_CLK_DIV)) SR(DIVISOR); dispc.ctx_valid = true; @@ -466,15 +552,15 @@ static void dispc_restore_context(void) /*RR(CONTROL);*/ RR(CONFIG); RR(LINE_NUMBER); - if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || - dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) + if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || + dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) RR(GLOBAL_ALPHA); - if (dss_has_feature(FEAT_MGR_LCD2)) + if (dispc_has_feature(FEAT_MGR_LCD2)) RR(CONFIG2); - if (dss_has_feature(FEAT_MGR_LCD3)) + if (dispc_has_feature(FEAT_MGR_LCD3)) RR(CONFIG3); - for (i = 0; i < dss_feat_get_num_mgrs(); i++) { + for (i = 0; i < dispc_get_num_mgrs(); i++) { RR(DEFAULT_COLOR(i)); RR(TRANS_COLOR(i)); RR(SIZE_MGR(i)); @@ -489,14 +575,14 @@ static void dispc_restore_context(void) RR(DATA_CYCLE2(i)); RR(DATA_CYCLE3(i)); - if (dss_has_feature(FEAT_CPR)) { + if (dispc_has_feature(FEAT_CPR)) { RR(CPR_COEF_R(i)); RR(CPR_COEF_G(i)); RR(CPR_COEF_B(i)); } } - for (i = 0; i < dss_feat_get_num_ovls(); i++) { + for (i = 0; i < dispc_get_num_ovls(); i++) { RR(OVL_BA0(i)); RR(OVL_BA1(i)); RR(OVL_POSITION(i)); @@ -505,7 +591,7 @@ static void dispc_restore_context(void) RR(OVL_FIFO_THRESHOLD(i)); RR(OVL_ROW_INC(i)); RR(OVL_PIXEL_INC(i)); - if (dss_has_feature(FEAT_PRELOAD)) + if (dispc_has_feature(FEAT_PRELOAD)) RR(OVL_PRELOAD(i)); if (i == OMAP_DSS_GFX) { RR(OVL_WINDOW_SKIP(i)); @@ -526,12 +612,12 @@ static void dispc_restore_context(void) for (j = 0; j < 5; j++) RR(OVL_CONV_COEF(i, j)); - if (dss_has_feature(FEAT_FIR_COEF_V)) { + if (dispc_has_feature(FEAT_FIR_COEF_V)) { for (j = 0; j < 8; j++) RR(OVL_FIR_COEF_V(i, j)); } - if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { + if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { RR(OVL_BA0_UV(i)); RR(OVL_BA1_UV(i)); RR(OVL_FIR2(i)); @@ -547,18 +633,18 @@ static void dispc_restore_context(void) for (j = 0; j < 8; j++) RR(OVL_FIR_COEF_V2(i, j)); } - if (dss_has_feature(FEAT_ATTR2)) + if (dispc_has_feature(FEAT_ATTR2)) RR(OVL_ATTRIBUTES2(i)); } - if (dss_has_feature(FEAT_CORE_CLK_DIV)) + if (dispc_has_feature(FEAT_CORE_CLK_DIV)) RR(DIVISOR); /* enable last, because LCD & DIGIT enable are here */ RR(CONTROL); - if (dss_has_feature(FEAT_MGR_LCD2)) + if (dispc_has_feature(FEAT_MGR_LCD2)) RR(CONTROL2); - if (dss_has_feature(FEAT_MGR_LCD3)) + if (dispc_has_feature(FEAT_MGR_LCD3)) RR(CONTROL3); /* clear spurious SYNC_LOST_DIGIT interrupts */ dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); @@ -777,7 +863,7 @@ static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane, static void dispc_setup_color_conv_coef(void) { int i; - int num_ovl = dss_feat_get_num_ovls(); + int num_ovl = dispc_get_num_ovls(); const struct color_conv_coef ctbl_bt601_5_ovl = { /* YUV -> RGB */ 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, @@ -866,10 +952,10 @@ static void dispc_ovl_enable_zorder_planes(void) { int i; - if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) + if (!dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) return; - for (i = 0; i < dss_feat_get_num_ovls(); i++) + for (i = 0; i < dispc_get_num_ovls(); i++) REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); } @@ -905,78 +991,69 @@ static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc) dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); } -static void dispc_ovl_set_color_mode(enum omap_plane_id plane, - enum omap_color_mode color_mode) +static void dispc_ovl_set_color_mode(enum omap_plane_id plane, u32 fourcc) { u32 m = 0; if (plane != OMAP_DSS_GFX) { - switch (color_mode) { - case OMAP_DSS_COLOR_NV12: + switch (fourcc) { + case DRM_FORMAT_NV12: m = 0x0; break; - case OMAP_DSS_COLOR_RGBX16: + case DRM_FORMAT_XRGB4444: m = 0x1; break; - case OMAP_DSS_COLOR_RGBA16: + case DRM_FORMAT_RGBA4444: m = 0x2; break; - case OMAP_DSS_COLOR_RGB12U: + case DRM_FORMAT_RGBX4444: m = 0x4; break; - case OMAP_DSS_COLOR_ARGB16: + case DRM_FORMAT_ARGB4444: m = 0x5; break; - case OMAP_DSS_COLOR_RGB16: + case DRM_FORMAT_RGB565: m = 0x6; break; - case OMAP_DSS_COLOR_ARGB16_1555: + case DRM_FORMAT_ARGB1555: m = 0x7; break; - case OMAP_DSS_COLOR_RGB24U: + case DRM_FORMAT_XRGB8888: m = 0x8; break; - case OMAP_DSS_COLOR_RGB24P: + case DRM_FORMAT_RGB888: m = 0x9; break; - case OMAP_DSS_COLOR_YUV2: + case DRM_FORMAT_YUYV: m = 0xa; break; - case OMAP_DSS_COLOR_UYVY: + case DRM_FORMAT_UYVY: m = 0xb; break; - case OMAP_DSS_COLOR_ARGB32: + case DRM_FORMAT_ARGB8888: m = 0xc; break; - case OMAP_DSS_COLOR_RGBA32: + case DRM_FORMAT_RGBA8888: m = 0xd; break; - case OMAP_DSS_COLOR_RGBX32: + case DRM_FORMAT_RGBX8888: m = 0xe; break; - case OMAP_DSS_COLOR_XRGB16_1555: + case DRM_FORMAT_XRGB1555: m = 0xf; break; default: BUG(); return; } } else { - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - m = 0x0; break; - case OMAP_DSS_COLOR_CLUT2: - m = 0x1; break; - case OMAP_DSS_COLOR_CLUT4: - m = 0x2; break; - case OMAP_DSS_COLOR_CLUT8: - m = 0x3; break; - case OMAP_DSS_COLOR_RGB12U: + switch (fourcc) { + case DRM_FORMAT_RGBX4444: m = 0x4; break; - case OMAP_DSS_COLOR_ARGB16: + case DRM_FORMAT_ARGB4444: m = 0x5; break; - case OMAP_DSS_COLOR_RGB16: + case DRM_FORMAT_RGB565: m = 0x6; break; - case OMAP_DSS_COLOR_ARGB16_1555: + case DRM_FORMAT_ARGB1555: m = 0x7; break; - case OMAP_DSS_COLOR_RGB24U: + case DRM_FORMAT_XRGB8888: m = 0x8; break; - case OMAP_DSS_COLOR_RGB24P: + case DRM_FORMAT_RGB888: m = 0x9; break; - case OMAP_DSS_COLOR_RGBX16: + case DRM_FORMAT_XRGB4444: m = 0xa; break; - case OMAP_DSS_COLOR_RGBA16: + case DRM_FORMAT_RGBA4444: m = 0xb; break; - case OMAP_DSS_COLOR_ARGB32: + case DRM_FORMAT_ARGB8888: m = 0xc; break; - case OMAP_DSS_COLOR_RGBA32: + case DRM_FORMAT_RGBA8888: m = 0xd; break; - case OMAP_DSS_COLOR_RGBX32: + case DRM_FORMAT_RGBX8888: m = 0xe; break; - case OMAP_DSS_COLOR_XRGB16_1555: + case DRM_FORMAT_XRGB1555: m = 0xf; break; default: BUG(); return; @@ -986,10 +1063,22 @@ static void dispc_ovl_set_color_mode(enum omap_plane_id plane, REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); } +static bool format_is_yuv(u32 fourcc) +{ + switch (fourcc) { + case DRM_FORMAT_YUYV: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_NV12: + return true; + default: + return false; + } +} + static void dispc_ovl_configure_burst_type(enum omap_plane_id plane, enum omap_dss_rotation_type rotation_type) { - if (dss_has_feature(FEAT_BURST_2D) == 0) + if (dispc_has_feature(FEAT_BURST_2D) == 0) return; if (rotation_type == OMAP_DSS_ROT_TILER) @@ -1020,7 +1109,7 @@ static void dispc_ovl_set_channel_out(enum omap_plane_id plane, } val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); - if (dss_has_feature(FEAT_MGR_LCD2)) { + if (dispc_has_feature(FEAT_MGR_LCD2)) { switch (channel) { case OMAP_DSS_CHANNEL_LCD: chan = 0; @@ -1035,7 +1124,7 @@ static void dispc_ovl_set_channel_out(enum omap_plane_id plane, chan2 = 1; break; case OMAP_DSS_CHANNEL_LCD3: - if (dss_has_feature(FEAT_MGR_LCD3)) { + if (dispc_has_feature(FEAT_MGR_LCD3)) { chan = 0; chan2 = 2; } else { @@ -1084,7 +1173,7 @@ static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane) if (FLD_GET(val, shift, shift) == 1) return OMAP_DSS_CHANNEL_DIGIT; - if (!dss_has_feature(FEAT_MGR_LCD2)) + if (!dispc_has_feature(FEAT_MGR_LCD2)) return OMAP_DSS_CHANNEL_LCD; switch (FLD_GET(val, 31, 30)) { @@ -1123,7 +1212,7 @@ static void dispc_configure_burst_sizes(void) const int burst_size = BURST_SIZE_X8; /* Configure burst size always to maximum size */ - for (i = 0; i < dss_feat_get_num_ovls(); ++i) + for (i = 0; i < dispc_get_num_ovls(); ++i) dispc_ovl_set_burst_size(i, burst_size); if (dispc.feat->has_writeback) dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); @@ -1131,19 +1220,28 @@ static void dispc_configure_burst_sizes(void) static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane) { - unsigned unit = dss_feat_get_burst_size_unit(); /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ - return unit * 8; + return dispc.feat->burst_size_unit * 8; } -static enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane_id plane) +static bool dispc_ovl_color_mode_supported(enum omap_plane_id plane, u32 fourcc) { - return dss_feat_get_supported_color_modes(plane); + const u32 *modes; + unsigned int i; + + modes = dispc.feat->supported_color_modes[plane]; + + for (i = 0; modes[i]; ++i) { + if (modes[i] == fourcc) + return true; + } + + return false; } -static int dispc_get_num_ovls(void) +static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane) { - return dss_feat_get_num_ovls(); + return dispc.feat->supported_color_modes[plane]; } static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) @@ -1218,9 +1316,9 @@ static void dispc_init_fifos(void) u32 unit; int i; - unit = dss_feat_get_buffer_size_unit(); + unit = dispc.feat->buffer_size_unit; - dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); + dispc_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); @@ -1260,7 +1358,7 @@ static void dispc_init_fifos(void) /* * Setup default fifo thresholds. */ - for (i = 0; i < dss_feat_get_num_ovls(); ++i) { + for (i = 0; i < dispc_get_num_ovls(); ++i) { u32 low, high; const bool use_fifomerge = false; const bool manual_update = false; @@ -1302,7 +1400,7 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, u8 hi_start, hi_end, lo_start, lo_end; u32 unit; - unit = dss_feat_get_buffer_size_unit(); + unit = dispc.feat->buffer_size_unit; WARN_ON(low % unit != 0); WARN_ON(high % unit != 0); @@ -1310,8 +1408,8 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, low /= unit; high /= unit; - dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); - dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); + dispc_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); + dispc_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", plane, @@ -1330,14 +1428,14 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, * large for the preload field, set the threshold to the maximum value * that can be held by the preload register */ - if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && + if (dispc_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && plane != OMAP_DSS_WB) dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); } void dispc_enable_fifomerge(bool enable) { - if (!dss_has_feature(FEAT_FIFO_MERGE)) { + if (!dispc_has_feature(FEAT_FIFO_MERGE)) { WARN_ON(enable); return; } @@ -1355,7 +1453,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, * buffer_units, and the fifo thresholds must be buffer_unit aligned. */ - unsigned buf_unit = dss_feat_get_buffer_size_unit(); + unsigned buf_unit = dispc.feat->buffer_size_unit; unsigned ovl_fifo_size, total_fifo_size, burst_size; int i; @@ -1364,7 +1462,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, if (use_fifomerge) { total_fifo_size = 0; - for (i = 0; i < dss_feat_get_num_ovls(); ++i) + for (i = 0; i < dispc_get_num_ovls(); ++i) total_fifo_size += dispc_ovl_get_fifo_size(i); } else { total_fifo_size = ovl_fifo_size; @@ -1376,7 +1474,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, * combined fifo size */ - if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { + if (manual_update && dispc_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { *fifo_low = ovl_fifo_size - burst_size * 2; *fifo_high = total_fifo_size - burst_size; } else if (plane == OMAP_DSS_WB) { @@ -1430,9 +1528,9 @@ static void dispc_init_mflag(void) (1 << 0) | /* MFLAG_CTRL = force always on */ (0 << 2)); /* MFLAG_START = disable */ - for (i = 0; i < dss_feat_get_num_ovls(); ++i) { + for (i = 0; i < dispc_get_num_ovls(); ++i) { u32 size = dispc_ovl_get_fifo_size(i); - u32 unit = dss_feat_get_buffer_size_unit(); + u32 unit = dispc.feat->buffer_size_unit; u32 low, high; dispc_ovl_set_mflag(i, true); @@ -1451,7 +1549,7 @@ static void dispc_init_mflag(void) if (dispc.feat->has_writeback) { u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB); - u32 unit = dss_feat_get_buffer_size_unit(); + u32 unit = dispc.feat->buffer_size_unit; u32 low, high; dispc_ovl_set_mflag(OMAP_DSS_WB, true); @@ -1478,10 +1576,8 @@ static void dispc_ovl_set_fir(enum omap_plane_id plane, if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { u8 hinc_start, hinc_end, vinc_start, vinc_end; - dss_feat_get_reg_field(FEAT_REG_FIRHINC, - &hinc_start, &hinc_end); - dss_feat_get_reg_field(FEAT_REG_FIRVINC, - &vinc_start, &vinc_end); + dispc_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end); + dispc_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end); val = FLD_VAL(vinc, vinc_start, vinc_end) | FLD_VAL(hinc, hinc_start, hinc_end); @@ -1498,8 +1594,8 @@ static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu, u32 val; u8 hor_start, hor_end, vert_start, vert_end; - dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); - dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); + dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); + dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); val = FLD_VAL(vaccu, vert_start, vert_end) | FLD_VAL(haccu, hor_start, hor_end); @@ -1513,8 +1609,8 @@ static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu, u32 val; u8 hor_start, hor_end, vert_start, vert_end; - dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); - dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); + dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); + dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); val = FLD_VAL(vaccu, vert_start, vert_end) | FLD_VAL(haccu, hor_start, hor_end); @@ -1558,7 +1654,7 @@ static void dispc_ovl_set_scale_param(enum omap_plane_id plane, static void dispc_ovl_set_accu_uv(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, - bool ilace, enum omap_color_mode color_mode, u8 rotation) + bool ilace, u32 fourcc, u8 rotation) { int h_accu2_0, h_accu2_1; int v_accu2_0, v_accu2_1; @@ -1596,33 +1692,32 @@ static void dispc_ovl_set_accu_uv(enum omap_plane_id plane, { 0, 1, 0, 1, -1, 1, 0, 1 }, }; - switch (rotation) { - case OMAP_DSS_ROT_0: + /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ + switch (rotation & DRM_MODE_ROTATE_MASK) { + default: + case DRM_MODE_ROTATE_0: idx = 0; break; - case OMAP_DSS_ROT_90: - idx = 1; + case DRM_MODE_ROTATE_90: + idx = 3; break; - case OMAP_DSS_ROT_180: + case DRM_MODE_ROTATE_180: idx = 2; break; - case OMAP_DSS_ROT_270: - idx = 3; + case DRM_MODE_ROTATE_270: + idx = 1; break; - default: - BUG(); - return; } - switch (color_mode) { - case OMAP_DSS_COLOR_NV12: + switch (fourcc) { + case DRM_FORMAT_NV12: if (ilace) accu_table = accu_nv12_ilace; else accu_table = accu_nv12; break; - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_UYVY: accu_table = accu_yuv; break; default: @@ -1648,7 +1743,7 @@ static void dispc_ovl_set_scaling_common(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, bool ilace, bool five_taps, - bool fieldmode, enum omap_color_mode color_mode, + bool fieldmode, u32 fourcc, u8 rotation) { int accu0 = 0; @@ -1667,14 +1762,14 @@ static void dispc_ovl_set_scaling_common(enum omap_plane_id plane, l |= five_taps ? (1 << 21) : 0; /* VRESIZECONF and HRESIZECONF */ - if (dss_has_feature(FEAT_RESIZECONF)) { + if (dispc_has_feature(FEAT_RESIZECONF)) { l &= ~(0x3 << 7); l |= (orig_width <= out_width) ? 0 : (1 << 7); l |= (orig_height <= out_height) ? 0 : (1 << 8); } /* LINEBUFFERSPLIT */ - if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { + if (dispc_has_feature(FEAT_LINEBUFFERSPLIT)) { l &= ~(0x1 << 22); l |= five_taps ? (1 << 22) : 0; } @@ -1702,18 +1797,17 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, bool ilace, bool five_taps, - bool fieldmode, enum omap_color_mode color_mode, + bool fieldmode, u32 fourcc, u8 rotation) { int scale_x = out_width != orig_width; int scale_y = out_height != orig_height; bool chroma_upscale = plane != OMAP_DSS_WB; - if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) + if (!dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) return; - if ((color_mode != OMAP_DSS_COLOR_YUV2 && - color_mode != OMAP_DSS_COLOR_UYVY && - color_mode != OMAP_DSS_COLOR_NV12)) { + + if (!format_is_yuv(fourcc)) { /* reset chroma resampling for RGB formats */ if (plane != OMAP_DSS_WB) REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); @@ -1721,10 +1815,10 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane, } dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, - out_height, ilace, color_mode, rotation); + out_height, ilace, fourcc, rotation); - switch (color_mode) { - case OMAP_DSS_COLOR_NV12: + switch (fourcc) { + case DRM_FORMAT_NV12: if (chroma_upscale) { /* UV is subsampled by 2 horizontally and vertically */ orig_height >>= 1; @@ -1736,11 +1830,10 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane, } break; - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_UYVY: /* For YUV422 with 90/270 rotation, we don't upsample chroma */ - if (rotation == OMAP_DSS_ROT_0 || - rotation == OMAP_DSS_ROT_180) { + if (!drm_rotation_90_or_270(rotation)) { if (chroma_upscale) /* UV is subsampled by 2 horizontally */ orig_width >>= 1; @@ -1750,7 +1843,7 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane, } /* must use FIR for YUV422 if rotated */ - if (rotation != OMAP_DSS_ROT_0) + if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0) scale_x = scale_y = true; break; @@ -1782,7 +1875,7 @@ static void dispc_ovl_set_scaling(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, bool ilace, bool five_taps, - bool fieldmode, enum omap_color_mode color_mode, + bool fieldmode, u32 fourcc, u8 rotation) { BUG_ON(plane == OMAP_DSS_GFX); @@ -1791,60 +1884,59 @@ static void dispc_ovl_set_scaling(enum omap_plane_id plane, orig_width, orig_height, out_width, out_height, ilace, five_taps, - fieldmode, color_mode, + fieldmode, fourcc, rotation); dispc_ovl_set_scaling_uv(plane, orig_width, orig_height, out_width, out_height, ilace, five_taps, - fieldmode, color_mode, + fieldmode, fourcc, rotation); } static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation, - enum omap_dss_rotation_type rotation_type, - bool mirroring, enum omap_color_mode color_mode) + enum omap_dss_rotation_type rotation_type, u32 fourcc) { bool row_repeat = false; int vidrot = 0; - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) { + /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ + if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) { - if (mirroring) { - switch (rotation) { - case OMAP_DSS_ROT_0: + if (rotation & DRM_MODE_REFLECT_X) { + switch (rotation & DRM_MODE_ROTATE_MASK) { + case DRM_MODE_ROTATE_0: vidrot = 2; break; - case OMAP_DSS_ROT_90: + case DRM_MODE_ROTATE_90: vidrot = 1; break; - case OMAP_DSS_ROT_180: + case DRM_MODE_ROTATE_180: vidrot = 0; break; - case OMAP_DSS_ROT_270: + case DRM_MODE_ROTATE_270: vidrot = 3; break; } } else { - switch (rotation) { - case OMAP_DSS_ROT_0: + switch (rotation & DRM_MODE_ROTATE_MASK) { + case DRM_MODE_ROTATE_0: vidrot = 0; break; - case OMAP_DSS_ROT_90: - vidrot = 1; + case DRM_MODE_ROTATE_90: + vidrot = 3; break; - case OMAP_DSS_ROT_180: + case DRM_MODE_ROTATE_180: vidrot = 2; break; - case OMAP_DSS_ROT_270: - vidrot = 3; + case DRM_MODE_ROTATE_270: + vidrot = 1; break; } } - if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) + if (drm_rotation_90_or_270(rotation)) row_repeat = true; else row_repeat = false; @@ -1855,53 +1947,46 @@ static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation, * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra * rows beyond the framebuffer, which may cause OCP error. */ - if (color_mode == OMAP_DSS_COLOR_NV12 && - rotation_type != OMAP_DSS_ROT_TILER) + if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER) vidrot = 1; REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); - if (dss_has_feature(FEAT_ROWREPEATENABLE)) + if (dispc_has_feature(FEAT_ROWREPEATENABLE)) REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), row_repeat ? 1 : 0, 18, 18); - if (color_mode == OMAP_DSS_COLOR_NV12) { - bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) && - (rotation == OMAP_DSS_ROT_0 || - rotation == OMAP_DSS_ROT_180); + if (dispc_ovl_color_mode_supported(plane, DRM_FORMAT_NV12)) { + bool doublestride = + fourcc == DRM_FORMAT_NV12 && + rotation_type == OMAP_DSS_ROT_TILER && + !drm_rotation_90_or_270(rotation); + /* DOUBLESTRIDE */ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); } - } -static int color_mode_to_bpp(enum omap_color_mode color_mode) +static int color_mode_to_bpp(u32 fourcc) { - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - return 1; - case OMAP_DSS_COLOR_CLUT2: - return 2; - case OMAP_DSS_COLOR_CLUT4: - return 4; - case OMAP_DSS_COLOR_CLUT8: - case OMAP_DSS_COLOR_NV12: + switch (fourcc) { + case DRM_FORMAT_NV12: return 8; - case OMAP_DSS_COLOR_RGB12U: - case OMAP_DSS_COLOR_RGB16: - case OMAP_DSS_COLOR_ARGB16: - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: - case OMAP_DSS_COLOR_RGBA16: - case OMAP_DSS_COLOR_RGBX16: - case OMAP_DSS_COLOR_ARGB16_1555: - case OMAP_DSS_COLOR_XRGB16_1555: + case DRM_FORMAT_RGBX4444: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_ARGB4444: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_RGBA4444: + case DRM_FORMAT_XRGB4444: + case DRM_FORMAT_ARGB1555: + case DRM_FORMAT_XRGB1555: return 16; - case OMAP_DSS_COLOR_RGB24P: + case DRM_FORMAT_RGB888: return 24; - case OMAP_DSS_COLOR_RGB24U: - case OMAP_DSS_COLOR_ARGB32: - case OMAP_DSS_COLOR_RGBA32: - case OMAP_DSS_COLOR_RGBX32: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBX8888: return 32; default: BUG(); @@ -1922,281 +2007,42 @@ static s32 pixinc(int pixels, u8 ps) return 0; } -static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, - u16 screen_width, - u16 width, u16 height, - enum omap_color_mode color_mode, bool fieldmode, - unsigned int field_offset, - unsigned *offset0, unsigned *offset1, - s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) +static void calc_offset(u16 screen_width, u16 width, + u32 fourcc, bool fieldmode, + unsigned int field_offset, unsigned *offset0, unsigned *offset1, + s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim, + enum omap_dss_rotation_type rotation_type, u8 rotation) { u8 ps; - /* FIXME CLUT formats */ - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - case OMAP_DSS_COLOR_CLUT2: - case OMAP_DSS_COLOR_CLUT4: - case OMAP_DSS_COLOR_CLUT8: - BUG(); - return; - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: - ps = 4; - break; - default: - ps = color_mode_to_bpp(color_mode) / 8; - break; - } + ps = color_mode_to_bpp(fourcc) / 8; - DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, - width, height); + DSSDBG("scrw %d, width %d\n", screen_width, width); - /* - * field 0 = even field = bottom field - * field 1 = odd field = top field - */ - switch (rotation + mirror * 4) { - case OMAP_DSS_ROT_0: - case OMAP_DSS_ROT_180: + if (rotation_type == OMAP_DSS_ROT_TILER && + (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) && + drm_rotation_90_or_270(rotation)) { /* - * If the pixel format is YUV or UYVY divide the width - * of the image by 2 for 0 and 180 degree rotation. + * HACK: ROW_INC needs to be calculated with TILER units. + * We get such 'screen_width' that multiplying it with the + * YUV422 pixel size gives the correct TILER container width. + * However, 'width' is in pixels and multiplying it with YUV422 + * pixel size gives incorrect result. We thus multiply it here + * with 2 to match the 32 bit TILER unit size. */ - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - width = width >> 1; - case OMAP_DSS_ROT_90: - case OMAP_DSS_ROT_270: - *offset1 = 0; - if (field_offset) - *offset0 = field_offset * screen_width * ps; - else - *offset0 = 0; - - *row_inc = pixinc(1 + - (y_predecim * screen_width - x_predecim * width) + - (fieldmode ? screen_width : 0), ps); - *pix_inc = pixinc(x_predecim, ps); - break; - - case OMAP_DSS_ROT_0 + 4: - case OMAP_DSS_ROT_180 + 4: - /* If the pixel format is YUV or UYVY divide the width - * of the image by 2 for 0 degree and 180 degree - */ - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - width = width >> 1; - case OMAP_DSS_ROT_90 + 4: - case OMAP_DSS_ROT_270 + 4: - *offset1 = 0; - if (field_offset) - *offset0 = field_offset * screen_width * ps; - else - *offset0 = 0; - *row_inc = pixinc(1 - - (y_predecim * screen_width + x_predecim * width) - - (fieldmode ? screen_width : 0), ps); - *pix_inc = pixinc(x_predecim, ps); - break; - - default: - BUG(); - return; - } -} - -static void calc_dma_rotation_offset(u8 rotation, bool mirror, - u16 screen_width, - u16 width, u16 height, - enum omap_color_mode color_mode, bool fieldmode, - unsigned int field_offset, - unsigned *offset0, unsigned *offset1, - s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) -{ - u8 ps; - u16 fbw, fbh; - - /* FIXME CLUT formats */ - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - case OMAP_DSS_COLOR_CLUT2: - case OMAP_DSS_COLOR_CLUT4: - case OMAP_DSS_COLOR_CLUT8: - BUG(); - return; - default: - ps = color_mode_to_bpp(color_mode) / 8; - break; - } - - DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, - width, height); - - /* width & height are overlay sizes, convert to fb sizes */ - - if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { - fbw = width; - fbh = height; - } else { - fbw = height; - fbh = width; - } - - /* - * field 0 = even field = bottom field - * field 1 = odd field = top field - */ - switch (rotation + mirror * 4) { - case OMAP_DSS_ROT_0: - *offset1 = 0; - if (field_offset) - *offset0 = *offset1 + field_offset * screen_width * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(1 + - (y_predecim * screen_width - fbw * x_predecim) + - (fieldmode ? screen_width : 0), ps); - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - *pix_inc = pixinc(x_predecim, 2 * ps); - else - *pix_inc = pixinc(x_predecim, ps); - break; - case OMAP_DSS_ROT_90: - *offset1 = screen_width * (fbh - 1) * ps; - if (field_offset) - *offset0 = *offset1 + field_offset * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + - y_predecim + (fieldmode ? 1 : 0), ps); - *pix_inc = pixinc(-x_predecim * screen_width, ps); - break; - case OMAP_DSS_ROT_180: - *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; - if (field_offset) - *offset0 = *offset1 - field_offset * screen_width * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(-1 - - (y_predecim * screen_width - fbw * x_predecim) - - (fieldmode ? screen_width : 0), ps); - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - *pix_inc = pixinc(-x_predecim, 2 * ps); - else - *pix_inc = pixinc(-x_predecim, ps); - break; - case OMAP_DSS_ROT_270: - *offset1 = (fbw - 1) * ps; - if (field_offset) - *offset0 = *offset1 - field_offset * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - - y_predecim - (fieldmode ? 1 : 0), ps); - *pix_inc = pixinc(x_predecim * screen_width, ps); - break; - - /* mirroring */ - case OMAP_DSS_ROT_0 + 4: - *offset1 = (fbw - 1) * ps; - if (field_offset) - *offset0 = *offset1 + field_offset * screen_width * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + - (fieldmode ? screen_width : 0), - ps); - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - *pix_inc = pixinc(-x_predecim, 2 * ps); - else - *pix_inc = pixinc(-x_predecim, ps); - break; - - case OMAP_DSS_ROT_90 + 4: - *offset1 = 0; - if (field_offset) - *offset0 = *offset1 + field_offset * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + - y_predecim + (fieldmode ? 1 : 0), - ps); - *pix_inc = pixinc(x_predecim * screen_width, ps); - break; - - case OMAP_DSS_ROT_180 + 4: - *offset1 = screen_width * (fbh - 1) * ps; - if (field_offset) - *offset0 = *offset1 - field_offset * screen_width * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(1 - y_predecim * screen_width * 2 - - (fieldmode ? screen_width : 0), - ps); - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - *pix_inc = pixinc(x_predecim, 2 * ps); - else - *pix_inc = pixinc(x_predecim, ps); - break; - - case OMAP_DSS_ROT_270 + 4: - *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; - if (field_offset) - *offset0 = *offset1 - field_offset * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - - y_predecim - (fieldmode ? 1 : 0), - ps); - *pix_inc = pixinc(-x_predecim * screen_width, ps); - break; - - default: - BUG(); - return; - } -} - -static void calc_tiler_rotation_offset(u16 screen_width, u16 width, - enum omap_color_mode color_mode, bool fieldmode, - unsigned int field_offset, unsigned *offset0, unsigned *offset1, - s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) -{ - u8 ps; - - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - case OMAP_DSS_COLOR_CLUT2: - case OMAP_DSS_COLOR_CLUT4: - case OMAP_DSS_COLOR_CLUT8: - BUG(); - return; - default: - ps = color_mode_to_bpp(color_mode) / 8; - break; + width *= 2; } - DSSDBG("scrw %d, width %d\n", screen_width, width); - /* * field 0 = even field = bottom field * field 1 = odd field = top field */ + *offset0 = field_offset * screen_width * ps; *offset1 = 0; - if (field_offset) - *offset0 = *offset1 + field_offset * screen_width * ps; - else - *offset0 = *offset1; + *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + (fieldmode ? screen_width : 0), ps); - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) + if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) *pix_inc = pixinc(x_predecim, 2 * ps); else *pix_inc = pixinc(x_predecim, ps); @@ -2263,7 +2109,7 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, static unsigned long calc_core_clk_five_taps(unsigned long pclk, const struct videomode *vm, u16 width, u16 height, u16 out_width, u16 out_height, - enum omap_color_mode color_mode) + u32 fourcc) { u32 core_clk = 0; u64 tmp; @@ -2293,7 +2139,7 @@ static unsigned long calc_core_clk_five_taps(unsigned long pclk, do_div(tmp, out_width); core_clk = max_t(u32, core_clk, tmp); - if (color_mode == OMAP_DSS_COLOR_RGB24U) + if (fourcc == DRM_FORMAT_XRGB8888) core_clk <<= 1; } @@ -2356,15 +2202,14 @@ static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, const struct videomode *vm, u16 width, u16 height, u16 out_width, u16 out_height, - enum omap_color_mode color_mode, bool *five_taps, + u32 fourcc, bool *five_taps, int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, u16 pos_x, unsigned long *core_clk, bool mem_to_mem) { int error; u16 in_width, in_height; int min_factor = min(*decim_x, *decim_y); - const int maxsinglelinewidth = - dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); + const int maxsinglelinewidth = dispc.feat->max_line_width; *five_taps = false; @@ -2402,14 +2247,13 @@ static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, const struct videomode *vm, u16 width, u16 height, u16 out_width, u16 out_height, - enum omap_color_mode color_mode, bool *five_taps, + u32 fourcc, bool *five_taps, int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, u16 pos_x, unsigned long *core_clk, bool mem_to_mem) { int error; u16 in_width, in_height; - const int maxsinglelinewidth = - dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); + const int maxsinglelinewidth = dispc.feat->max_line_width; do { in_height = height / *decim_y; @@ -2424,7 +2268,7 @@ again: if (*five_taps) *core_clk = calc_core_clk_five_taps(pclk, vm, in_width, in_height, out_width, - out_height, color_mode); + out_height, fourcc); else *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, out_width, out_height, @@ -2487,16 +2331,15 @@ again: static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, const struct videomode *vm, u16 width, u16 height, u16 out_width, u16 out_height, - enum omap_color_mode color_mode, bool *five_taps, + u32 fourcc, bool *five_taps, int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, u16 pos_x, unsigned long *core_clk, bool mem_to_mem) { u16 in_width, in_width_max; int decim_x_min = *decim_x; u16 in_height = height / *decim_y; - const int maxsinglelinewidth = - dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); - const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); + const int maxsinglelinewidth = dispc.feat->max_line_width; + const int maxdownscale = dispc.feat->max_downscale; if (mem_to_mem) { in_width_max = out_width * maxdownscale; @@ -2521,7 +2364,7 @@ static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, return -EINVAL; } - if (*decim_x > 4 && color_mode != OMAP_DSS_COLOR_NV12) { + if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) { /* * Let's disable all scaling that requires horizontal * decimation with higher factor than 4, until we have @@ -2552,11 +2395,11 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, enum omap_overlay_caps caps, const struct videomode *vm, u16 width, u16 height, u16 out_width, u16 out_height, - enum omap_color_mode color_mode, bool *five_taps, + u32 fourcc, bool *five_taps, int *x_predecim, int *y_predecim, u16 pos_x, enum omap_dss_rotation_type rotation_type, bool mem_to_mem) { - const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); + const int maxdownscale = dispc.feat->max_downscale; const int max_decim_limit = 16; unsigned long core_clk = 0; int decim_x, decim_y, ret; @@ -2577,20 +2420,10 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, } else { *x_predecim = max_decim_limit; *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && - dss_has_feature(FEAT_BURST_2D)) ? + dispc_has_feature(FEAT_BURST_2D)) ? 2 : max_decim_limit; } - if (color_mode == OMAP_DSS_COLOR_CLUT1 || - color_mode == OMAP_DSS_COLOR_CLUT2 || - color_mode == OMAP_DSS_COLOR_CLUT4 || - color_mode == OMAP_DSS_COLOR_CLUT8) { - *x_predecim = 1; - *y_predecim = 1; - *five_taps = false; - return 0; - } - decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); @@ -2601,7 +2434,7 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, return -EINVAL; ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height, - out_width, out_height, color_mode, five_taps, + out_width, out_height, fourcc, five_taps, x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, mem_to_mem); if (ret) @@ -2637,8 +2470,8 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, static int dispc_ovl_setup_common(enum omap_plane_id plane, enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, - u16 out_width, u16 out_height, enum omap_color_mode color_mode, - u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, + u16 out_width, u16 out_height, u32 fourcc, + u8 rotation, u8 zorder, u8 pre_mult_alpha, u8 global_alpha, enum omap_dss_rotation_type rotation_type, bool replication, const struct videomode *vm, bool mem_to_mem) @@ -2661,19 +2494,9 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) return -EINVAL; - switch (color_mode) { - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: - case OMAP_DSS_COLOR_NV12: - if (in_width & 1) { - DSSERR("input width %d is not even for YUV format\n", - in_width); - return -EINVAL; - } - break; - - default: - break; + if (format_is_yuv(fourcc) && (in_width & 1)) { + DSSERR("input width %d is not even for YUV format\n", in_width); + return -EINVAL; } out_width = out_width == 0 ? width : out_width; @@ -2693,11 +2516,11 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, out_height); } - if (!dss_feat_color_mode_supported(plane, color_mode)) + if (!dispc_ovl_color_mode_supported(plane, fourcc)) return -EINVAL; r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width, - in_height, out_width, out_height, color_mode, + in_height, out_width, out_height, fourcc, &five_taps, &x_predecim, &y_predecim, pos_x, rotation_type, mem_to_mem); if (r) @@ -2710,26 +2533,15 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, DSSDBG("predecimation %d x %x, new input size %d x %d\n", x_predecim, y_predecim, in_width, in_height); - switch (color_mode) { - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: - case OMAP_DSS_COLOR_NV12: - if (in_width & 1) { - DSSDBG("predecimated input width is not even for YUV format\n"); - DSSDBG("adjusting input width %d -> %d\n", - in_width, in_width & ~1); - - in_width &= ~1; - } - break; + if (format_is_yuv(fourcc) && (in_width & 1)) { + DSSDBG("predecimated input width is not even for YUV format\n"); + DSSDBG("adjusting input width %d -> %d\n", + in_width, in_width & ~1); - default: - break; + in_width &= ~1; } - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY || - color_mode == OMAP_DSS_COLOR_NV12) + if (format_is_yuv(fourcc)) cconv = 1; if (ilace && !fieldmode) { @@ -2763,28 +2575,16 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, frame_height = height; } - if (rotation_type == OMAP_DSS_ROT_TILER) - calc_tiler_rotation_offset(screen_width, frame_width, - color_mode, fieldmode, field_offset, - &offset0, &offset1, &row_inc, &pix_inc, - x_predecim, y_predecim); - else if (rotation_type == OMAP_DSS_ROT_DMA) - calc_dma_rotation_offset(rotation, mirror, screen_width, - frame_width, frame_height, - color_mode, fieldmode, field_offset, - &offset0, &offset1, &row_inc, &pix_inc, - x_predecim, y_predecim); - else - calc_vrfb_rotation_offset(rotation, mirror, - screen_width, frame_width, frame_height, - color_mode, fieldmode, field_offset, - &offset0, &offset1, &row_inc, &pix_inc, - x_predecim, y_predecim); + calc_offset(screen_width, frame_width, + fourcc, fieldmode, field_offset, + &offset0, &offset1, &row_inc, &pix_inc, + x_predecim, y_predecim, + rotation_type, rotation); DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", offset0, offset1, row_inc, pix_inc); - dispc_ovl_set_color_mode(plane, color_mode); + dispc_ovl_set_color_mode(plane, fourcc); dispc_ovl_configure_burst_type(plane, rotation_type); @@ -2794,7 +2594,7 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, dispc_ovl_set_ba0(plane, paddr + offset0); dispc_ovl_set_ba1(plane, paddr + offset1); - if (OMAP_DSS_COLOR_NV12 == color_mode) { + if (fourcc == DRM_FORMAT_NV12) { dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); } @@ -2815,13 +2615,12 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, if (caps & OMAP_DSS_OVL_CAP_SCALE) { dispc_ovl_set_scaling(plane, in_width, in_height, out_width, out_height, ilace, five_taps, fieldmode, - color_mode, rotation); + fourcc, rotation); dispc_ovl_set_output_size(plane, out_width, out_height); dispc_ovl_set_vid_color_conv(plane, cconv); } - dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror, - color_mode); + dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, fourcc); dispc_ovl_set_zorder(plane, caps, zorder); dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); @@ -2834,25 +2633,25 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, static int dispc_ovl_setup(enum omap_plane_id plane, const struct omap_overlay_info *oi, - const struct videomode *vm, bool mem_to_mem) + const struct videomode *vm, bool mem_to_mem, + enum omap_channel channel) { int r; - enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); - enum omap_channel channel; + enum omap_overlay_caps caps = dispc.feat->overlay_caps[plane]; const bool replication = true; - channel = dispc_ovl_get_channel_out(plane); - DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" - " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n", + " %dx%d, cmode %x, rot %d, chan %d repl %d\n", plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, - oi->color_mode, oi->rotation, oi->mirror, channel, replication); + oi->fourcc, oi->rotation, channel, replication); + + dispc_ovl_set_channel_out(plane, channel); r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, - oi->out_width, oi->out_height, oi->color_mode, oi->rotation, - oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, + oi->out_width, oi->out_height, oi->fourcc, oi->rotation, + oi->zorder, oi->pre_mult_alpha, oi->global_alpha, oi->rotation_type, replication, vm, mem_to_mem); return r; @@ -2874,25 +2673,24 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi, OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " - "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width, - in_height, wi->width, wi->height, wi->color_mode, wi->rotation, - wi->mirror); + "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, + in_height, wi->width, wi->height, wi->fourcc, wi->rotation); r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr, wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, - wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder, + wi->height, wi->fourcc, wi->rotation, zorder, wi->pre_mult_alpha, global_alpha, wi->rotation_type, replication, vm, mem_to_mem); - switch (wi->color_mode) { - case OMAP_DSS_COLOR_RGB16: - case OMAP_DSS_COLOR_RGB24P: - case OMAP_DSS_COLOR_ARGB16: - case OMAP_DSS_COLOR_RGBA16: - case OMAP_DSS_COLOR_RGB12U: - case OMAP_DSS_COLOR_ARGB16_1555: - case OMAP_DSS_COLOR_XRGB16_1555: - case OMAP_DSS_COLOR_RGBX16: + switch (wi->fourcc) { + case DRM_FORMAT_RGB565: + case DRM_FORMAT_RGB888: + case DRM_FORMAT_ARGB4444: + case DRM_FORMAT_RGBA4444: + case DRM_FORMAT_RGBX4444: + case DRM_FORMAT_ARGB1555: + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_XRGB4444: truncation = true; break; default: @@ -2935,19 +2733,14 @@ static int dispc_ovl_enable(enum omap_plane_id plane, bool enable) return 0; } -static bool dispc_ovl_enabled(enum omap_plane_id plane) -{ - return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); -} - static enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel) { - return dss_feat_get_supported_outputs(channel); + return dss_get_supported_outputs(channel); } static void dispc_lcd_enable_signal_polarity(bool act_high) { - if (!dss_has_feature(FEAT_LCDENABLEPOL)) + if (!dispc_has_feature(FEAT_LCDENABLEPOL)) return; REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); @@ -2955,7 +2748,7 @@ static void dispc_lcd_enable_signal_polarity(bool act_high) void dispc_lcd_enable_signal(bool enable) { - if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) + if (!dispc_has_feature(FEAT_LCDENABLESIGNAL)) return; REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); @@ -2963,17 +2756,12 @@ void dispc_lcd_enable_signal(bool enable) void dispc_pck_free_enable(bool enable) { - if (!dss_has_feature(FEAT_PCKFREEENABLE)) + if (!dispc_has_feature(FEAT_PCKFREEENABLE)) return; REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); } -static int dispc_get_num_mgrs(void) -{ - return dss_feat_get_num_mgrs(); -} - static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) { mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); @@ -3013,7 +2801,7 @@ static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable) { - if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) + if (!dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER)) return; if (ch == OMAP_DSS_CHANNEL_LCD) @@ -3030,7 +2818,7 @@ static void dispc_mgr_setup(enum omap_channel channel, dispc_mgr_enable_trans_key(channel, info->trans_enabled); dispc_mgr_enable_alpha_fixed_zorder(channel, info->partial_alpha_enabled); - if (dss_has_feature(FEAT_CPR)) { + if (dispc_has_feature(FEAT_CPR)) { dispc_mgr_enable_cpr(channel, info->cpr_enable); dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); } @@ -3308,7 +3096,7 @@ static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, dispc_write_reg(DISPC_DIVISORo(channel), FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); - if (!dss_has_feature(FEAT_CORE_CLK_DIV) && + if (!dispc_has_feature(FEAT_CORE_CLK_DIV) && channel == OMAP_DSS_CHANNEL_LCD) dispc.core_clk_rate = dispc_fclk_rate() / lck_div; } @@ -3463,7 +3251,7 @@ void dispc_dump_clocks(struct seq_file *s) seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); - if (dss_has_feature(FEAT_CORE_CLK_DIV)) { + if (dispc_has_feature(FEAT_CORE_CLK_DIV)) { seq_printf(s, "- DISPC-CORE-CLK -\n"); l = dispc_read_reg(DISPC_DIVISOR); lcd = FLD_GET(l, 23, 16); @@ -3474,9 +3262,9 @@ void dispc_dump_clocks(struct seq_file *s) dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); - if (dss_has_feature(FEAT_MGR_LCD2)) + if (dispc_has_feature(FEAT_MGR_LCD2)) dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); - if (dss_has_feature(FEAT_MGR_LCD3)) + if (dispc_has_feature(FEAT_MGR_LCD3)) dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); dispc_runtime_put(); @@ -3516,18 +3304,18 @@ static void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_CAPABLE); DUMPREG(DISPC_LINE_STATUS); DUMPREG(DISPC_LINE_NUMBER); - if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || - dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) + if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || + dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) DUMPREG(DISPC_GLOBAL_ALPHA); - if (dss_has_feature(FEAT_MGR_LCD2)) { + if (dispc_has_feature(FEAT_MGR_LCD2)) { DUMPREG(DISPC_CONTROL2); DUMPREG(DISPC_CONFIG2); } - if (dss_has_feature(FEAT_MGR_LCD3)) { + if (dispc_has_feature(FEAT_MGR_LCD3)) { DUMPREG(DISPC_CONTROL3); DUMPREG(DISPC_CONFIG3); } - if (dss_has_feature(FEAT_MFLAG)) + if (dispc_has_feature(FEAT_MFLAG)) DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); #undef DUMPREG @@ -3540,7 +3328,7 @@ static void dispc_dump_regs(struct seq_file *s) p_names = mgr_names; /* DISPC channel specific registers */ - for (i = 0; i < dss_feat_get_num_mgrs(); i++) { + for (i = 0; i < dispc_get_num_mgrs(); i++) { DUMPREG(i, DISPC_DEFAULT_COLOR); DUMPREG(i, DISPC_TRANS_COLOR); DUMPREG(i, DISPC_SIZE_MGR); @@ -3557,7 +3345,7 @@ static void dispc_dump_regs(struct seq_file *s) DUMPREG(i, DISPC_DATA_CYCLE2); DUMPREG(i, DISPC_DATA_CYCLE3); - if (dss_has_feature(FEAT_CPR)) { + if (dispc_has_feature(FEAT_CPR)) { DUMPREG(i, DISPC_CPR_COEF_R); DUMPREG(i, DISPC_CPR_COEF_G); DUMPREG(i, DISPC_CPR_COEF_B); @@ -3566,7 +3354,7 @@ static void dispc_dump_regs(struct seq_file *s) p_names = ovl_names; - for (i = 0; i < dss_feat_get_num_ovls(); i++) { + for (i = 0; i < dispc_get_num_ovls(); i++) { DUMPREG(i, DISPC_OVL_BA0); DUMPREG(i, DISPC_OVL_BA1); DUMPREG(i, DISPC_OVL_POSITION); @@ -3577,9 +3365,9 @@ static void dispc_dump_regs(struct seq_file *s) DUMPREG(i, DISPC_OVL_ROW_INC); DUMPREG(i, DISPC_OVL_PIXEL_INC); - if (dss_has_feature(FEAT_PRELOAD)) + if (dispc_has_feature(FEAT_PRELOAD)) DUMPREG(i, DISPC_OVL_PRELOAD); - if (dss_has_feature(FEAT_MFLAG)) + if (dispc_has_feature(FEAT_MFLAG)) DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); if (i == OMAP_DSS_GFX) { @@ -3592,14 +3380,14 @@ static void dispc_dump_regs(struct seq_file *s) DUMPREG(i, DISPC_OVL_PICTURE_SIZE); DUMPREG(i, DISPC_OVL_ACCU0); DUMPREG(i, DISPC_OVL_ACCU1); - if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { + if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { DUMPREG(i, DISPC_OVL_BA0_UV); DUMPREG(i, DISPC_OVL_BA1_UV); DUMPREG(i, DISPC_OVL_FIR2); DUMPREG(i, DISPC_OVL_ACCU2_0); DUMPREG(i, DISPC_OVL_ACCU2_1); } - if (dss_has_feature(FEAT_ATTR2)) + if (dispc_has_feature(FEAT_ATTR2)) DUMPREG(i, DISPC_OVL_ATTRIBUTES2); } @@ -3614,21 +3402,21 @@ static void dispc_dump_regs(struct seq_file *s) DUMPREG(i, DISPC_OVL_ROW_INC); DUMPREG(i, DISPC_OVL_PIXEL_INC); - if (dss_has_feature(FEAT_MFLAG)) + if (dispc_has_feature(FEAT_MFLAG)) DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); DUMPREG(i, DISPC_OVL_FIR); DUMPREG(i, DISPC_OVL_PICTURE_SIZE); DUMPREG(i, DISPC_OVL_ACCU0); DUMPREG(i, DISPC_OVL_ACCU1); - if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { + if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { DUMPREG(i, DISPC_OVL_BA0_UV); DUMPREG(i, DISPC_OVL_BA1_UV); DUMPREG(i, DISPC_OVL_FIR2); DUMPREG(i, DISPC_OVL_ACCU2_0); DUMPREG(i, DISPC_OVL_ACCU2_1); } - if (dss_has_feature(FEAT_ATTR2)) + if (dispc_has_feature(FEAT_ATTR2)) DUMPREG(i, DISPC_OVL_ATTRIBUTES2); } @@ -3644,7 +3432,7 @@ static void dispc_dump_regs(struct seq_file *s) /* Video pipeline coefficient registers */ /* start from OMAP_DSS_VIDEO1 */ - for (i = 1; i < dss_feat_get_num_ovls(); i++) { + for (i = 1; i < dispc_get_num_ovls(); i++) { for (j = 0; j < 8; j++) DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); @@ -3654,12 +3442,12 @@ static void dispc_dump_regs(struct seq_file *s) for (j = 0; j < 5; j++) DUMPREG(i, DISPC_OVL_CONV_COEF, j); - if (dss_has_feature(FEAT_FIR_COEF_V)) { + if (dispc_has_feature(FEAT_FIR_COEF_V)) { for (j = 0; j < 8; j++) DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); } - if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { + if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { for (j = 0; j < 8; j++) DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); @@ -3692,7 +3480,7 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, return 0; } -bool dispc_div_calc(unsigned long dispc, +bool dispc_div_calc(unsigned long dispc_freq, unsigned long pck_min, unsigned long pck_max, dispc_div_calc_func func, void *data) { @@ -3710,19 +3498,19 @@ bool dispc_div_calc(unsigned long dispc, min_fck_per_pck = 0; #endif - pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); - pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); + pckd_hw_min = dispc.feat->min_pcd; + pckd_hw_max = 255; - lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); + lck_max = dss_get_max_fck_rate(); pck_min = pck_min ? pck_min : 1; pck_max = pck_max ? pck_max : ULONG_MAX; - lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); - lckd_stop = min(dispc / pck_min, 255ul); + lckd_start = max(DIV_ROUND_UP(dispc_freq, lck_max), 1ul); + lckd_stop = min(dispc_freq / pck_min, 255ul); for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { - lck = dispc / lckd; + lck = dispc_freq / lckd; pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); pckd_stop = min(lck / pck_min, pckd_hw_max); @@ -3736,7 +3524,7 @@ bool dispc_div_calc(unsigned long dispc, * also. Thus we need to use the calculated lck. For * OMAP4+ the DISPC fclk is a separate clock. */ - if (dss_has_feature(FEAT_CORE_CLK_DIV)) + if (dispc_has_feature(FEAT_CORE_CLK_DIV)) fck = dispc_core_clk_rate(); else fck = lck; @@ -3787,11 +3575,6 @@ static void dispc_clear_irqstatus(u32 mask) dispc_write_reg(DISPC_IRQSTATUS, mask); } -static u32 dispc_read_irqenable(void) -{ - return dispc_read_reg(DISPC_IRQENABLE); -} - static void dispc_write_irqenable(u32 mask) { u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); @@ -3800,6 +3583,9 @@ static void dispc_write_irqenable(u32 mask) dispc_clear_irqstatus((mask ^ old_mask) & mask); dispc_write_reg(DISPC_IRQENABLE, mask); + + /* flush posted write */ + dispc_read_reg(DISPC_IRQENABLE); } void dispc_enable_sidle(void) @@ -3853,10 +3639,10 @@ static void dispc_restore_gamma_tables(void) dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT); - if (dss_has_feature(FEAT_MGR_LCD2)) + if (dispc_has_feature(FEAT_MGR_LCD2)) dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2); - if (dss_has_feature(FEAT_MGR_LCD3)) + if (dispc_has_feature(FEAT_MGR_LCD3)) dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3); } @@ -3924,11 +3710,11 @@ static int dispc_init_gamma_tables(void) u32 *gt; if (channel == OMAP_DSS_CHANNEL_LCD2 && - !dss_has_feature(FEAT_MGR_LCD2)) + !dispc_has_feature(FEAT_MGR_LCD2)) continue; if (channel == OMAP_DSS_CHANNEL_LCD3 && - !dss_has_feature(FEAT_MGR_LCD3)) + !dispc_has_feature(FEAT_MGR_LCD3)) continue; gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len, @@ -3948,7 +3734,7 @@ static void _omap_dispc_initial_config(void) u32 l; /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ - if (dss_has_feature(FEAT_CORE_CLK_DIV)) { + if (dispc_has_feature(FEAT_CORE_CLK_DIV)) { l = dispc_read_reg(DISPC_DIVISOR); /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ l = FLD_MOD(l, 1, 0, 0); @@ -3966,7 +3752,7 @@ static void _omap_dispc_initial_config(void) * func-clock auto-gating. For newer versions * (dispc.feat->has_gamma_table) this enables tv-out gamma tables. */ - if (dss_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table) + if (dispc_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table) REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); dispc_setup_color_conv_coef(); @@ -3982,10 +3768,272 @@ static void _omap_dispc_initial_config(void) if (dispc.feat->mstandby_workaround) REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); - if (dss_has_feature(FEAT_MFLAG)) + if (dispc_has_feature(FEAT_MFLAG)) dispc_init_mflag(); } +static const enum dispc_feature_id omap2_dispc_features_list[] = { + FEAT_LCDENABLEPOL, + FEAT_LCDENABLESIGNAL, + FEAT_PCKFREEENABLE, + FEAT_FUNCGATED, + FEAT_ROWREPEATENABLE, + FEAT_RESIZECONF, +}; + +static const enum dispc_feature_id omap3_dispc_features_list[] = { + FEAT_LCDENABLEPOL, + FEAT_LCDENABLESIGNAL, + FEAT_PCKFREEENABLE, + FEAT_FUNCGATED, + FEAT_LINEBUFFERSPLIT, + FEAT_ROWREPEATENABLE, + FEAT_RESIZECONF, + FEAT_CPR, + FEAT_PRELOAD, + FEAT_FIR_COEF_V, + FEAT_ALPHA_FIXED_ZORDER, + FEAT_FIFO_MERGE, + FEAT_OMAP3_DSI_FIFO_BUG, +}; + +static const enum dispc_feature_id am43xx_dispc_features_list[] = { + FEAT_LCDENABLEPOL, + FEAT_LCDENABLESIGNAL, + FEAT_PCKFREEENABLE, + FEAT_FUNCGATED, + FEAT_LINEBUFFERSPLIT, + FEAT_ROWREPEATENABLE, + FEAT_RESIZECONF, + FEAT_CPR, + FEAT_PRELOAD, + FEAT_FIR_COEF_V, + FEAT_ALPHA_FIXED_ZORDER, + FEAT_FIFO_MERGE, +}; + +static const enum dispc_feature_id omap4_dispc_features_list[] = { + FEAT_MGR_LCD2, + FEAT_CORE_CLK_DIV, + FEAT_HANDLE_UV_SEPARATE, + FEAT_ATTR2, + FEAT_CPR, + FEAT_PRELOAD, + FEAT_FIR_COEF_V, + FEAT_ALPHA_FREE_ZORDER, + FEAT_FIFO_MERGE, + FEAT_BURST_2D, +}; + +static const enum dispc_feature_id omap5_dispc_features_list[] = { + FEAT_MGR_LCD2, + FEAT_MGR_LCD3, + FEAT_CORE_CLK_DIV, + FEAT_HANDLE_UV_SEPARATE, + FEAT_ATTR2, + FEAT_CPR, + FEAT_PRELOAD, + FEAT_FIR_COEF_V, + FEAT_ALPHA_FREE_ZORDER, + FEAT_FIFO_MERGE, + FEAT_BURST_2D, + FEAT_MFLAG, +}; + +static const struct dss_reg_field omap2_dispc_reg_fields[] = { + [FEAT_REG_FIRHINC] = { 11, 0 }, + [FEAT_REG_FIRVINC] = { 27, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, + [FEAT_REG_FIFOSIZE] = { 8, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, +}; + +static const struct dss_reg_field omap3_dispc_reg_fields[] = { + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, + [FEAT_REG_FIFOSIZE] = { 10, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, +}; + +static const struct dss_reg_field omap4_dispc_reg_fields[] = { + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, + [FEAT_REG_FIFOSIZE] = { 15, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, + [FEAT_REG_VERTICALACCU] = { 26, 16 }, +}; + +static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, +}; + +static const enum omap_overlay_caps omap3430_dispc_overlay_caps[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, +}; + +static const enum omap_overlay_caps omap3630_dispc_overlay_caps[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, +}; + +static const enum omap_overlay_caps omap4_dispc_overlay_caps[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | + OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO3 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, +}; + +#define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 } + +static const u32 *omap2_dispc_supported_color_modes[] = { + + /* OMAP_DSS_GFX */ + COLOR_ARRAY( + DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888), + + /* OMAP_DSS_VIDEO1 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY), + + /* OMAP_DSS_VIDEO2 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY), +}; + +static const u32 *omap3_dispc_supported_color_modes[] = { + /* OMAP_DSS_GFX */ + COLOR_ARRAY( + DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), + + /* OMAP_DSS_VIDEO1 */ + COLOR_ARRAY( + DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888, + DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, + DRM_FORMAT_YUYV, DRM_FORMAT_UYVY), + + /* OMAP_DSS_VIDEO2 */ + COLOR_ARRAY( + DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), +}; + +static const u32 *omap4_dispc_supported_color_modes[] = { + /* OMAP_DSS_GFX */ + COLOR_ARRAY( + DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888, + DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555), + + /* OMAP_DSS_VIDEO1 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, + DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, + DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBX8888), + + /* OMAP_DSS_VIDEO2 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, + DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, + DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBX8888), + + /* OMAP_DSS_VIDEO3 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, + DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, + DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBX8888), + + /* OMAP_DSS_WB */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, + DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, + DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBX8888), +}; + static const struct dispc_features omap24xx_dispc_feats = { .sw_start = 5, .fp_start = 15, @@ -3998,9 +4046,26 @@ static const struct dispc_features omap24xx_dispc_feats = { .mgr_width_max = 2048, .mgr_height_max = 2048, .max_lcd_pclk = 66500000, + .max_downscale = 2, + /* + * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler + * cannot scale an image width larger than 768. + */ + .max_line_width = 768, + .min_pcd = 2, .calc_scaling = dispc_ovl_calc_scaling_24xx, .calc_core_clk = calc_core_clk_24xx, .num_fifos = 3, + .features = omap2_dispc_features_list, + .num_features = ARRAY_SIZE(omap2_dispc_features_list), + .reg_fields = omap2_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap2_dispc_reg_fields), + .overlay_caps = omap2_dispc_overlay_caps, + .supported_color_modes = omap2_dispc_supported_color_modes, + .num_mgrs = 2, + .num_ovls = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, .no_framedone_tv = true, .set_max_preload = false, .last_pixel_inc_missing = true, @@ -4019,9 +4084,22 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { .mgr_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, + .max_downscale = 4, + .max_line_width = 1024, + .min_pcd = 1, .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .features = omap3_dispc_features_list, + .num_features = ARRAY_SIZE(omap3_dispc_features_list), + .reg_fields = omap3_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), + .overlay_caps = omap3430_dispc_overlay_caps, + .supported_color_modes = omap3_dispc_supported_color_modes, + .num_mgrs = 2, + .num_ovls = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, .no_framedone_tv = true, .set_max_preload = false, .last_pixel_inc_missing = true, @@ -4040,9 +4118,90 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { .mgr_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, + .max_downscale = 4, + .max_line_width = 1024, + .min_pcd = 1, + .calc_scaling = dispc_ovl_calc_scaling_34xx, + .calc_core_clk = calc_core_clk_34xx, + .num_fifos = 3, + .features = omap3_dispc_features_list, + .num_features = ARRAY_SIZE(omap3_dispc_features_list), + .reg_fields = omap3_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), + .overlay_caps = omap3430_dispc_overlay_caps, + .supported_color_modes = omap3_dispc_supported_color_modes, + .num_mgrs = 2, + .num_ovls = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, + .no_framedone_tv = true, + .set_max_preload = false, + .last_pixel_inc_missing = true, +}; + +static const struct dispc_features omap36xx_dispc_feats = { + .sw_start = 7, + .fp_start = 19, + .bp_start = 31, + .sw_max = 256, + .vp_max = 4095, + .hp_max = 4096, + .mgr_width_start = 10, + .mgr_height_start = 26, + .mgr_width_max = 2048, + .mgr_height_max = 2048, + .max_lcd_pclk = 173000000, + .max_tv_pclk = 59000000, + .max_downscale = 4, + .max_line_width = 1024, + .min_pcd = 1, + .calc_scaling = dispc_ovl_calc_scaling_34xx, + .calc_core_clk = calc_core_clk_34xx, + .num_fifos = 3, + .features = omap3_dispc_features_list, + .num_features = ARRAY_SIZE(omap3_dispc_features_list), + .reg_fields = omap3_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), + .overlay_caps = omap3630_dispc_overlay_caps, + .supported_color_modes = omap3_dispc_supported_color_modes, + .num_mgrs = 2, + .num_ovls = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, + .no_framedone_tv = true, + .set_max_preload = false, + .last_pixel_inc_missing = true, +}; + +static const struct dispc_features am43xx_dispc_feats = { + .sw_start = 7, + .fp_start = 19, + .bp_start = 31, + .sw_max = 256, + .vp_max = 4095, + .hp_max = 4096, + .mgr_width_start = 10, + .mgr_height_start = 26, + .mgr_width_max = 2048, + .mgr_height_max = 2048, + .max_lcd_pclk = 173000000, + .max_tv_pclk = 59000000, + .max_downscale = 4, + .max_line_width = 1024, + .min_pcd = 1, .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .features = am43xx_dispc_features_list, + .num_features = ARRAY_SIZE(am43xx_dispc_features_list), + .reg_fields = omap3_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), + .overlay_caps = omap3430_dispc_overlay_caps, + .supported_color_modes = omap3_dispc_supported_color_modes, + .num_mgrs = 1, + .num_ovls = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, .no_framedone_tv = true, .set_max_preload = false, .last_pixel_inc_missing = true, @@ -4061,9 +4220,22 @@ static const struct dispc_features omap44xx_dispc_feats = { .mgr_height_max = 2048, .max_lcd_pclk = 170000000, .max_tv_pclk = 185625000, + .max_downscale = 4, + .max_line_width = 2048, + .min_pcd = 1, .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .features = omap4_dispc_features_list, + .num_features = ARRAY_SIZE(omap4_dispc_features_list), + .reg_fields = omap4_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), + .overlay_caps = omap4_dispc_overlay_caps, + .supported_color_modes = omap4_dispc_supported_color_modes, + .num_mgrs = 3, + .num_ovls = 4, + .buffer_size_unit = 16, + .burst_size_unit = 16, .gfx_fifo_workaround = true, .set_max_preload = true, .supports_sync_align = true, @@ -4087,9 +4259,22 @@ static const struct dispc_features omap54xx_dispc_feats = { .mgr_height_max = 4096, .max_lcd_pclk = 170000000, .max_tv_pclk = 186000000, + .max_downscale = 4, + .max_line_width = 2048, + .min_pcd = 1, .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .features = omap5_dispc_features_list, + .num_features = ARRAY_SIZE(omap5_dispc_features_list), + .reg_fields = omap4_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), + .overlay_caps = omap4_dispc_overlay_caps, + .supported_color_modes = omap4_dispc_supported_color_modes, + .num_mgrs = 4, + .num_ovls = 4, + .buffer_size_unit = 16, + .burst_size_unit = 16, .gfx_fifo_workaround = true, .mstandby_workaround = true, .set_max_preload = true, @@ -4101,54 +4286,6 @@ static const struct dispc_features omap54xx_dispc_feats = { .has_gamma_i734_bug = true, }; -static int dispc_init_features(struct platform_device *pdev) -{ - const struct dispc_features *src; - struct dispc_features *dst; - - dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); - if (!dst) { - dev_err(&pdev->dev, "Failed to allocate DISPC Features\n"); - return -ENOMEM; - } - - switch (omapdss_get_version()) { - case OMAPDSS_VER_OMAP24xx: - src = &omap24xx_dispc_feats; - break; - - case OMAPDSS_VER_OMAP34xx_ES1: - src = &omap34xx_rev1_0_dispc_feats; - break; - - case OMAPDSS_VER_OMAP34xx_ES3: - case OMAPDSS_VER_OMAP3630: - case OMAPDSS_VER_AM35xx: - case OMAPDSS_VER_AM43xx: - src = &omap34xx_rev3_0_dispc_feats; - break; - - case OMAPDSS_VER_OMAP4430_ES1: - case OMAPDSS_VER_OMAP4430_ES2: - case OMAPDSS_VER_OMAP4: - src = &omap44xx_dispc_feats; - break; - - case OMAPDSS_VER_OMAP5: - case OMAPDSS_VER_DRA7xx: - src = &omap54xx_dispc_feats; - break; - - default: - return -ENODEV; - } - - memcpy(dst, src, sizeof(*dst)); - dispc.feat = dst; - - return 0; -} - static irqreturn_t dispc_irq_handler(int irq, void *arg) { if (!dispc.is_enabled) @@ -4225,10 +4362,9 @@ static const struct dispc_errata_i734_data { .ovli = { .screen_width = 1, .width = 1, .height = 1, - .color_mode = OMAP_DSS_COLOR_RGB24U, - .rotation = OMAP_DSS_ROT_0, - .rotation_type = OMAP_DSS_ROT_DMA, - .mirror = 0, + .fourcc = DRM_FORMAT_XRGB8888, + .rotation = DRM_MODE_ROTATE_0, + .rotation_type = OMAP_DSS_ROT_NONE, .pos_x = 0, .pos_y = 0, .out_width = 0, .out_height = 0, .global_alpha = 0xff, @@ -4266,7 +4402,7 @@ static int dispc_errata_i734_wa_init(void) return 0; i734_buf.size = i734.ovli.width * i734.ovli.height * - color_mode_to_bpp(i734.ovli.color_mode) / 8; + color_mode_to_bpp(i734.ovli.fourcc) / 8; i734_buf.vaddr = dma_alloc_writecombine(&dispc.pdev->dev, i734_buf.size, &i734_buf.paddr, GFP_KERNEL); @@ -4309,8 +4445,8 @@ static void dispc_errata_i734_wa(void) REG_FLD_MOD(DISPC_CONFIG, 0x1f, 8, 4); /* Setup and enable GFX plane */ - dispc_ovl_set_channel_out(OMAP_DSS_GFX, OMAP_DSS_CHANNEL_LCD); - dispc_ovl_setup(OMAP_DSS_GFX, &ovli, &i734.vm, false); + dispc_ovl_setup(OMAP_DSS_GFX, &ovli, &i734.vm, false, + OMAP_DSS_CHANNEL_LCD); dispc_ovl_enable(OMAP_DSS_GFX, true); /* Set up and enable display manager for LCD1 */ @@ -4350,7 +4486,6 @@ static void dispc_errata_i734_wa(void) static const struct dispc_ops dispc_ops = { .read_irqstatus = dispc_read_irqstatus, .clear_irqstatus = dispc_clear_irqstatus, - .read_irqenable = dispc_read_irqenable, .write_irqenable = dispc_write_irqenable, .request_irq = dispc_request_irq, @@ -4377,16 +4512,33 @@ static const struct dispc_ops dispc_ops = { .mgr_set_gamma = dispc_mgr_set_gamma, .ovl_enable = dispc_ovl_enable, - .ovl_enabled = dispc_ovl_enabled, - .ovl_set_channel_out = dispc_ovl_set_channel_out, .ovl_setup = dispc_ovl_setup, .ovl_get_color_modes = dispc_ovl_get_color_modes, }; /* DISPC HW IP initialisation */ +static const struct of_device_id dispc_of_match[] = { + { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats }, + { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats }, + { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats }, + { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats }, + { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats }, + {}, +}; + +static const struct soc_device_attribute dispc_soc_devices[] = { + { .machine = "OMAP3[45]*", + .revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats }, + { .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats }, + { .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats }, + { .machine = "AM43*", .data = &am43xx_dispc_feats }, + { /* sentinel */ } +}; + static int dispc_bind(struct device *dev, struct device *master, void *data) { struct platform_device *pdev = to_platform_device(dev); + const struct soc_device_attribute *soc; u32 rev; int r = 0; struct resource *dispc_mem; @@ -4396,26 +4548,24 @@ static int dispc_bind(struct device *dev, struct device *master, void *data) spin_lock_init(&dispc.control_lock); - r = dispc_init_features(dispc.pdev); - if (r) - return r; + /* + * The OMAP3-based models can't be told apart using the compatible + * string, use SoC device matching. + */ + soc = soc_device_match(dispc_soc_devices); + if (soc) + dispc.feat = soc->data; + else + dispc.feat = of_match_device(dispc_of_match, &pdev->dev)->data; r = dispc_errata_i734_wa_init(); if (r) return r; dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); - if (!dispc_mem) { - DSSERR("can't get IORESOURCE_MEM DISPC\n"); - return -EINVAL; - } - - dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, - resource_size(dispc_mem)); - if (!dispc.base) { - DSSERR("can't ioremap DISPC\n"); - return -ENOMEM; - } + dispc.base = devm_ioremap_resource(&pdev->dev, dispc_mem); + if (IS_ERR(dispc.base)) + return PTR_ERR(dispc.base); dispc.irq = platform_get_irq(dispc.pdev, 0); if (dispc.irq < 0) { @@ -4535,15 +4685,6 @@ static const struct dev_pm_ops dispc_pm_ops = { .runtime_resume = dispc_runtime_resume, }; -static const struct of_device_id dispc_of_match[] = { - { .compatible = "ti,omap2-dispc", }, - { .compatible = "ti,omap3-dispc", }, - { .compatible = "ti,omap4-dispc", }, - { .compatible = "ti,omap5-dispc", }, - { .compatible = "ti,dra7-dispc", }, - {}, -}; - static struct platform_driver omap_dispchw_driver = { .probe = dispc_probe, .remove = dispc_remove, diff --git a/drivers/gpu/drm/omapdrm/dss/display.c b/drivers/gpu/drm/omapdrm/dss/display.c index 26cb59be045e..42279933790e 100644 --- a/drivers/gpu/drm/omapdrm/dss/display.c +++ b/drivers/gpu/drm/omapdrm/dss/display.c @@ -30,45 +30,6 @@ #include "omapdss.h" -void omapdss_default_get_resolution(struct omap_dss_device *dssdev, - u16 *xres, u16 *yres) -{ - *xres = dssdev->panel.vm.hactive; - *yres = dssdev->panel.vm.vactive; -} -EXPORT_SYMBOL(omapdss_default_get_resolution); - -int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev) -{ - switch (dssdev->type) { - case OMAP_DISPLAY_TYPE_DPI: - if (dssdev->phy.dpi.data_lines == 24) - return 24; - else - return 16; - - case OMAP_DISPLAY_TYPE_DBI: - if (dssdev->ctrl.pixel_size == 24) - return 24; - else - return 16; - case OMAP_DISPLAY_TYPE_DSI: - if (dssdev->panel.dsi_pix_fmt == OMAP_DSS_DSI_FMT_RGB565) - return 16; - else - return 24; - case OMAP_DISPLAY_TYPE_VENC: - case OMAP_DISPLAY_TYPE_SDI: - case OMAP_DISPLAY_TYPE_HDMI: - case OMAP_DISPLAY_TYPE_DVI: - return 24; - default: - BUG(); - return 0; - } -} -EXPORT_SYMBOL(omapdss_default_get_recommended_bpp); - void omapdss_default_get_timings(struct omap_dss_device *dssdev, struct videomode *vm) { @@ -87,34 +48,21 @@ int omapdss_register_display(struct omap_dss_device *dssdev) int id; /* - * Note: this presumes all the displays are either using DT or non-DT, - * which normally should be the case. This also presumes that all - * displays either have an DT alias, or none has. + * Note: this presumes that all displays either have an DT alias, or + * none has. */ - - if (dssdev->dev->of_node) { - id = of_alias_get_id(dssdev->dev->of_node, "display"); - - if (id < 0) - id = disp_num_counter++; - } else { + id = of_alias_get_id(dssdev->dev->of_node, "display"); + if (id < 0) id = disp_num_counter++; - } snprintf(dssdev->alias, sizeof(dssdev->alias), "display%d", id); /* Use 'label' property for name, if it exists */ - if (dssdev->dev->of_node) - of_property_read_string(dssdev->dev->of_node, "label", - &dssdev->name); + of_property_read_string(dssdev->dev->of_node, "label", &dssdev->name); if (dssdev->name == NULL) dssdev->name = dssdev->alias; - if (drv && drv->get_resolution == NULL) - drv->get_resolution = omapdss_default_get_resolution; - if (drv && drv->get_recommended_bpp == NULL) - drv->get_recommended_bpp = omapdss_default_get_recommended_bpp; if (drv && drv->get_timings == NULL) drv->get_timings = omapdss_default_get_timings; diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c index 8a730a7afe76..daf286fc8a40 100644 --- a/drivers/gpu/drm/omapdrm/dss/dpi.c +++ b/drivers/gpu/drm/omapdrm/dss/dpi.c @@ -32,14 +32,14 @@ #include <linux/string.h> #include <linux/of.h> #include <linux/clk.h> -#include <linux/component.h> +#include <linux/sys_soc.h> #include "omapdss.h" #include "dss.h" -#include "dss_features.h" struct dpi_data { struct platform_device *pdev; + enum dss_model dss_model; struct regulator *vdds_dsi_reg; enum dss_clk_source clk_src; @@ -61,12 +61,6 @@ static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev) return container_of(dssdev, struct dpi_data, output); } -/* only used in non-DT mode */ -static struct dpi_data *dpi_get_data_from_pdev(struct platform_device *pdev) -{ - return dev_get_drvdata(&pdev->dev); -} - static enum dss_clk_source dpi_get_clk_src_dra7xx(enum omap_channel channel) { /* @@ -106,25 +100,21 @@ static enum dss_clk_source dpi_get_clk_src_dra7xx(enum omap_channel channel) return DSS_CLK_SRC_FCK; } -static enum dss_clk_source dpi_get_clk_src(enum omap_channel channel) +static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi) { + enum omap_channel channel = dpi->output.dispc_channel; + /* * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL * would also be used for DISPC fclk. Meaning, when the DPI output is * disabled, DISPC clock will be disabled, and TV out will stop. */ - switch (omapdss_get_version()) { - case OMAPDSS_VER_OMAP24xx: - case OMAPDSS_VER_OMAP34xx_ES1: - case OMAPDSS_VER_OMAP34xx_ES3: - case OMAPDSS_VER_OMAP3630: - case OMAPDSS_VER_AM35xx: - case OMAPDSS_VER_AM43xx: + switch (dpi->dss_model) { + case DSS_MODEL_OMAP2: + case DSS_MODEL_OMAP3: return DSS_CLK_SRC_FCK; - case OMAPDSS_VER_OMAP4430_ES1: - case OMAPDSS_VER_OMAP4430_ES2: - case OMAPDSS_VER_OMAP4: + case DSS_MODEL_OMAP4: switch (channel) { case OMAP_DSS_CHANNEL_LCD: return DSS_CLK_SRC_PLL1_1; @@ -134,7 +124,7 @@ static enum dss_clk_source dpi_get_clk_src(enum omap_channel channel) return DSS_CLK_SRC_FCK; } - case OMAPDSS_VER_OMAP5: + case DSS_MODEL_OMAP5: switch (channel) { case OMAP_DSS_CHANNEL_LCD: return DSS_CLK_SRC_PLL1_1; @@ -145,7 +135,7 @@ static enum dss_clk_source dpi_get_clk_src(enum omap_channel channel) return DSS_CLK_SRC_FCK; } - case OMAPDSS_VER_DRA7xx: + case DSS_MODEL_DRA7: return dpi_get_clk_src_dra7xx(channel); default: @@ -220,7 +210,7 @@ static bool dpi_calc_pll_cb(int n, int m, unsigned long fint, ctx->pll_cinfo.clkdco = clkdco; return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, - ctx->pck_min, dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), + ctx->pck_min, dss_get_max_fck_rate(), dpi_calc_hsdiv_cb, ctx); } @@ -410,19 +400,13 @@ static int dpi_display_enable(struct omap_dss_device *dssdev) mutex_lock(&dpi->lock); - if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi->vdds_dsi_reg) { - DSSERR("no VDSS_DSI regulator\n"); - r = -ENODEV; - goto err_no_reg; - } - if (!out->dispc_channel_connected) { DSSERR("failed to enable display: no output/manager\n"); r = -ENODEV; goto err_no_out_mgr; } - if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) { + if (dpi->vdds_dsi_reg) { r = regulator_enable(dpi->vdds_dsi_reg); if (r) goto err_reg_enable; @@ -466,11 +450,10 @@ err_pll_init: err_src_sel: dispc_runtime_put(); err_get_dispc: - if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) + if (dpi->vdds_dsi_reg) regulator_disable(dpi->vdds_dsi_reg); err_reg_enable: err_no_out_mgr: -err_no_reg: mutex_unlock(&dpi->lock); return r; } @@ -491,7 +474,7 @@ static void dpi_display_disable(struct omap_dss_device *dssdev) dispc_runtime_put(); - if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) + if (dpi->vdds_dsi_reg) regulator_disable(dpi->vdds_dsi_reg); mutex_unlock(&dpi->lock); @@ -567,17 +550,6 @@ static int dpi_check_timings(struct omap_dss_device *dssdev, return 0; } -static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines) -{ - struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); - - mutex_lock(&dpi->lock); - - dpi->data_lines = data_lines; - - mutex_unlock(&dpi->lock); -} - static int dpi_verify_pll(struct dss_pll *pll) { int r; @@ -593,11 +565,21 @@ static int dpi_verify_pll(struct dss_pll *pll) return 0; } +static const struct soc_device_attribute dpi_soc_devices[] = { + { .family = "OMAP3[456]*" }, + { .family = "[AD]M37*" }, + { /* sentinel */ } +}; + static int dpi_init_regulator(struct dpi_data *dpi) { struct regulator *vdds_dsi; - if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) + /* + * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and + * DM37xx only. + */ + if (!soc_device_match(dpi_soc_devices)) return 0; if (dpi->vdds_dsi_reg) @@ -622,7 +604,7 @@ static void dpi_init_pll(struct dpi_data *dpi) if (dpi->pll) return; - dpi->clk_src = dpi_get_clk_src(dpi->output.dispc_channel); + dpi->clk_src = dpi_get_clk_src(dpi); pll = dss_pll_find_by_src(dpi->clk_src); if (!pll) @@ -642,18 +624,14 @@ static void dpi_init_pll(struct dpi_data *dpi) * the channel in some more dynamic manner, or get the channel as a user * parameter. */ -static enum omap_channel dpi_get_channel(int port_num) +static enum omap_channel dpi_get_channel(struct dpi_data *dpi, int port_num) { - switch (omapdss_get_version()) { - case OMAPDSS_VER_OMAP24xx: - case OMAPDSS_VER_OMAP34xx_ES1: - case OMAPDSS_VER_OMAP34xx_ES3: - case OMAPDSS_VER_OMAP3630: - case OMAPDSS_VER_AM35xx: - case OMAPDSS_VER_AM43xx: + switch (dpi->dss_model) { + case DSS_MODEL_OMAP2: + case DSS_MODEL_OMAP3: return OMAP_DSS_CHANNEL_LCD; - case OMAPDSS_VER_DRA7xx: + case DSS_MODEL_DRA7: switch (port_num) { case 2: return OMAP_DSS_CHANNEL_LCD3; @@ -664,12 +642,10 @@ static enum omap_channel dpi_get_channel(int port_num) return OMAP_DSS_CHANNEL_LCD; } - case OMAPDSS_VER_OMAP4430_ES1: - case OMAPDSS_VER_OMAP4430_ES2: - case OMAPDSS_VER_OMAP4: + case DSS_MODEL_OMAP4: return OMAP_DSS_CHANNEL_LCD2; - case OMAPDSS_VER_OMAP5: + case DSS_MODEL_OMAP5: return OMAP_DSS_CHANNEL_LCD3; default: @@ -732,38 +708,10 @@ static const struct omapdss_dpi_ops dpi_ops = { .check_timings = dpi_check_timings, .set_timings = dpi_set_timings, .get_timings = dpi_get_timings, - - .set_data_lines = dpi_set_data_lines, }; -static void dpi_init_output(struct platform_device *pdev) -{ - struct dpi_data *dpi = dpi_get_data_from_pdev(pdev); - struct omap_dss_device *out = &dpi->output; - - out->dev = &pdev->dev; - out->id = OMAP_DSS_OUTPUT_DPI; - out->output_type = OMAP_DISPLAY_TYPE_DPI; - out->name = "dpi.0"; - out->dispc_channel = dpi_get_channel(0); - out->ops.dpi = &dpi_ops; - out->owner = THIS_MODULE; - - omapdss_register_output(out); -} - -static void dpi_uninit_output(struct platform_device *pdev) +static void dpi_init_output_port(struct dpi_data *dpi, struct device_node *port) { - struct dpi_data *dpi = dpi_get_data_from_pdev(pdev); - struct omap_dss_device *out = &dpi->output; - - omapdss_unregister_output(out); -} - -static void dpi_init_output_port(struct platform_device *pdev, - struct device_node *port) -{ - struct dpi_data *dpi = port->data; struct omap_dss_device *out = &dpi->output; int r; u32 port_num; @@ -785,10 +733,10 @@ static void dpi_init_output_port(struct platform_device *pdev, break; } - out->dev = &pdev->dev; + out->dev = &dpi->pdev->dev; out->id = OMAP_DSS_OUTPUT_DPI; out->output_type = OMAP_DISPLAY_TYPE_DPI; - out->dispc_channel = dpi_get_channel(port_num); + out->dispc_channel = dpi_get_channel(dpi, port_num); out->port_num = port_num; out->ops.dpi = &dpi_ops; out->owner = THIS_MODULE; @@ -804,69 +752,8 @@ static void dpi_uninit_output_port(struct device_node *port) omapdss_unregister_output(out); } -static int dpi_bind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - struct dpi_data *dpi; - - dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL); - if (!dpi) - return -ENOMEM; - - dpi->pdev = pdev; - - dev_set_drvdata(&pdev->dev, dpi); - - mutex_init(&dpi->lock); - - dpi_init_output(pdev); - - return 0; -} - -static void dpi_unbind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - - dpi_uninit_output(pdev); -} - -static const struct component_ops dpi_component_ops = { - .bind = dpi_bind, - .unbind = dpi_unbind, -}; - -static int dpi_probe(struct platform_device *pdev) -{ - return component_add(&pdev->dev, &dpi_component_ops); -} - -static int dpi_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &dpi_component_ops); - return 0; -} - -static struct platform_driver omap_dpi_driver = { - .probe = dpi_probe, - .remove = dpi_remove, - .driver = { - .name = "omapdss_dpi", - .suppress_bind_attrs = true, - }, -}; - -int __init dpi_init_platform_driver(void) -{ - return platform_driver_register(&omap_dpi_driver); -} - -void dpi_uninit_platform_driver(void) -{ - platform_driver_unregister(&omap_dpi_driver); -} - -int dpi_init_port(struct platform_device *pdev, struct device_node *port) +int dpi_init_port(struct platform_device *pdev, struct device_node *port, + enum dss_model dss_model) { struct dpi_data *dpi; struct device_node *ep; @@ -892,11 +779,12 @@ int dpi_init_port(struct platform_device *pdev, struct device_node *port) of_node_put(ep); dpi->pdev = pdev; + dpi->dss_model = dss_model; port->data = dpi; mutex_init(&dpi->lock); - dpi_init_output_port(pdev, port); + dpi_init_output_port(dpi, port); dpi->port_initialized = true; diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 910754bf8cf9..b56a05730314 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -20,6 +20,8 @@ #define DSS_SUBSYS_NAME "DSI" #include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> #include <linux/io.h> #include <linux/clk.h> #include <linux/device.h> @@ -42,12 +44,12 @@ #include <linux/of_graph.h> #include <linux/of_platform.h> #include <linux/component.h> +#include <linux/sys_soc.h> #include <video/mipi_display.h> #include "omapdss.h" #include "dss.h" -#include "dss_features.h" #define DSI_CATCH_MISSING_TE @@ -228,6 +230,12 @@ static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); #define DSI_MAX_NR_ISRS 2 #define DSI_MAX_NR_LANES 5 +enum dsi_model { + DSI_MODEL_OMAP3, + DSI_MODEL_OMAP4, + DSI_MODEL_OMAP5, +}; + enum dsi_lane_function { DSI_LANE_UNUSED = 0, DSI_LANE_CLK, @@ -299,12 +307,36 @@ struct dsi_lp_clock_info { u16 lp_clk_div; }; +struct dsi_module_id_data { + u32 address; + int id; +}; + +enum dsi_quirks { + DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */ + DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1), + DSI_QUIRK_VC_OCP_WIDTH = (1 << 2), + DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3), + DSI_QUIRK_GNQ = (1 << 4), + DSI_QUIRK_PHY_DCC = (1 << 5), +}; + +struct dsi_of_data { + enum dsi_model model; + const struct dss_pll_hw *pll_hw; + const struct dsi_module_id_data *modules; + unsigned int max_fck_freq; + unsigned int max_pll_lpdiv; + enum dsi_quirks quirks; +}; + struct dsi_data { struct platform_device *pdev; void __iomem *proto_base; void __iomem *phy_base; void __iomem *pll_base; + const struct dsi_of_data *data; int module_id; int irq; @@ -312,6 +344,7 @@ struct dsi_data { bool is_enabled; struct clk *dss_clk; + struct regmap *syscon; struct dispc_clock_info user_dispc_cinfo; struct dss_pll_clock_info user_dsi_cinfo; @@ -397,13 +430,6 @@ struct dsi_packet_sent_handler_data { struct completion *completion; }; -struct dsi_module_id_data { - u32 address; - int id; -}; - -static const struct of_device_id dsi_of_match[]; - #ifdef DSI_PERF_MEASURE static bool dsi_perf; module_param(dsi_perf, bool, 0644); @@ -1186,6 +1212,7 @@ static int dsi_regulator_init(struct platform_device *dsidev) static void _dsi_print_reset_status(struct platform_device *dsidev) { + struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); u32 l; int b0, b1, b2; @@ -1194,7 +1221,7 @@ static void _dsi_print_reset_status(struct platform_device *dsidev) * I/O. */ l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); - if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { + if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { b0 = 28; b1 = 27; b2 = 26; @@ -1297,7 +1324,7 @@ static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) unsigned long dsi_fclk; unsigned lp_clk_div; unsigned long lp_clk; - unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); + unsigned lpdiv_max = dsi->data->max_pll_lpdiv; lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; @@ -1349,11 +1376,12 @@ enum dsi_pll_power_state { static int dsi_pll_power(struct platform_device *dsidev, enum dsi_pll_power_state state) { + struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); int t = 0; /* DSI-PLL power command 0x3 is not working */ - if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && - state == DSI_PLL_POWER_ON_DIV) + if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) && + state == DSI_PLL_POWER_ON_DIV) state = DSI_PLL_POWER_ON_ALL; /* PLL_PWR_CMD */ @@ -1373,11 +1401,12 @@ static int dsi_pll_power(struct platform_device *dsidev, } -static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo) +static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi, + struct dss_pll_clock_info *cinfo) { unsigned long max_dsi_fck; - max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK); + max_dsi_fck = dsi->data->max_fck_freq; cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; @@ -1773,13 +1802,14 @@ static int dsi_cio_power(struct platform_device *dsidev, static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) { + struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); int val; /* line buffer on OMAP3 is 1024 x 24bits */ /* XXX: for some reason using full buffer size causes * considerable TX slowdown with update sizes that fill the * whole buffer */ - if (!dss_has_feature(FEAT_DSI_GNQ)) + if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) return 1023 * 3; val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ @@ -1872,6 +1902,7 @@ static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) static void dsi_cio_timings(struct platform_device *dsidev) { + struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); u32 r; u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; u32 tlpx_half, tclk_trail, tclk_zero; @@ -1934,7 +1965,7 @@ static void dsi_cio_timings(struct platform_device *dsidev) r = FLD_MOD(r, tclk_trail, 15, 8); r = FLD_MOD(r, tclk_zero, 7, 0); - if (dss_has_feature(FEAT_DSI_PHY_DCC)) { + if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) { r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ @@ -2006,7 +2037,7 @@ static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; const u8 *offsets; - if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) + if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) offsets = offsets_old; else offsets = offsets_new; @@ -2060,6 +2091,83 @@ static unsigned dsi_get_lane_mask(struct platform_device *dsidev) return mask; } +/* OMAP4 CONTROL_DSIPHY */ +#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 + +#define OMAP4_DSI2_LANEENABLE_SHIFT 29 +#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) +#define OMAP4_DSI1_LANEENABLE_SHIFT 24 +#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_DSI1_PIPD_SHIFT 19 +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) +#define OMAP4_DSI2_PIPD_SHIFT 14 +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) + +static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes) +{ + u32 enable_mask, enable_shift; + u32 pipd_mask, pipd_shift; + + if (dsi->module_id == 0) { + enable_mask = OMAP4_DSI1_LANEENABLE_MASK; + enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; + pipd_mask = OMAP4_DSI1_PIPD_MASK; + pipd_shift = OMAP4_DSI1_PIPD_SHIFT; + } else if (dsi->module_id == 1) { + enable_mask = OMAP4_DSI2_LANEENABLE_MASK; + enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; + pipd_mask = OMAP4_DSI2_PIPD_MASK; + pipd_shift = OMAP4_DSI2_PIPD_SHIFT; + } else { + return -ENODEV; + } + + return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET, + enable_mask | pipd_mask, + (lanes << enable_shift) | (lanes << pipd_shift)); +} + +/* OMAP5 CONTROL_DSIPHY */ + +#define OMAP5_DSIPHY_SYSCON_OFFSET 0x74 + +#define OMAP5_DSI1_LANEENABLE_SHIFT 24 +#define OMAP5_DSI2_LANEENABLE_SHIFT 19 +#define OMAP5_DSI_LANEENABLE_MASK 0x1f + +static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes) +{ + u32 enable_shift; + + if (dsi->module_id == 0) + enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT; + else if (dsi->module_id == 1) + enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT; + else + return -ENODEV; + + return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET, + OMAP5_DSI_LANEENABLE_MASK << enable_shift, + lanes << enable_shift); +} + +static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) +{ + if (dsi->data->model == DSI_MODEL_OMAP4) + return dsi_omap4_mux_pads(dsi, lane_mask); + if (dsi->data->model == DSI_MODEL_OMAP5) + return dsi_omap5_mux_pads(dsi, lane_mask); + return 0; +} + +static void dsi_disable_pads(struct dsi_data *dsi) +{ + if (dsi->data->model == DSI_MODEL_OMAP4) + dsi_omap4_mux_pads(dsi, 0); + else if (dsi->data->model == DSI_MODEL_OMAP5) + dsi_omap5_mux_pads(dsi, 0); +} + static int dsi_cio_init(struct platform_device *dsidev) { struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); @@ -2068,7 +2176,7 @@ static int dsi_cio_init(struct platform_device *dsidev) DSSDBG("DSI CIO init starts"); - r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); + r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsidev)); if (r) return r; @@ -2178,7 +2286,7 @@ err_cio_pwr: dsi_cio_disable_lane_override(dsidev); err_scp_clk_dom: dsi_disable_scp_clk(dsidev); - dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); + dsi_disable_pads(dsi); return r; } @@ -2191,7 +2299,7 @@ static void dsi_cio_uninit(struct platform_device *dsidev) dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); dsi_disable_scp_clk(dsidev); - dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); + dsi_disable_pads(dsi); } static void dsi_config_tx_fifo(struct platform_device *dsidev, @@ -2439,7 +2547,7 @@ static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ - if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) + if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH) r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ @@ -2474,7 +2582,7 @@ static int dsi_vc_config_source(struct platform_device *dsidev, int channel, REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); /* DCS_CMD_ENABLE */ - if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { + if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) { bool enable = source == DSI_VC_SOURCE_VP; REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); } @@ -3607,7 +3715,7 @@ static int dsi_proto_config(struct platform_device *dsidev) r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ - if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { + if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) { r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ /* DCS_CMD_CODE, 1=start, 0=continue */ r = FLD_MOD(r, 0, 25, 25); @@ -4450,6 +4558,7 @@ static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, unsigned long clkdco, void *data) { struct dsi_clk_calc_ctx *ctx = data; + struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); ctx->dsi_cinfo.n = n; ctx->dsi_cinfo.m = m; @@ -4457,7 +4566,7 @@ static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, ctx->dsi_cinfo.clkdco = clkdco; return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, - dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), + dsi->data->max_fck_freq, dsi_cm_calc_hsdiv_cb, ctx); } @@ -4749,6 +4858,7 @@ static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, unsigned long clkdco, void *data) { struct dsi_clk_calc_ctx *ctx = data; + struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); ctx->dsi_cinfo.n = n; ctx->dsi_cinfo.m = m; @@ -4756,7 +4866,7 @@ static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, ctx->dsi_cinfo.clkdco = clkdco; return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, - dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), + dsi->data->max_fck_freq, dsi_vm_calc_hsdiv_cb, ctx); } @@ -4827,7 +4937,7 @@ static int dsi_set_config(struct omap_dss_device *dssdev, goto err; } - dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo); + dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo); r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); @@ -4857,24 +4967,14 @@ err: * the channel in some more dynamic manner, or get the channel as a user * parameter. */ -static enum omap_channel dsi_get_channel(int module_id) +static enum omap_channel dsi_get_channel(struct dsi_data *dsi) { - switch (omapdss_get_version()) { - case OMAPDSS_VER_OMAP24xx: - case OMAPDSS_VER_AM43xx: - DSSWARN("DSI not supported\n"); + switch (dsi->data->model) { + case DSI_MODEL_OMAP3: return OMAP_DSS_CHANNEL_LCD; - case OMAPDSS_VER_OMAP34xx_ES1: - case OMAPDSS_VER_OMAP34xx_ES3: - case OMAPDSS_VER_OMAP3630: - case OMAPDSS_VER_AM35xx: - return OMAP_DSS_CHANNEL_LCD; - - case OMAPDSS_VER_OMAP4430_ES1: - case OMAPDSS_VER_OMAP4430_ES2: - case OMAPDSS_VER_OMAP4: - switch (module_id) { + case DSI_MODEL_OMAP4: + switch (dsi->module_id) { case 0: return OMAP_DSS_CHANNEL_LCD; case 1: @@ -4884,8 +4984,8 @@ static enum omap_channel dsi_get_channel(int module_id) return OMAP_DSS_CHANNEL_LCD; } - case OMAPDSS_VER_OMAP5: - switch (module_id) { + case DSI_MODEL_OMAP5: + switch (dsi->module_id) { case 0: return OMAP_DSS_CHANNEL_LCD; case 1: @@ -5065,7 +5165,7 @@ static void dsi_init_output(struct platform_device *dsidev) out->output_type = OMAP_DISPLAY_TYPE_DSI; out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; - out->dispc_channel = dsi_get_channel(dsi->module_id); + out->dispc_channel = dsi_get_channel(dsi); out->ops.dsi = &dsi_ops; out->owner = THIS_MODULE; @@ -5240,29 +5340,7 @@ static int dsi_init_pll_data(struct platform_device *dsidev) pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; pll->clkin = clk; pll->base = dsi->pll_base; - - switch (omapdss_get_version()) { - case OMAPDSS_VER_OMAP34xx_ES1: - case OMAPDSS_VER_OMAP34xx_ES3: - case OMAPDSS_VER_OMAP3630: - case OMAPDSS_VER_AM35xx: - pll->hw = &dss_omap3_dsi_pll_hw; - break; - - case OMAPDSS_VER_OMAP4430_ES1: - case OMAPDSS_VER_OMAP4430_ES2: - case OMAPDSS_VER_OMAP4: - pll->hw = &dss_omap4_dsi_pll_hw; - break; - - case OMAPDSS_VER_OMAP5: - pll->hw = &dss_omap5_dsi_pll_hw; - break; - - default: - return -ENODEV; - } - + pll->hw = dsi->data->pll_hw; pll->ops = &dsi_pll_ops; r = dss_pll_register(pll); @@ -5273,15 +5351,80 @@ static int dsi_init_pll_data(struct platform_device *dsidev) } /* DSI1 HW IP initialisation */ +static const struct dsi_of_data dsi_of_data_omap34xx = { + .model = DSI_MODEL_OMAP3, + .pll_hw = &dss_omap3_dsi_pll_hw, + .modules = (const struct dsi_module_id_data[]) { + { .address = 0x4804fc00, .id = 0, }, + { }, + }, + .max_fck_freq = 173000000, + .max_pll_lpdiv = (1 << 13) - 1, + .quirks = DSI_QUIRK_REVERSE_TXCLKESC, +}; + +static const struct dsi_of_data dsi_of_data_omap36xx = { + .model = DSI_MODEL_OMAP3, + .pll_hw = &dss_omap3_dsi_pll_hw, + .modules = (const struct dsi_module_id_data[]) { + { .address = 0x4804fc00, .id = 0, }, + { }, + }, + .max_fck_freq = 173000000, + .max_pll_lpdiv = (1 << 13) - 1, + .quirks = DSI_QUIRK_PLL_PWR_BUG, +}; + +static const struct dsi_of_data dsi_of_data_omap4 = { + .model = DSI_MODEL_OMAP4, + .pll_hw = &dss_omap4_dsi_pll_hw, + .modules = (const struct dsi_module_id_data[]) { + { .address = 0x58004000, .id = 0, }, + { .address = 0x58005000, .id = 1, }, + { }, + }, + .max_fck_freq = 170000000, + .max_pll_lpdiv = (1 << 13) - 1, + .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH + | DSI_QUIRK_GNQ, +}; + +static const struct dsi_of_data dsi_of_data_omap5 = { + .model = DSI_MODEL_OMAP5, + .pll_hw = &dss_omap5_dsi_pll_hw, + .modules = (const struct dsi_module_id_data[]) { + { .address = 0x58004000, .id = 0, }, + { .address = 0x58009000, .id = 1, }, + { }, + }, + .max_fck_freq = 209250000, + .max_pll_lpdiv = (1 << 13) - 1, + .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH + | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC, +}; + +static const struct of_device_id dsi_of_match[] = { + { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, }, + { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, }, + { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, }, + {}, +}; + +static const struct soc_device_attribute dsi_soc_devices[] = { + { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx }, + { .machine = "AM35*", .data = &dsi_of_data_omap34xx }, + { /* sentinel */ } +}; static int dsi_bind(struct device *dev, struct device *master, void *data) { struct platform_device *dsidev = to_platform_device(dev); + const struct soc_device_attribute *soc; + const struct dsi_module_id_data *d; u32 rev; int r, i; struct dsi_data *dsi; struct resource *dsi_mem; struct resource *res; - struct resource temp_res; dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); if (!dsi) @@ -5311,67 +5454,20 @@ static int dsi_bind(struct device *dev, struct device *master, void *data) dsi->te_timer.data = 0; #endif - res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); - if (!res) { - res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); - if (!res) { - DSSERR("can't get IORESOURCE_MEM DSI\n"); - return -EINVAL; - } - - temp_res.start = res->start; - temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; - res = &temp_res; - } - - dsi_mem = res; - - dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, - resource_size(res)); - if (!dsi->proto_base) { - DSSERR("can't ioremap DSI protocol engine\n"); - return -ENOMEM; - } + dsi_mem = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); + dsi->proto_base = devm_ioremap_resource(&dsidev->dev, dsi_mem); + if (IS_ERR(dsi->proto_base)) + return PTR_ERR(dsi->proto_base); res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); - if (!res) { - res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); - if (!res) { - DSSERR("can't get IORESOURCE_MEM DSI\n"); - return -EINVAL; - } - - temp_res.start = res->start + DSI_PHY_OFFSET; - temp_res.end = temp_res.start + DSI_PHY_SZ - 1; - res = &temp_res; - } - - dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, - resource_size(res)); - if (!dsi->phy_base) { - DSSERR("can't ioremap DSI PHY\n"); - return -ENOMEM; - } + dsi->phy_base = devm_ioremap_resource(&dsidev->dev, res); + if (IS_ERR(dsi->phy_base)) + return PTR_ERR(dsi->phy_base); res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); - if (!res) { - res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); - if (!res) { - DSSERR("can't get IORESOURCE_MEM DSI\n"); - return -EINVAL; - } - - temp_res.start = res->start + DSI_PLL_OFFSET; - temp_res.end = temp_res.start + DSI_PLL_SZ - 1; - res = &temp_res; - } - - dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, - resource_size(res)); - if (!dsi->pll_base) { - DSSERR("can't ioremap DSI PLL\n"); - return -ENOMEM; - } + dsi->pll_base = devm_ioremap_resource(&dsidev->dev, res); + if (IS_ERR(dsi->pll_base)) + return PTR_ERR(dsi->pll_base); dsi->irq = platform_get_irq(dsi->pdev, 0); if (dsi->irq < 0) { @@ -5386,29 +5482,39 @@ static int dsi_bind(struct device *dev, struct device *master, void *data) return r; } - if (dsidev->dev.of_node) { - const struct of_device_id *match; - const struct dsi_module_id_data *d; + soc = soc_device_match(dsi_soc_devices); + if (soc) + dsi->data = soc->data; + else + dsi->data = of_match_node(dsi_of_match, dev->of_node)->data; - match = of_match_node(dsi_of_match, dsidev->dev.of_node); - if (!match) { - DSSERR("unsupported DSI module\n"); - return -ENODEV; - } + d = dsi->data->modules; + while (d->address != 0 && d->address != dsi_mem->start) + d++; + + if (d->address == 0) { + DSSERR("unsupported DSI module\n"); + return -ENODEV; + } - d = match->data; + dsi->module_id = d->id; - while (d->address != 0 && d->address != dsi_mem->start) - d++; + if (dsi->data->model == DSI_MODEL_OMAP4 || + dsi->data->model == DSI_MODEL_OMAP5) { + struct device_node *np; - if (d->address == 0) { - DSSERR("unsupported DSI module\n"); + /* + * The OMAP4/5 display DT bindings don't reference the padconf + * syscon. Our only option to retrieve it is to find it by name. + */ + np = of_find_node_by_name(NULL, + dsi->data->model == DSI_MODEL_OMAP4 ? + "omap4_padconf_global" : "omap5_padconf_global"); + if (!np) return -ENODEV; - } - dsi->module_id = d->id; - } else { - dsi->module_id = dsidev->id; + dsi->syscon = syscon_node_to_regmap(np); + of_node_put(np); } /* DSI VCs initialization */ @@ -5436,7 +5542,7 @@ static int dsi_bind(struct device *dev, struct device *master, void *data) /* DSI on OMAP3 doesn't have register DSI_GNQ, set number * of data to 3 by default */ - if (dss_has_feature(FEAT_DSI_GNQ)) + if (dsi->data->quirks & DSI_QUIRK_GNQ) /* NB_DATA_LANES */ dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); else @@ -5446,19 +5552,16 @@ static int dsi_bind(struct device *dev, struct device *master, void *data) dsi_init_output(dsidev); - if (dsidev->dev.of_node) { - r = dsi_probe_of(dsidev); - if (r) { - DSSERR("Invalid DSI DT data\n"); - goto err_probe_of; - } - - r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, - &dsidev->dev); - if (r) - DSSERR("Failed to populate DSI child devices: %d\n", r); + r = dsi_probe_of(dsidev); + if (r) { + DSSERR("Invalid DSI DT data\n"); + goto err_probe_of; } + r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, &dsidev->dev); + if (r) + DSSERR("Failed to populate DSI child devices: %d\n", r); + dsi_runtime_put(dsidev); if (dsi->module_id == 0) @@ -5559,30 +5662,6 @@ static const struct dev_pm_ops dsi_pm_ops = { .runtime_resume = dsi_runtime_resume, }; -static const struct dsi_module_id_data dsi_of_data_omap3[] = { - { .address = 0x4804fc00, .id = 0, }, - { }, -}; - -static const struct dsi_module_id_data dsi_of_data_omap4[] = { - { .address = 0x58004000, .id = 0, }, - { .address = 0x58005000, .id = 1, }, - { }, -}; - -static const struct dsi_module_id_data dsi_of_data_omap5[] = { - { .address = 0x58004000, .id = 0, }, - { .address = 0x58009000, .id = 1, }, - { }, -}; - -static const struct of_device_id dsi_of_match[] = { - { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, - { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, - { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, - {}, -}; - static struct platform_driver omap_dsihw_driver = { .probe = dsi_probe, .remove = dsi_remove, diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c index fa99ec72d832..d1755f12236b 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.c +++ b/drivers/gpu/drm/omapdrm/dss/dss.c @@ -22,6 +22,7 @@ #define DSS_SUBSYS_NAME "DSS" +#include <linux/debugfs.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/io.h> @@ -38,14 +39,15 @@ #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/of_graph.h> #include <linux/regulator/consumer.h> #include <linux/suspend.h> #include <linux/component.h> +#include <linux/sys_soc.h> #include "omapdss.h" #include "dss.h" -#include "dss_features.h" #define DSS_SZ_REGS SZ_512 @@ -69,15 +71,24 @@ struct dss_reg { #define REG_FLD_MOD(idx, val, start, end) \ dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) +struct dss_ops { + int (*dpi_select_source)(int port, enum omap_channel channel); + int (*select_lcd_source)(enum omap_channel channel, + enum dss_clk_source clk_src); +}; + struct dss_features { + enum dss_model model; u8 fck_div_max; + unsigned int fck_freq_max; u8 dss_fck_multiplier; const char *parent_clk_name; const enum omap_display_type *ports; int num_ports; - int (*dpi_select_source)(int port, enum omap_channel channel); - int (*select_lcd_source)(enum omap_channel channel, - enum dss_clk_source clk_src); + const enum omap_dss_output_id *outputs; + const struct dss_ops *ops; + struct dss_reg_field dispc_clk_switch; + bool has_lcd_clk_src; }; static struct { @@ -139,8 +150,7 @@ static void dss_save_context(void) SR(CONTROL); - if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & - OMAP_DISPLAY_TYPE_SDI) { + if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { SR(SDI_CONTROL); SR(PLL_CONTROL); } @@ -159,8 +169,7 @@ static void dss_restore_context(void) RR(CONTROL); - if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & - OMAP_DISPLAY_TYPE_SDI) { + if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { RR(SDI_CONTROL); RR(PLL_CONTROL); } @@ -390,8 +399,7 @@ static void dss_dump_regs(struct seq_file *s) DUMPREG(DSS_SYSSTATUS); DUMPREG(DSS_CONTROL); - if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & - OMAP_DISPLAY_TYPE_SDI) { + if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { DUMPREG(DSS_SDI_CONTROL); DUMPREG(DSS_PLL_CONTROL); DUMPREG(DSS_SDI_STATUS); @@ -419,14 +427,12 @@ static int dss_get_channel_index(enum omap_channel channel) static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) { int b; - u8 start, end; /* * We always use PRCM clock as the DISPC func clock, except on DSS3, * where we don't have separate DISPC and LCD clock sources. */ - if (WARN_ON(dss_has_feature(FEAT_LCD_CLK_SRC) && - clk_src != DSS_CLK_SRC_FCK)) + if (WARN_ON(dss.feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK)) return; switch (clk_src) { @@ -444,9 +450,9 @@ static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) return; } - dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); - - REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ + REG_FLD_MOD(DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ + dss.feat->dispc_clk_switch.start, + dss.feat->dispc_clk_switch.end); dss.dispc_clk_source = clk_src; } @@ -570,13 +576,13 @@ void dss_select_lcd_clk_source(enum omap_channel channel, int idx = dss_get_channel_index(channel); int r; - if (!dss_has_feature(FEAT_LCD_CLK_SRC)) { + if (!dss.feat->has_lcd_clk_src) { dss_select_dispc_clk_source(clk_src); dss.lcd_clk_source[idx] = clk_src; return; } - r = dss.feat->select_lcd_source(channel, clk_src); + r = dss.feat->ops->select_lcd_source(channel, clk_src); if (r) return; @@ -595,7 +601,7 @@ enum dss_clk_source dss_get_dsi_clk_source(int dsi_module) enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) { - if (dss_has_feature(FEAT_LCD_CLK_SRC)) { + if (dss.feat->has_lcd_clk_src) { int idx = dss_get_channel_index(channel); return dss.lcd_clk_source[idx]; } else { @@ -615,7 +621,7 @@ bool dss_div_calc(unsigned long pck, unsigned long fck_min, unsigned long prate; unsigned m; - fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); + fck_hw_max = dss.feat->fck_freq_max; if (dss.parent_clk == NULL) { unsigned pckd; @@ -673,6 +679,16 @@ unsigned long dss_get_dispc_clk_rate(void) return dss.dss_clk_rate; } +unsigned long dss_get_max_fck_rate(void) +{ + return dss.feat->fck_freq_max; +} + +enum omap_dss_output_id dss_get_supported_outputs(enum omap_channel channel) +{ + return dss.feat->outputs[channel]; +} + static int dss_setup_default_clock(void) { unsigned long max_dss_fck, prate; @@ -680,7 +696,7 @@ static int dss_setup_default_clock(void) unsigned fck_div; int r; - max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); + max_dss_fck = dss.feat->fck_freq_max; if (dss.parent_clk == NULL) { fck = clk_round_rate(dss.dss_clk, max_dss_fck); @@ -721,27 +737,29 @@ void dss_set_dac_pwrdn_bgz(bool enable) void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) { - enum omap_display_type dp; - dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); + enum omap_dss_output_id outputs; + + outputs = dss.feat->outputs[OMAP_DSS_CHANNEL_DIGIT]; /* Complain about invalid selections */ - WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC)); - WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI)); + WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC)); + WARN_ON((src == DSS_HDMI_M_PCLK) && !(outputs & OMAP_DSS_OUTPUT_HDMI)); /* Select only if we have options */ - if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI)) + if ((outputs & OMAP_DSS_OUTPUT_VENC) && + (outputs & OMAP_DSS_OUTPUT_HDMI)) REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ } enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) { - enum omap_display_type displays; + enum omap_dss_output_id outputs; - displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); - if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) + outputs = dss.feat->outputs[OMAP_DSS_CHANNEL_DIGIT]; + if ((outputs & OMAP_DSS_OUTPUT_HDMI) == 0) return DSS_VENC_TV_CLK; - if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0) + if ((outputs & OMAP_DSS_OUTPUT_VENC) == 0) return DSS_HDMI_M_PCLK; return REG_GET(DSS_CONTROL, 15, 15); @@ -823,7 +841,7 @@ static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel) int dss_dpi_select_source(int port, enum omap_channel channel) { - return dss.feat->dpi_select_source(port, channel); + return dss.feat->ops->dpi_select_source(port, channel); } static int dss_get_clocks(void) @@ -882,7 +900,7 @@ void dss_runtime_put(void) /* DEBUGFS */ #if defined(CONFIG_OMAP2_DSS_DEBUGFS) -void dss_debug_dump_clocks(struct seq_file *s) +static void dss_debug_dump_clocks(struct seq_file *s) { dss_dump_clocks(s); dispc_dump_clocks(s); @@ -890,8 +908,88 @@ void dss_debug_dump_clocks(struct seq_file *s) dsi_dump_clocks(s); #endif } -#endif +static int dss_debug_show(struct seq_file *s, void *unused) +{ + void (*func)(struct seq_file *) = s->private; + + func(s); + return 0; +} + +static int dss_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, dss_debug_show, inode->i_private); +} + +static const struct file_operations dss_debug_fops = { + .open = dss_debug_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static struct dentry *dss_debugfs_dir; + +static int dss_initialize_debugfs(void) +{ + dss_debugfs_dir = debugfs_create_dir("omapdss", NULL); + if (IS_ERR(dss_debugfs_dir)) { + int err = PTR_ERR(dss_debugfs_dir); + + dss_debugfs_dir = NULL; + return err; + } + + debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir, + &dss_debug_dump_clocks, &dss_debug_fops); + + return 0; +} + +static void dss_uninitialize_debugfs(void) +{ + if (dss_debugfs_dir) + debugfs_remove_recursive(dss_debugfs_dir); +} + +int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)) +{ + struct dentry *d; + + d = debugfs_create_file(name, S_IRUGO, dss_debugfs_dir, + write, &dss_debug_fops); + + return PTR_ERR_OR_ZERO(d); +} +#else /* CONFIG_OMAP2_DSS_DEBUGFS */ +static inline int dss_initialize_debugfs(void) +{ + return 0; +} +static inline void dss_uninitialize_debugfs(void) +{ +} +#endif /* CONFIG_OMAP2_DSS_DEBUGFS */ + +static const struct dss_ops dss_ops_omap2_omap3 = { + .dpi_select_source = &dss_dpi_select_source_omap2_omap3, +}; + +static const struct dss_ops dss_ops_omap4 = { + .dpi_select_source = &dss_dpi_select_source_omap4, + .select_lcd_source = &dss_lcd_clk_mux_omap4, +}; + +static const struct dss_ops dss_ops_omap5 = { + .dpi_select_source = &dss_dpi_select_source_omap5, + .select_lcd_source = &dss_lcd_clk_mux_omap5, +}; + +static const struct dss_ops dss_ops_dra7 = { + .dpi_select_source = &dss_dpi_select_source_dra7xx, + .select_lcd_source = &dss_lcd_clk_mux_dra7, +}; static const enum omap_display_type omap2plus_ports[] = { OMAP_DISPLAY_TYPE_DPI, @@ -908,130 +1006,168 @@ static const enum omap_display_type dra7xx_ports[] = { OMAP_DISPLAY_TYPE_DPI, }; +static const enum omap_dss_output_id omap2_dss_supported_outputs[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DSS_OUTPUT_VENC, +}; + +static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | + OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DSS_OUTPUT_VENC, +}; + +static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | + OMAP_DSS_OUTPUT_DSI1, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DSS_OUTPUT_VENC, +}; + +static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, +}; + +static const enum omap_dss_output_id omap4_dss_supported_outputs[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI, + + /* OMAP_DSS_CHANNEL_LCD2 */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | + OMAP_DSS_OUTPUT_DSI2, +}; + +static const enum omap_dss_output_id omap5_dss_supported_outputs[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | + OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DSS_OUTPUT_HDMI, + + /* OMAP_DSS_CHANNEL_LCD2 */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | + OMAP_DSS_OUTPUT_DSI1, + + /* OMAP_DSS_CHANNEL_LCD3 */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | + OMAP_DSS_OUTPUT_DSI2, +}; + static const struct dss_features omap24xx_dss_feats = { + .model = DSS_MODEL_OMAP2, /* * fck div max is really 16, but the divider range has gaps. The range * from 1 to 6 has no gaps, so let's use that as a max. */ .fck_div_max = 6, + .fck_freq_max = 133000000, .dss_fck_multiplier = 2, .parent_clk_name = "core_ck", - .dpi_select_source = &dss_dpi_select_source_omap2_omap3, .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), + .outputs = omap2_dss_supported_outputs, + .ops = &dss_ops_omap2_omap3, + .dispc_clk_switch = { 0, 0 }, + .has_lcd_clk_src = false, }; static const struct dss_features omap34xx_dss_feats = { + .model = DSS_MODEL_OMAP3, .fck_div_max = 16, + .fck_freq_max = 173000000, .dss_fck_multiplier = 2, .parent_clk_name = "dpll4_ck", - .dpi_select_source = &dss_dpi_select_source_omap2_omap3, .ports = omap34xx_ports, + .outputs = omap3430_dss_supported_outputs, .num_ports = ARRAY_SIZE(omap34xx_ports), + .ops = &dss_ops_omap2_omap3, + .dispc_clk_switch = { 0, 0 }, + .has_lcd_clk_src = false, }; static const struct dss_features omap3630_dss_feats = { + .model = DSS_MODEL_OMAP3, .fck_div_max = 32, + .fck_freq_max = 173000000, .dss_fck_multiplier = 1, .parent_clk_name = "dpll4_ck", - .dpi_select_source = &dss_dpi_select_source_omap2_omap3, .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), + .outputs = omap3630_dss_supported_outputs, + .ops = &dss_ops_omap2_omap3, + .dispc_clk_switch = { 0, 0 }, + .has_lcd_clk_src = false, }; static const struct dss_features omap44xx_dss_feats = { + .model = DSS_MODEL_OMAP4, .fck_div_max = 32, + .fck_freq_max = 186000000, .dss_fck_multiplier = 1, .parent_clk_name = "dpll_per_x2_ck", - .dpi_select_source = &dss_dpi_select_source_omap4, .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), - .select_lcd_source = &dss_lcd_clk_mux_omap4, + .outputs = omap4_dss_supported_outputs, + .ops = &dss_ops_omap4, + .dispc_clk_switch = { 9, 8 }, + .has_lcd_clk_src = true, }; static const struct dss_features omap54xx_dss_feats = { + .model = DSS_MODEL_OMAP5, .fck_div_max = 64, + .fck_freq_max = 209250000, .dss_fck_multiplier = 1, .parent_clk_name = "dpll_per_x2_ck", - .dpi_select_source = &dss_dpi_select_source_omap5, .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), - .select_lcd_source = &dss_lcd_clk_mux_omap5, + .outputs = omap5_dss_supported_outputs, + .ops = &dss_ops_omap5, + .dispc_clk_switch = { 9, 7 }, + .has_lcd_clk_src = true, }; static const struct dss_features am43xx_dss_feats = { + .model = DSS_MODEL_OMAP3, .fck_div_max = 0, + .fck_freq_max = 200000000, .dss_fck_multiplier = 0, .parent_clk_name = NULL, - .dpi_select_source = &dss_dpi_select_source_omap2_omap3, .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), + .outputs = am43xx_dss_supported_outputs, + .ops = &dss_ops_omap2_omap3, + .dispc_clk_switch = { 0, 0 }, + .has_lcd_clk_src = true, }; static const struct dss_features dra7xx_dss_feats = { + .model = DSS_MODEL_DRA7, .fck_div_max = 64, + .fck_freq_max = 209250000, .dss_fck_multiplier = 1, .parent_clk_name = "dpll_per_x2_ck", - .dpi_select_source = &dss_dpi_select_source_dra7xx, .ports = dra7xx_ports, .num_ports = ARRAY_SIZE(dra7xx_ports), - .select_lcd_source = &dss_lcd_clk_mux_dra7, + .outputs = omap5_dss_supported_outputs, + .ops = &dss_ops_dra7, + .dispc_clk_switch = { 9, 7 }, + .has_lcd_clk_src = true, }; -static int dss_init_features(struct platform_device *pdev) -{ - const struct dss_features *src; - struct dss_features *dst; - - dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); - if (!dst) { - dev_err(&pdev->dev, "Failed to allocate local DSS Features\n"); - return -ENOMEM; - } - - switch (omapdss_get_version()) { - case OMAPDSS_VER_OMAP24xx: - src = &omap24xx_dss_feats; - break; - - case OMAPDSS_VER_OMAP34xx_ES1: - case OMAPDSS_VER_OMAP34xx_ES3: - case OMAPDSS_VER_AM35xx: - src = &omap34xx_dss_feats; - break; - - case OMAPDSS_VER_OMAP3630: - src = &omap3630_dss_feats; - break; - - case OMAPDSS_VER_OMAP4430_ES1: - case OMAPDSS_VER_OMAP4430_ES2: - case OMAPDSS_VER_OMAP4: - src = &omap44xx_dss_feats; - break; - - case OMAPDSS_VER_OMAP5: - src = &omap54xx_dss_feats; - break; - - case OMAPDSS_VER_AM43xx: - src = &am43xx_dss_feats; - break; - - case OMAPDSS_VER_DRA7xx: - src = &dra7xx_dss_feats; - break; - - default: - return -ENODEV; - } - - memcpy(dst, src, sizeof(*dst)); - dss.feat = dst; - - return 0; -} - static int dss_init_ports(struct platform_device *pdev) { struct device_node *parent = pdev->dev.of_node; @@ -1045,7 +1181,7 @@ static int dss_init_ports(struct platform_device *pdev) switch (dss.feat->ports[i]) { case OMAP_DISPLAY_TYPE_DPI: - dpi_init_port(pdev, port); + dpi_init_port(pdev, port, dss.feat->model); break; case OMAP_DISPLAY_TYPE_SDI: sdi_init_port(pdev, port); @@ -1144,6 +1280,23 @@ static int dss_video_pll_probe(struct platform_device *pdev) } /* DSS HW IP initialisation */ +static const struct of_device_id dss_of_match[] = { + { .compatible = "ti,omap2-dss", .data = &omap24xx_dss_feats }, + { .compatible = "ti,omap3-dss", .data = &omap3630_dss_feats }, + { .compatible = "ti,omap4-dss", .data = &omap44xx_dss_feats }, + { .compatible = "ti,omap5-dss", .data = &omap54xx_dss_feats }, + { .compatible = "ti,dra7-dss", .data = &dra7xx_dss_feats }, + {}, +}; +MODULE_DEVICE_TABLE(of, dss_of_match); + +static const struct soc_device_attribute dss_soc_devices[] = { + { .machine = "OMAP3430/3530", .data = &omap34xx_dss_feats }, + { .machine = "AM35??", .data = &omap34xx_dss_feats }, + { .family = "AM43xx", .data = &am43xx_dss_feats }, + { /* sentinel */ } +}; + static int dss_bind(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -1151,24 +1304,10 @@ static int dss_bind(struct device *dev) u32 rev; int r; - dss.pdev = pdev; - - r = dss_init_features(dss.pdev); - if (r) - return r; - dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); - if (!dss_mem) { - DSSERR("can't get IORESOURCE_MEM DSS\n"); - return -EINVAL; - } - - dss.base = devm_ioremap(&pdev->dev, dss_mem->start, - resource_size(dss_mem)); - if (!dss.base) { - DSSERR("can't ioremap DSS\n"); - return -ENOMEM; - } + dss.base = devm_ioremap_resource(&pdev->dev, dss_mem); + if (IS_ERR(dss.base)) + return PTR_ERR(dss.base); r = dss_get_clocks(); if (r) @@ -1296,15 +1435,34 @@ static int dss_add_child_component(struct device *dev, void *data) static int dss_probe(struct platform_device *pdev) { + const struct soc_device_attribute *soc; struct component_match *match = NULL; int r; + dss.pdev = pdev; + + /* + * The various OMAP3-based SoCs can't be told apart using the compatible + * string, use SoC device matching. + */ + soc = soc_device_match(dss_soc_devices); + if (soc) + dss.feat = soc->data; + else + dss.feat = of_match_device(dss_of_match, &pdev->dev)->data; + + r = dss_initialize_debugfs(); + if (r) + return r; + /* add all the child devices as components */ device_for_each_child(&pdev->dev, &match, dss_add_child_component); r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); - if (r) + if (r) { + dss_uninitialize_debugfs(); return r; + } return 0; } @@ -1312,9 +1470,27 @@ static int dss_probe(struct platform_device *pdev) static int dss_remove(struct platform_device *pdev) { component_master_del(&pdev->dev, &dss_component_ops); + + dss_uninitialize_debugfs(); + return 0; } +static void dss_shutdown(struct platform_device *pdev) +{ + struct omap_dss_device *dssdev = NULL; + + DSSDBG("shutdown\n"); + + for_each_dss_dev(dssdev) { + if (!dssdev->driver) + continue; + + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + dssdev->driver->disable(dssdev); + } +} + static int dss_runtime_suspend(struct device *dev) { dss_save_context(); @@ -1351,20 +1527,10 @@ static const struct dev_pm_ops dss_pm_ops = { .runtime_resume = dss_runtime_resume, }; -static const struct of_device_id dss_of_match[] = { - { .compatible = "ti,omap2-dss", }, - { .compatible = "ti,omap3-dss", }, - { .compatible = "ti,omap4-dss", }, - { .compatible = "ti,omap5-dss", }, - { .compatible = "ti,dra7-dss", }, - {}, -}; - -MODULE_DEVICE_TABLE(of, dss_of_match); - static struct platform_driver omap_dsshw_driver = { .probe = dss_probe, .remove = dss_remove, + .shutdown = dss_shutdown, .driver = { .name = "omapdss_dss", .pm = &dss_pm_ops, diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index 5dd29c98143a..ed465572491e 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -27,6 +27,9 @@ #include "omapdss.h" +#define MAX_DSS_LCD_MANAGERS 3 +#define MAX_NUM_DSI 2 + #ifdef pr_fmt #undef pr_fmt #endif @@ -72,6 +75,14 @@ #define FLD_MOD(orig, val, start, end) \ (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) +enum dss_model { + DSS_MODEL_OMAP2, + DSS_MODEL_OMAP3, + DSS_MODEL_OMAP4, + DSS_MODEL_OMAP5, + DSS_MODEL_DRA7, +}; + enum dss_io_pad_mode { DSS_IO_PAD_MODE_RESET, DSS_IO_PAD_MODE_RFBI, @@ -174,6 +185,9 @@ struct dss_pll_hw { bool has_freqsel; bool has_selfreqdco; bool has_refsel; + + /* DRA7 errata i886: use high N & M to avoid jitter */ + bool errata_i886; }; struct dss_pll { @@ -192,6 +206,11 @@ struct dss_pll { struct dss_pll_clock_info cinfo; }; +/* Defines a generic omap register field */ +struct dss_reg_field { + u8 start, end; +}; + struct dispc_clock_info { /* rates that we get with dividers below */ unsigned long lck; @@ -219,11 +238,11 @@ struct seq_file; struct platform_device; /* core */ -struct platform_device *dss_get_core_pdev(void); -int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask); -void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask); -int dss_set_min_bus_tput(struct device *dev, unsigned long tput); -int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); +static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput) +{ + /* To be implemented when the OMAP platform will provide this feature */ + return 0; +} static inline bool dss_mgr_is_lcd(enum omap_channel id) { @@ -235,6 +254,16 @@ static inline bool dss_mgr_is_lcd(enum omap_channel id) } /* DSS */ +#if defined(CONFIG_OMAP2_DSS_DEBUGFS) +int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); +#else +static inline int dss_debugfs_create_file(const char *name, + void (*write)(struct seq_file *)) +{ + return 0; +} +#endif /* CONFIG_OMAP2_DSS_DEBUGFS */ + int dss_init_platform_driver(void) __init; void dss_uninit_platform_driver(void); @@ -242,6 +271,8 @@ int dss_runtime_get(void); void dss_runtime_put(void); unsigned long dss_get_dispc_clk_rate(void); +unsigned long dss_get_max_fck_rate(void); +enum omap_dss_output_id dss_get_supported_outputs(enum omap_channel channel); int dss_dpi_select_source(int port, enum omap_channel channel); void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void); @@ -253,10 +284,6 @@ struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, struct regulator *regulator); void dss_video_pll_uninit(struct dss_pll *pll); -#if defined(CONFIG_OMAP2_DSS_DEBUGFS) -void dss_debug_dump_clocks(struct seq_file *s); -#endif - void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable); void dss_sdi_init(int datapairs); @@ -281,9 +308,6 @@ bool dss_div_calc(unsigned long pck, unsigned long fck_min, dss_div_calc_func func, void *data); /* SDI */ -int sdi_init_platform_driver(void) __init; -void sdi_uninit_platform_driver(void); - #ifdef CONFIG_OMAP2_DSS_SDI int sdi_init_port(struct platform_device *pdev, struct device_node *port); void sdi_uninit_port(struct device_node *port); @@ -315,15 +339,13 @@ void dsi_irq_handler(void); #endif /* DPI */ -int dpi_init_platform_driver(void) __init; -void dpi_uninit_platform_driver(void); - #ifdef CONFIG_OMAP2_DSS_DPI -int dpi_init_port(struct platform_device *pdev, struct device_node *port); +int dpi_init_port(struct platform_device *pdev, struct device_node *port, + enum dss_model dss_model); void dpi_uninit_port(struct device_node *port); #else static inline int dpi_init_port(struct platform_device *pdev, - struct device_node *port) + struct device_node *port, enum dss_model dss_model) { return 0; } @@ -389,10 +411,6 @@ void hdmi4_uninit_platform_driver(void); int hdmi5_init_platform_driver(void) __init; void hdmi5_uninit_platform_driver(void); -/* RFBI */ -int rfbi_init_platform_driver(void) __init; -void rfbi_uninit_platform_driver(void); - #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c deleted file mode 100644 index 80c6440a0e08..000000000000 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ /dev/null @@ -1,904 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dss_features.c - * - * Copyright (C) 2010 Texas Instruments - * Author: Archit Taneja <archit@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/err.h> -#include <linux/slab.h> - -#include "omapdss.h" -#include "dss.h" -#include "dss_features.h" - -/* Defines a generic omap register field */ -struct dss_reg_field { - u8 start, end; -}; - -struct dss_param_range { - int min, max; -}; - -struct omap_dss_features { - const struct dss_reg_field *reg_fields; - const int num_reg_fields; - - const enum dss_feat_id *features; - const int num_features; - - const int num_mgrs; - const int num_ovls; - const enum omap_display_type *supported_displays; - const enum omap_dss_output_id *supported_outputs; - const enum omap_color_mode *supported_color_modes; - const enum omap_overlay_caps *overlay_caps; - const struct dss_param_range *dss_params; - - const enum omap_dss_rotation_type supported_rotation_types; - - const u32 buffer_size_unit; - const u32 burst_size_unit; -}; - -/* This struct is assigned to one of the below during initialization */ -static const struct omap_dss_features *omap_current_dss_features; - -static const struct dss_reg_field omap2_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 11, 0 }, - [FEAT_REG_FIRVINC] = { 27, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, - [FEAT_REG_FIFOSIZE] = { 8, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, - [FEAT_REG_VERTICALACCU] = { 25, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, -}; - -static const struct dss_reg_field omap3_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, - [FEAT_REG_FIFOSIZE] = { 10, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, - [FEAT_REG_VERTICALACCU] = { 25, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, -}; - -static const struct dss_reg_field am43xx_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, - [FEAT_REG_FIFOSIZE] = { 10, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, - [FEAT_REG_VERTICALACCU] = { 25, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, -}; - -static const struct dss_reg_field omap4_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, - [FEAT_REG_FIFOSIZE] = { 15, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, - [FEAT_REG_VERTICALACCU] = { 26, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 }, -}; - -static const struct dss_reg_field omap5_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, - [FEAT_REG_FIFOSIZE] = { 15, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, - [FEAT_REG_VERTICALACCU] = { 26, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 }, -}; - -static const enum omap_display_type omap2_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC, -}; - -static const enum omap_display_type omap3430_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC, -}; - -static const enum omap_display_type omap3630_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC, -}; - -static const enum omap_display_type am43xx_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI, -}; - -static const enum omap_display_type omap4_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI, - - /* OMAP_DSS_CHANNEL_LCD2 */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_DSI, -}; - -static const enum omap_display_type omap5_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI, - - /* OMAP_DSS_CHANNEL_LCD2 */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_DSI, -}; - -static const enum omap_dss_output_id omap2_dss_supported_outputs[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DSS_OUTPUT_VENC, -}; - -static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | - OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DSS_OUTPUT_VENC, -}; - -static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | - OMAP_DSS_OUTPUT_DSI1, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DSS_OUTPUT_VENC, -}; - -static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, -}; - -static const enum omap_dss_output_id omap4_dss_supported_outputs[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI, - - /* OMAP_DSS_CHANNEL_LCD2 */ - OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | - OMAP_DSS_OUTPUT_DSI2, -}; - -static const enum omap_dss_output_id omap5_dss_supported_outputs[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | - OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DSS_OUTPUT_HDMI, - - /* OMAP_DSS_CHANNEL_LCD2 */ - OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | - OMAP_DSS_OUTPUT_DSI1, - - /* OMAP_DSS_CHANNEL_LCD3 */ - OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | - OMAP_DSS_OUTPUT_DSI2, -}; - -static const enum omap_color_mode omap2_dss_supported_color_modes[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | - OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | - OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | - OMAP_DSS_COLOR_UYVY, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | - OMAP_DSS_COLOR_UYVY, -}; - -static const enum omap_color_mode omap3_dss_supported_color_modes[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | - OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | - OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | - OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, -}; - -static const enum omap_color_mode omap4_dss_supported_color_modes[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | - OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 | - OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 | - OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U | - OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 | - OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY | - OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 | - OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 | - OMAP_DSS_COLOR_RGBX32, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U | - OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 | - OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY | - OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 | - OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 | - OMAP_DSS_COLOR_RGBX32, - - /* OMAP_DSS_VIDEO3 */ - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U | - OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 | - OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY | - OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 | - OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 | - OMAP_DSS_COLOR_RGBX32, - - /* OMAP_DSS_WB */ - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U | - OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 | - OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY | - OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 | - OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 | - OMAP_DSS_COLOR_RGBX32, -}; - -static const enum omap_overlay_caps omap2_dss_overlay_caps[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, -}; - -static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, -}; - -static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, -}; - -static const enum omap_overlay_caps omap4_dss_overlay_caps[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | - OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO3 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, -}; - -static const struct dss_param_range omap2_dss_param_range[] = { - [FEAT_PARAM_DSS_FCK] = { 0, 133000000 }, - [FEAT_PARAM_DSS_PCD] = { 2, 255 }, - [FEAT_PARAM_DOWNSCALE] = { 1, 2 }, - /* - * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC - * scaler cannot scale a image with width more than 768. - */ - [FEAT_PARAM_LINEWIDTH] = { 1, 768 }, -}; - -static const struct dss_param_range omap3_dss_param_range[] = { - [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, - [FEAT_PARAM_DSS_PCD] = { 1, 255 }, - [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1}, - [FEAT_PARAM_DSI_FCK] = { 0, 173000000 }, - [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, - [FEAT_PARAM_LINEWIDTH] = { 1, 1024 }, -}; - -static const struct dss_param_range am43xx_dss_param_range[] = { - [FEAT_PARAM_DSS_FCK] = { 0, 200000000 }, - [FEAT_PARAM_DSS_PCD] = { 1, 255 }, - [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, - [FEAT_PARAM_LINEWIDTH] = { 1, 1024 }, -}; - -static const struct dss_param_range omap4_dss_param_range[] = { - [FEAT_PARAM_DSS_FCK] = { 0, 186000000 }, - [FEAT_PARAM_DSS_PCD] = { 1, 255 }, - [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 }, - [FEAT_PARAM_DSI_FCK] = { 0, 170000000 }, - [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, - [FEAT_PARAM_LINEWIDTH] = { 1, 2048 }, -}; - -static const struct dss_param_range omap5_dss_param_range[] = { - [FEAT_PARAM_DSS_FCK] = { 0, 209250000 }, - [FEAT_PARAM_DSS_PCD] = { 1, 255 }, - [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 }, - [FEAT_PARAM_DSI_FCK] = { 0, 209250000 }, - [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, - [FEAT_PARAM_LINEWIDTH] = { 1, 2048 }, -}; - -static const enum dss_feat_id omap2_dss_feat_list[] = { - FEAT_LCDENABLEPOL, - FEAT_LCDENABLESIGNAL, - FEAT_PCKFREEENABLE, - FEAT_FUNCGATED, - FEAT_ROWREPEATENABLE, - FEAT_RESIZECONF, -}; - -static const enum dss_feat_id omap3430_dss_feat_list[] = { - FEAT_LCDENABLEPOL, - FEAT_LCDENABLESIGNAL, - FEAT_PCKFREEENABLE, - FEAT_FUNCGATED, - FEAT_LINEBUFFERSPLIT, - FEAT_ROWREPEATENABLE, - FEAT_RESIZECONF, - FEAT_DSI_REVERSE_TXCLKESC, - FEAT_VENC_REQUIRES_TV_DAC_CLK, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FIXED_ZORDER, - FEAT_FIFO_MERGE, - FEAT_OMAP3_DSI_FIFO_BUG, - FEAT_DPI_USES_VDDS_DSI, -}; - -static const enum dss_feat_id am35xx_dss_feat_list[] = { - FEAT_LCDENABLEPOL, - FEAT_LCDENABLESIGNAL, - FEAT_PCKFREEENABLE, - FEAT_FUNCGATED, - FEAT_LINEBUFFERSPLIT, - FEAT_ROWREPEATENABLE, - FEAT_RESIZECONF, - FEAT_DSI_REVERSE_TXCLKESC, - FEAT_VENC_REQUIRES_TV_DAC_CLK, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FIXED_ZORDER, - FEAT_FIFO_MERGE, - FEAT_OMAP3_DSI_FIFO_BUG, -}; - -static const enum dss_feat_id am43xx_dss_feat_list[] = { - FEAT_LCDENABLEPOL, - FEAT_LCDENABLESIGNAL, - FEAT_PCKFREEENABLE, - FEAT_FUNCGATED, - FEAT_LINEBUFFERSPLIT, - FEAT_ROWREPEATENABLE, - FEAT_RESIZECONF, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FIXED_ZORDER, - FEAT_FIFO_MERGE, -}; - -static const enum dss_feat_id omap3630_dss_feat_list[] = { - FEAT_LCDENABLEPOL, - FEAT_LCDENABLESIGNAL, - FEAT_PCKFREEENABLE, - FEAT_FUNCGATED, - FEAT_LINEBUFFERSPLIT, - FEAT_ROWREPEATENABLE, - FEAT_RESIZECONF, - FEAT_DSI_PLL_PWR_BUG, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FIXED_ZORDER, - FEAT_FIFO_MERGE, - FEAT_OMAP3_DSI_FIFO_BUG, - FEAT_DPI_USES_VDDS_DSI, -}; - -static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = { - FEAT_MGR_LCD2, - FEAT_CORE_CLK_DIV, - FEAT_LCD_CLK_SRC, - FEAT_DSI_DCS_CMD_CONFIG_VC, - FEAT_DSI_VC_OCP_WIDTH, - FEAT_DSI_GNQ, - FEAT_HANDLE_UV_SEPARATE, - FEAT_ATTR2, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FREE_ZORDER, - FEAT_FIFO_MERGE, - FEAT_BURST_2D, -}; - -static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = { - FEAT_MGR_LCD2, - FEAT_CORE_CLK_DIV, - FEAT_LCD_CLK_SRC, - FEAT_DSI_DCS_CMD_CONFIG_VC, - FEAT_DSI_VC_OCP_WIDTH, - FEAT_DSI_GNQ, - FEAT_HDMI_CTS_SWMODE, - FEAT_HANDLE_UV_SEPARATE, - FEAT_ATTR2, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FREE_ZORDER, - FEAT_FIFO_MERGE, - FEAT_BURST_2D, -}; - -static const enum dss_feat_id omap4_dss_feat_list[] = { - FEAT_MGR_LCD2, - FEAT_CORE_CLK_DIV, - FEAT_LCD_CLK_SRC, - FEAT_DSI_DCS_CMD_CONFIG_VC, - FEAT_DSI_VC_OCP_WIDTH, - FEAT_DSI_GNQ, - FEAT_HDMI_CTS_SWMODE, - FEAT_HDMI_AUDIO_USE_MCLK, - FEAT_HANDLE_UV_SEPARATE, - FEAT_ATTR2, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FREE_ZORDER, - FEAT_FIFO_MERGE, - FEAT_BURST_2D, -}; - -static const enum dss_feat_id omap5_dss_feat_list[] = { - FEAT_MGR_LCD2, - FEAT_MGR_LCD3, - FEAT_CORE_CLK_DIV, - FEAT_LCD_CLK_SRC, - FEAT_DSI_DCS_CMD_CONFIG_VC, - FEAT_DSI_VC_OCP_WIDTH, - FEAT_DSI_GNQ, - FEAT_HDMI_CTS_SWMODE, - FEAT_HDMI_AUDIO_USE_MCLK, - FEAT_HANDLE_UV_SEPARATE, - FEAT_ATTR2, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FREE_ZORDER, - FEAT_FIFO_MERGE, - FEAT_BURST_2D, - FEAT_DSI_PHY_DCC, - FEAT_MFLAG, -}; - -/* OMAP2 DSS Features */ -static const struct omap_dss_features omap2_dss_features = { - .reg_fields = omap2_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields), - - .features = omap2_dss_feat_list, - .num_features = ARRAY_SIZE(omap2_dss_feat_list), - - .num_mgrs = 2, - .num_ovls = 3, - .supported_displays = omap2_dss_supported_displays, - .supported_outputs = omap2_dss_supported_outputs, - .supported_color_modes = omap2_dss_supported_color_modes, - .overlay_caps = omap2_dss_overlay_caps, - .dss_params = omap2_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB, - .buffer_size_unit = 1, - .burst_size_unit = 8, -}; - -/* OMAP3 DSS Features */ -static const struct omap_dss_features omap3430_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - - .features = omap3430_dss_feat_list, - .num_features = ARRAY_SIZE(omap3430_dss_feat_list), - - .num_mgrs = 2, - .num_ovls = 3, - .supported_displays = omap3430_dss_supported_displays, - .supported_outputs = omap3430_dss_supported_outputs, - .supported_color_modes = omap3_dss_supported_color_modes, - .overlay_caps = omap3430_dss_overlay_caps, - .dss_params = omap3_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB, - .buffer_size_unit = 1, - .burst_size_unit = 8, -}; - -/* - * AM35xx DSS Features. This is basically OMAP3 DSS Features without the - * vdds_dsi regulator. - */ -static const struct omap_dss_features am35xx_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - - .features = am35xx_dss_feat_list, - .num_features = ARRAY_SIZE(am35xx_dss_feat_list), - - .num_mgrs = 2, - .num_ovls = 3, - .supported_displays = omap3430_dss_supported_displays, - .supported_outputs = omap3430_dss_supported_outputs, - .supported_color_modes = omap3_dss_supported_color_modes, - .overlay_caps = omap3430_dss_overlay_caps, - .dss_params = omap3_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB, - .buffer_size_unit = 1, - .burst_size_unit = 8, -}; - -static const struct omap_dss_features am43xx_dss_features = { - .reg_fields = am43xx_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields), - - .features = am43xx_dss_feat_list, - .num_features = ARRAY_SIZE(am43xx_dss_feat_list), - - .num_mgrs = 1, - .num_ovls = 3, - .supported_displays = am43xx_dss_supported_displays, - .supported_outputs = am43xx_dss_supported_outputs, - .supported_color_modes = omap3_dss_supported_color_modes, - .overlay_caps = omap3430_dss_overlay_caps, - .dss_params = am43xx_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA, - .buffer_size_unit = 1, - .burst_size_unit = 8, -}; - -static const struct omap_dss_features omap3630_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - - .features = omap3630_dss_feat_list, - .num_features = ARRAY_SIZE(omap3630_dss_feat_list), - - .num_mgrs = 2, - .num_ovls = 3, - .supported_displays = omap3630_dss_supported_displays, - .supported_outputs = omap3630_dss_supported_outputs, - .supported_color_modes = omap3_dss_supported_color_modes, - .overlay_caps = omap3630_dss_overlay_caps, - .dss_params = omap3_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB, - .buffer_size_unit = 1, - .burst_size_unit = 8, -}; - -/* OMAP4 DSS Features */ -/* For OMAP4430 ES 1.0 revision */ -static const struct omap_dss_features omap4430_es1_0_dss_features = { - .reg_fields = omap4_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), - - .features = omap4430_es1_0_dss_feat_list, - .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list), - - .num_mgrs = 3, - .num_ovls = 4, - .supported_displays = omap4_dss_supported_displays, - .supported_outputs = omap4_dss_supported_outputs, - .supported_color_modes = omap4_dss_supported_color_modes, - .overlay_caps = omap4_dss_overlay_caps, - .dss_params = omap4_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER, - .buffer_size_unit = 16, - .burst_size_unit = 16, -}; - -/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */ -static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = { - .reg_fields = omap4_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), - - .features = omap4430_es2_0_1_2_dss_feat_list, - .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list), - - .num_mgrs = 3, - .num_ovls = 4, - .supported_displays = omap4_dss_supported_displays, - .supported_outputs = omap4_dss_supported_outputs, - .supported_color_modes = omap4_dss_supported_color_modes, - .overlay_caps = omap4_dss_overlay_caps, - .dss_params = omap4_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER, - .buffer_size_unit = 16, - .burst_size_unit = 16, -}; - -/* For all the other OMAP4 versions */ -static const struct omap_dss_features omap4_dss_features = { - .reg_fields = omap4_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), - - .features = omap4_dss_feat_list, - .num_features = ARRAY_SIZE(omap4_dss_feat_list), - - .num_mgrs = 3, - .num_ovls = 4, - .supported_displays = omap4_dss_supported_displays, - .supported_outputs = omap4_dss_supported_outputs, - .supported_color_modes = omap4_dss_supported_color_modes, - .overlay_caps = omap4_dss_overlay_caps, - .dss_params = omap4_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER, - .buffer_size_unit = 16, - .burst_size_unit = 16, -}; - -/* OMAP5 DSS Features */ -static const struct omap_dss_features omap5_dss_features = { - .reg_fields = omap5_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields), - - .features = omap5_dss_feat_list, - .num_features = ARRAY_SIZE(omap5_dss_feat_list), - - .num_mgrs = 4, - .num_ovls = 4, - .supported_displays = omap5_dss_supported_displays, - .supported_outputs = omap5_dss_supported_outputs, - .supported_color_modes = omap4_dss_supported_color_modes, - .overlay_caps = omap4_dss_overlay_caps, - .dss_params = omap5_dss_param_range, - .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER, - .buffer_size_unit = 16, - .burst_size_unit = 16, -}; - -/* Functions returning values related to a DSS feature */ -int dss_feat_get_num_mgrs(void) -{ - return omap_current_dss_features->num_mgrs; -} - -int dss_feat_get_num_ovls(void) -{ - return omap_current_dss_features->num_ovls; -} - -unsigned long dss_feat_get_param_min(enum dss_range_param param) -{ - return omap_current_dss_features->dss_params[param].min; -} - -unsigned long dss_feat_get_param_max(enum dss_range_param param) -{ - return omap_current_dss_features->dss_params[param].max; -} - -enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel) -{ - return omap_current_dss_features->supported_displays[channel]; -} - -enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel) -{ - return omap_current_dss_features->supported_outputs[channel]; -} - -enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane) -{ - return omap_current_dss_features->supported_color_modes[plane]; -} - -enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane) -{ - return omap_current_dss_features->overlay_caps[plane]; -} - -bool dss_feat_color_mode_supported(enum omap_plane_id plane, - enum omap_color_mode color_mode) -{ - return omap_current_dss_features->supported_color_modes[plane] & - color_mode; -} - -u32 dss_feat_get_buffer_size_unit(void) -{ - return omap_current_dss_features->buffer_size_unit; -} - -u32 dss_feat_get_burst_size_unit(void) -{ - return omap_current_dss_features->burst_size_unit; -} - -/* DSS has_feature check */ -bool dss_has_feature(enum dss_feat_id id) -{ - int i; - const enum dss_feat_id *features = omap_current_dss_features->features; - const int num_features = omap_current_dss_features->num_features; - - for (i = 0; i < num_features; i++) { - if (features[i] == id) - return true; - } - - return false; -} - -void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end) -{ - if (id >= omap_current_dss_features->num_reg_fields) - BUG(); - - *start = omap_current_dss_features->reg_fields[id].start; - *end = omap_current_dss_features->reg_fields[id].end; -} - -bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type) -{ - return omap_current_dss_features->supported_rotation_types & rot_type; -} - -void dss_features_init(enum omapdss_version version) -{ - switch (version) { - case OMAPDSS_VER_OMAP24xx: - omap_current_dss_features = &omap2_dss_features; - break; - - case OMAPDSS_VER_OMAP34xx_ES1: - case OMAPDSS_VER_OMAP34xx_ES3: - omap_current_dss_features = &omap3430_dss_features; - break; - - case OMAPDSS_VER_OMAP3630: - omap_current_dss_features = &omap3630_dss_features; - break; - - case OMAPDSS_VER_OMAP4430_ES1: - omap_current_dss_features = &omap4430_es1_0_dss_features; - break; - - case OMAPDSS_VER_OMAP4430_ES2: - omap_current_dss_features = &omap4430_es2_0_1_2_dss_features; - break; - - case OMAPDSS_VER_OMAP4: - omap_current_dss_features = &omap4_dss_features; - break; - - case OMAPDSS_VER_OMAP5: - case OMAPDSS_VER_DRA7xx: - omap_current_dss_features = &omap5_dss_features; - break; - - case OMAPDSS_VER_AM35xx: - omap_current_dss_features = &am35xx_dss_features; - break; - - case OMAPDSS_VER_AM43xx: - omap_current_dss_features = &am43xx_dss_features; - break; - - default: - DSSWARN("Unsupported OMAP version"); - break; - } -} diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h deleted file mode 100644 index 27fbe64935e8..000000000000 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dss_features.h - * - * Copyright (C) 2010 Texas Instruments - * Author: Archit Taneja <archit@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __OMAP2_DSS_FEATURES_H -#define __OMAP2_DSS_FEATURES_H - -#define MAX_DSS_MANAGERS 4 -#define MAX_DSS_OVERLAYS 4 -#define MAX_DSS_LCD_MANAGERS 3 -#define MAX_NUM_DSI 2 - -/* DSS has feature id */ -enum dss_feat_id { - FEAT_LCDENABLEPOL, - FEAT_LCDENABLESIGNAL, - FEAT_PCKFREEENABLE, - FEAT_FUNCGATED, - FEAT_MGR_LCD2, - FEAT_MGR_LCD3, - FEAT_LINEBUFFERSPLIT, - FEAT_ROWREPEATENABLE, - FEAT_RESIZECONF, - /* Independent core clk divider */ - FEAT_CORE_CLK_DIV, - FEAT_LCD_CLK_SRC, - /* DSI-PLL power command 0x3 is not working */ - FEAT_DSI_PLL_PWR_BUG, - FEAT_DSI_DCS_CMD_CONFIG_VC, - FEAT_DSI_VC_OCP_WIDTH, - FEAT_DSI_REVERSE_TXCLKESC, - FEAT_DSI_GNQ, - FEAT_DPI_USES_VDDS_DSI, - FEAT_HDMI_CTS_SWMODE, - FEAT_HDMI_AUDIO_USE_MCLK, - FEAT_HANDLE_UV_SEPARATE, - FEAT_ATTR2, - FEAT_VENC_REQUIRES_TV_DAC_CLK, - FEAT_CPR, - FEAT_PRELOAD, - FEAT_FIR_COEF_V, - FEAT_ALPHA_FIXED_ZORDER, - FEAT_ALPHA_FREE_ZORDER, - FEAT_FIFO_MERGE, - /* An unknown HW bug causing the normal FIFO thresholds not to work */ - FEAT_OMAP3_DSI_FIFO_BUG, - FEAT_BURST_2D, - FEAT_DSI_PHY_DCC, - FEAT_MFLAG, -}; - -/* DSS register field id */ -enum dss_feat_reg_field { - FEAT_REG_FIRHINC, - FEAT_REG_FIRVINC, - FEAT_REG_FIFOHIGHTHRESHOLD, - FEAT_REG_FIFOLOWTHRESHOLD, - FEAT_REG_FIFOSIZE, - FEAT_REG_HORIZONTALACCU, - FEAT_REG_VERTICALACCU, - FEAT_REG_DISPC_CLK_SWITCH, -}; - -enum dss_range_param { - FEAT_PARAM_DSS_FCK, - FEAT_PARAM_DSS_PCD, - FEAT_PARAM_DSIPLL_LPDIV, - FEAT_PARAM_DSI_FCK, - FEAT_PARAM_DOWNSCALE, - FEAT_PARAM_LINEWIDTH, -}; - -/* DSS Feature Functions */ -unsigned long dss_feat_get_param_min(enum dss_range_param param); -unsigned long dss_feat_get_param_max(enum dss_range_param param); -enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane); -bool dss_feat_color_mode_supported(enum omap_plane_id plane, - enum omap_color_mode color_mode); - -u32 dss_feat_get_buffer_size_unit(void); /* in bytes */ -u32 dss_feat_get_burst_size_unit(void); /* in bytes */ - -bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type); - -bool dss_has_feature(enum dss_feat_id id); -void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); -void dss_features_init(enum omapdss_version version); - -enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); -enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); - -int dss_feat_get_num_mgrs(void); -int dss_feat_get_num_ovls(void); -enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane); - -#endif diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi.h b/drivers/gpu/drm/omapdrm/dss/hdmi.h index fb6cccd02374..a820b394af09 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi.h +++ b/drivers/gpu/drm/omapdrm/dss/hdmi.h @@ -234,6 +234,7 @@ struct hdmi_core_audio_config { struct hdmi_wp_data { void __iomem *base; phys_addr_t phys_base; + unsigned int version; }; struct hdmi_pll_data { @@ -245,15 +246,24 @@ struct hdmi_pll_data { struct hdmi_wp_data *wp; }; +struct hdmi_phy_features { + bool bist_ctrl; + bool ldo_voltage; + unsigned long max_phy; +}; + struct hdmi_phy_data { void __iomem *base; + const struct hdmi_phy_features *features; u8 lane_function[4]; u8 lane_polarity[4]; }; struct hdmi_core_data { void __iomem *base; + bool cts_swmode; + bool audio_use_mclk; }; static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, @@ -303,7 +313,8 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, struct videomode *vm); void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, struct videomode *vm, struct hdmi_config *param); -int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); +int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp, + unsigned int version); phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp); /* HDMI PLL funcs */ @@ -316,7 +327,8 @@ void hdmi_pll_uninit(struct hdmi_pll_data *hpll); int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk, unsigned long lfbitclk); void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); -int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); +int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy, + unsigned int version); int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes); /* HDMI common funcs */ diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c index 87c53034c634..f169348da377 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c @@ -40,7 +40,6 @@ #include "omapdss.h" #include "hdmi4_core.h" #include "dss.h" -#include "dss_features.h" #include "hdmi.h" static struct omap_hdmi hdmi; @@ -668,7 +667,7 @@ static int hdmi_audio_register(struct device *dev) { struct omap_hdmi_audio_pdata pdata = { .dev = dev, - .dss_version = omapdss_get_version(), + .version = 4, .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), .ops = &hdmi_audio_ops, }; @@ -696,13 +695,11 @@ static int hdmi4_bind(struct device *dev, struct device *master, void *data) mutex_init(&hdmi.lock); spin_lock_init(&hdmi.audio_playing_lock); - if (pdev->dev.of_node) { - r = hdmi_probe_of(pdev); - if (r) - return r; - } + r = hdmi_probe_of(pdev); + if (r) + return r; - r = hdmi_wp_init(pdev, &hdmi.wp); + r = hdmi_wp_init(pdev, &hdmi.wp, 4); if (r) return r; @@ -710,7 +707,7 @@ static int hdmi4_bind(struct device *dev, struct device *master, void *data) if (r) return r; - r = hdmi_phy_init(pdev, &hdmi.phy); + r = hdmi_phy_init(pdev, &hdmi.phy, 4); if (r) goto err; diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c index e05b7ac4f7dd..365cf07daa01 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c @@ -31,11 +31,11 @@ #include <linux/platform_device.h> #include <linux/string.h> #include <linux/seq_file.h> +#include <linux/sys_soc.h> #include <sound/asound.h> #include <sound/asoundef.h> #include "hdmi4_core.h" -#include "dss_features.h" #define HDMI_CORE_AV 0x500 @@ -757,10 +757,10 @@ int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, /* Audio clock regeneration settings */ acore.n = n; acore.cts = cts; - if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { + if (core->cts_swmode) { acore.aud_par_busclk = 0; acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; - acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); + acore.use_mclk = core->audio_use_mclk; } else { acore.aud_par_busclk = (((128 * 31) - 1) << 8); acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; @@ -884,21 +884,46 @@ void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) hdmi_wp_audio_core_req_enable(wp, false); } +struct hdmi4_features { + bool cts_swmode; + bool audio_use_mclk; +}; + +static const struct hdmi4_features hdmi4_es1_features = { + .cts_swmode = false, + .audio_use_mclk = false, +}; + +static const struct hdmi4_features hdmi4_es2_features = { + .cts_swmode = true, + .audio_use_mclk = false, +}; + +static const struct hdmi4_features hdmi4_es3_features = { + .cts_swmode = true, + .audio_use_mclk = true, +}; + +static const struct soc_device_attribute hdmi4_soc_devices[] = { + { .family = "OMAP4", .revision = "ES1.?", .data = &hdmi4_es1_features }, + { .family = "OMAP4", .revision = "ES2.?", .data = &hdmi4_es2_features }, + { .family = "OMAP4", .data = &hdmi4_es3_features }, + { /* sentinel */ } +}; + int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) { + const struct hdmi4_features *features; struct resource *res; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); - if (!res) { - DSSERR("can't get CORE mem resource\n"); - return -EINVAL; - } + features = soc_device_match(hdmi4_soc_devices)->data; + core->cts_swmode = features->cts_swmode; + core->audio_use_mclk = features->audio_use_mclk; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); core->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(core->base)) { - DSSERR("can't ioremap CORE\n"); + if (IS_ERR(core->base)) return PTR_ERR(core->base); - } return 0; } diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c index d13dce7e8079..b3221ca5bcd8 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c @@ -45,7 +45,6 @@ #include "omapdss.h" #include "hdmi5_core.h" #include "dss.h" -#include "dss_features.h" static struct omap_hdmi hdmi; @@ -695,7 +694,7 @@ static int hdmi_audio_register(struct device *dev) { struct omap_hdmi_audio_pdata pdata = { .dev = dev, - .dss_version = omapdss_get_version(), + .version = 5, .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), .ops = &hdmi_audio_ops, }; @@ -728,13 +727,11 @@ static int hdmi5_bind(struct device *dev, struct device *master, void *data) mutex_init(&hdmi.lock); spin_lock_init(&hdmi.audio_playing_lock); - if (pdev->dev.of_node) { - r = hdmi_probe_of(pdev); - if (r) - return r; - } + r = hdmi_probe_of(pdev); + if (r) + return r; - r = hdmi_wp_init(pdev, &hdmi.wp); + r = hdmi_wp_init(pdev, &hdmi.wp, 5); if (r) return r; @@ -742,7 +739,7 @@ static int hdmi5_bind(struct device *dev, struct device *master, void *data) if (r) return r; - r = hdmi_phy_init(pdev, &hdmi.phy); + r = hdmi_phy_init(pdev, &hdmi.phy, 5); if (r) goto err; diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c index 8de1d7b2ae55..ab179ec133c0 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c @@ -910,16 +910,9 @@ int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core) struct resource *res; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); - if (!res) { - DSSERR("can't get CORE IORESOURCE_MEM HDMI\n"); - return -EINVAL; - } - core->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(core->base)) { - DSSERR("can't ioremap HDMI core\n"); + if (IS_ERR(core->base)) return PTR_ERR(core->base); - } return 0; } diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c b/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c index 3ead47cccac5..a156292b1820 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c @@ -19,14 +19,6 @@ #include "dss.h" #include "hdmi.h" -struct hdmi_phy_features { - bool bist_ctrl; - bool ldo_voltage; - unsigned long max_phy; -}; - -static const struct hdmi_phy_features *phy_feat; - void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) { #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ @@ -36,7 +28,7 @@ void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL); DUMPPHY(HDMI_TXPHY_POWER_CTRL); DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL); - if (phy_feat->bist_ctrl) + if (phy->features->bist_ctrl) DUMPPHY(HDMI_TXPHY_BIST_CONTROL); } @@ -146,7 +138,7 @@ int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk, * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the * HDMI_PHYPWRCMD_LDOON command. */ - if (phy_feat->bist_ctrl) + if (phy->features->bist_ctrl) REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); /* @@ -155,7 +147,7 @@ int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk, */ if (hfbitclk != lfbitclk) freqout = 0; - else if (hfbitclk / 10 < phy_feat->max_phy) + else if (hfbitclk / 10 < phy->features->max_phy) freqout = 1; else freqout = 2; @@ -170,7 +162,7 @@ int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk, hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); /* Setup max LDO voltage */ - if (phy_feat->ldo_voltage) + if (phy->features->ldo_voltage) REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); hdmi_phy_configure_lanes(phy); @@ -190,59 +182,20 @@ static const struct hdmi_phy_features omap54xx_phy_feats = { .max_phy = 186000000, }; -static int hdmi_phy_init_features(struct platform_device *pdev) +int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy, + unsigned int version) { - struct hdmi_phy_features *dst; - const struct hdmi_phy_features *src; - - dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); - if (!dst) { - dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n"); - return -ENOMEM; - } - - switch (omapdss_get_version()) { - case OMAPDSS_VER_OMAP4430_ES1: - case OMAPDSS_VER_OMAP4430_ES2: - case OMAPDSS_VER_OMAP4: - src = &omap44xx_phy_feats; - break; - - case OMAPDSS_VER_OMAP5: - case OMAPDSS_VER_DRA7xx: - src = &omap54xx_phy_feats; - break; - - default: - return -ENODEV; - } - - memcpy(dst, src, sizeof(*dst)); - phy_feat = dst; - - return 0; -} - -int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy) -{ - int r; struct resource *res; - r = hdmi_phy_init_features(pdev); - if (r) - return r; + if (version == 4) + phy->features = &omap44xx_phy_feats; + else + phy->features = &omap54xx_phy_feats; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); - if (!res) { - DSSERR("can't get PHY mem resource\n"); - return -EINVAL; - } - phy->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(phy->base)) { - DSSERR("can't ioremap TX PHY\n"); + if (IS_ERR(phy->base)) return PTR_ERR(phy->base); - } return 0; } diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c b/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c index b8bf6a9e5557..55bee81f4dd5 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c @@ -71,7 +71,7 @@ static void hdmi_pll_disable(struct dss_pll *dsspll) WARN_ON(r < 0 && r != -ENOSYS); } -static const struct dss_pll_ops dsi_pll_ops = { +static const struct dss_pll_ops hdmi_pll_ops = { .enable = hdmi_pll_enable, .disable = hdmi_pll_disable, .set_config = dss_pll_write_config_type_b, @@ -128,7 +128,8 @@ static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = { .has_refsel = true, }; -static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll) +static int hdmi_init_pll_data(struct platform_device *pdev, + struct hdmi_pll_data *hpll) { struct dss_pll *pll = &hpll->pll; struct clk *clk; @@ -145,23 +146,12 @@ static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data pll->base = hpll->base; pll->clkin = clk; - switch (omapdss_get_version()) { - case OMAPDSS_VER_OMAP4430_ES1: - case OMAPDSS_VER_OMAP4430_ES2: - case OMAPDSS_VER_OMAP4: + if (hpll->wp->version == 4) pll->hw = &dss_omap4_hdmi_pll_hw; - break; - - case OMAPDSS_VER_OMAP5: - case OMAPDSS_VER_DRA7xx: + else pll->hw = &dss_omap5_hdmi_pll_hw; - break; - - default: - return -ENODEV; - } - pll->ops = &dsi_pll_ops; + pll->ops = &hdmi_pll_ops; r = dss_pll_register(pll); if (r) @@ -180,18 +170,11 @@ int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, pll->wp = wp; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll"); - if (!res) { - DSSERR("can't get PLL mem resource\n"); - return -EINVAL; - } - pll->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pll->base)) { - DSSERR("can't ioremap PLLCTRL\n"); + if (IS_ERR(pll->base)) return PTR_ERR(pll->base); - } - r = dsi_init_pll_data(pdev, pll); + r = hdmi_init_pll_data(pdev, pll); if (r) { DSSERR("failed to init HDMI PLL\n"); return r; diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c index 597ec9d87d1d..88034fbe0e9f 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c @@ -178,9 +178,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, * However, we don't support OMAP5 ES1 at all, so we can just check for * OMAP4 here. */ - if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || - omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || - omapdss_get_version() == OMAPDSS_VER_OMAP4) + if (wp->version == 4) hsync_len_offset = 0; timing_h |= FLD_VAL(vm->hback_porch, 31, 20); @@ -235,9 +233,7 @@ void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, DSSDBG("Enter hdmi_wp_audio_config_format\n"); r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); - if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || - omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || - omapdss_get_version() == OMAPDSS_VER_OMAP4) { + if (wp->version == 4) { r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); } @@ -282,22 +278,18 @@ int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable) return 0; } -int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp) +int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp, + unsigned int version) { struct resource *res; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp"); - if (!res) { - DSSERR("can't get WP mem resource\n"); - return -EINVAL; - } - wp->phys_base = res->start; - wp->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(wp->base)) { - DSSERR("can't ioremap HDMI WP\n"); + if (IS_ERR(wp->base)) return PTR_ERR(wp->base); - } + + wp->phys_base = res->start; + wp->version = version; return 0; } diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index b19dae1fd6c5..47a331670963 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -25,6 +25,7 @@ #include <video/videomode.h> #include <linux/platform_data/omapdss.h> #include <uapi/drm/drm_mode.h> +#include <drm/drm_crtc.h> #define DISPC_IRQ_FRAMEDONE (1 << 0) #define DISPC_IRQ_VSYNC (1 << 1) @@ -59,7 +60,6 @@ #define DISPC_IRQ_FRAMEDONE3 (1 << 30) struct omap_dss_device; -struct omap_overlay_manager; struct dss_lcd_mgr_config; struct snd_aes_iec958; struct snd_cea_861_aud_if; @@ -93,25 +93,7 @@ enum omap_channel { }; enum omap_color_mode { - OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ - OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ - OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ - OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ - OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ - OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ - OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ - OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ - OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ - OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ - OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ - OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ - OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ - OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ - OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ - OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ - OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ - OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ - OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ + _UNUSED_, }; enum omap_dss_load_mode { @@ -126,11 +108,6 @@ enum omap_dss_trans_key_type { OMAP_DSS_COLOR_KEY_VID_SRC = 1, }; -enum omap_rfbi_te_mode { - OMAP_DSS_RFBI_TE_MODE_1 = 1, - OMAP_DSS_RFBI_TE_MODE_2 = 2, -}; - enum omap_dss_signal_level { OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, @@ -169,17 +146,8 @@ enum omap_dss_display_state { }; enum omap_dss_rotation_type { - OMAP_DSS_ROT_DMA = 1 << 0, - OMAP_DSS_ROT_VRFB = 1 << 1, - OMAP_DSS_ROT_TILER = 1 << 2, -}; - -/* clockwise rotation angle */ -enum omap_dss_rotation_angle { - OMAP_DSS_ROT_0 = 0, - OMAP_DSS_ROT_90 = 1, - OMAP_DSS_ROT_180 = 2, - OMAP_DSS_ROT_270 = 3, + OMAP_DSS_ROT_NONE = 0, + OMAP_DSS_ROT_TILER = 1 << 0, }; enum omap_overlay_caps { @@ -191,10 +159,6 @@ enum omap_overlay_caps { OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, }; -enum omap_overlay_manager_caps { - OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ -}; - enum omap_dss_clk_source { OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK * OMAP4: DSS_FCLK */ @@ -220,27 +184,6 @@ enum omap_dss_output_id { OMAP_DSS_OUTPUT_HDMI = 1 << 6, }; -/* RFBI */ - -struct rfbi_timings { - int cs_on_time; - int cs_off_time; - int we_on_time; - int we_off_time; - int re_on_time; - int re_off_time; - int we_cycle_time; - int re_cycle_time; - int cs_pulse_width; - int access_time; - - int clk_div; - - u32 tim[5]; /* set by rfbi_convert_timings() */ - - int converted; -}; - /* DSI */ enum omap_dss_dsi_trans_mode { @@ -299,13 +242,6 @@ struct omap_dss_dsi_config { enum omap_dss_dsi_trans_mode trans_mode; }; -/* Hardcoded videomodes for tv. Venc only uses these to - * identify the mode, and does not actually use the configs - * itself. However, the configs should be something that - * a normal monitor can also show */ -extern const struct videomode omap_dss_pal_vm; -extern const struct videomode omap_dss_ntsc_vm; - struct omap_dss_cpr_coefs { s16 rr, rg, rb; s16 gr, gg, gb; @@ -318,10 +254,9 @@ struct omap_overlay_info { u16 screen_width; u16 width; u16 height; - enum omap_color_mode color_mode; + u32 fourcc; u8 rotation; enum omap_dss_rotation_type rotation_type; - bool mirror; u16 pos_x; u16 pos_y; @@ -332,48 +267,6 @@ struct omap_overlay_info { u8 zorder; }; -struct omap_overlay { - struct kobject kobj; - struct list_head list; - - /* static fields */ - const char *name; - enum omap_plane_id id; - enum omap_color_mode supported_modes; - enum omap_overlay_caps caps; - - /* dynamic fields */ - struct omap_overlay_manager *manager; - - /* - * The following functions do not block: - * - * is_enabled - * set_overlay_info - * get_overlay_info - * - * The rest of the functions may block and cannot be called from - * interrupt context - */ - - int (*enable)(struct omap_overlay *ovl); - int (*disable)(struct omap_overlay *ovl); - bool (*is_enabled)(struct omap_overlay *ovl); - - int (*set_manager)(struct omap_overlay *ovl, - struct omap_overlay_manager *mgr); - int (*unset_manager)(struct omap_overlay *ovl); - - int (*set_overlay_info)(struct omap_overlay *ovl, - struct omap_overlay_info *info); - void (*get_overlay_info)(struct omap_overlay *ovl, - struct omap_overlay_info *info); - - int (*wait_for_go)(struct omap_overlay *ovl); - - struct omap_dss_device *(*get_device)(struct omap_overlay *ovl); -}; - struct omap_overlay_manager_info { u32 default_color; @@ -387,47 +280,6 @@ struct omap_overlay_manager_info { struct omap_dss_cpr_coefs cpr_coefs; }; -struct omap_overlay_manager { - struct kobject kobj; - - /* static fields */ - const char *name; - enum omap_channel id; - enum omap_overlay_manager_caps caps; - struct list_head overlays; - enum omap_display_type supported_displays; - enum omap_dss_output_id supported_outputs; - - /* dynamic fields */ - struct omap_dss_device *output; - - /* - * The following functions do not block: - * - * set_manager_info - * get_manager_info - * apply - * - * The rest of the functions may block and cannot be called from - * interrupt context - */ - - int (*set_output)(struct omap_overlay_manager *mgr, - struct omap_dss_device *output); - int (*unset_output)(struct omap_overlay_manager *mgr); - - int (*set_manager_info)(struct omap_overlay_manager *mgr, - struct omap_overlay_manager_info *info); - void (*get_manager_info)(struct omap_overlay_manager *mgr, - struct omap_overlay_manager_info *info); - - int (*apply)(struct omap_overlay_manager *mgr); - int (*wait_for_go)(struct omap_overlay_manager *mgr); - int (*wait_for_vsync)(struct omap_overlay_manager *mgr); - - struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr); -}; - /* 22 pins means 1 clk lane and 10 data lanes */ #define OMAP_DSS_MAX_DSI_PINS 22 @@ -449,10 +301,9 @@ struct omap_dss_writeback_info { u16 buf_width; u16 width; u16 height; - enum omap_color_mode color_mode; + u32 fourcc; u8 rotation; enum omap_dss_rotation_type rotation_type; - bool mirror; u8 pre_mult_alpha; }; @@ -471,8 +322,6 @@ struct omapdss_dpi_ops { struct videomode *vm); void (*get_timings)(struct omap_dss_device *dssdev, struct videomode *vm); - - void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines); }; struct omapdss_sdi_ops { @@ -490,8 +339,6 @@ struct omapdss_sdi_ops { struct videomode *vm); void (*get_timings)(struct omap_dss_device *dssdev, struct videomode *vm); - - void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs); }; struct omapdss_dvi_ops { @@ -527,11 +374,6 @@ struct omapdss_atv_ops { void (*get_timings)(struct omap_dss_device *dssdev, struct videomode *vm); - void (*set_type)(struct omap_dss_device *dssdev, - enum omap_dss_venc_type type); - void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev, - bool invert_polarity); - int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); u32 (*get_wss)(struct omap_dss_device *dssdev); }; @@ -555,6 +397,14 @@ struct omapdss_hdmi_ops { int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); bool (*detect)(struct omap_dss_device *dssdev); + int (*register_hpd_cb)(struct omap_dss_device *dssdev, + void (*cb)(void *cb_data, + enum drm_connector_status status), + void *cb_data); + void (*unregister_hpd_cb)(struct omap_dss_device *dssdev); + void (*enable_hpd)(struct omap_dss_device *dssdev); + void (*disable_hpd)(struct omap_dss_device *dssdev); + int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); int (*set_infoframe)(struct omap_dss_device *dssdev, const struct hdmi_avi_infoframe *avi); @@ -631,30 +481,6 @@ struct omap_dss_device { enum omap_display_type type; enum omap_display_type output_type; - union { - struct { - u8 data_lines; - } dpi; - - struct { - u8 channel; - u8 data_lines; - } rfbi; - - struct { - u8 datapairs; - } sdi; - - struct { - int module; - } dsi; - - struct { - enum omap_dss_venc_type type; - bool invert_polarity; - } venc; - } phy; - struct { struct videomode vm; @@ -662,18 +488,8 @@ struct omap_dss_device { enum omap_dss_dsi_mode dsi_mode; } panel; - struct { - u8 pixel_size; - struct rfbi_timings rfbi_timings; - } ctrl; - const char *name; - /* used to match device to driver */ - const char *driver_name; - - void *data; - struct omap_dss_driver *driver; union { @@ -709,8 +525,6 @@ struct omap_dss_device { int port_num; /* dynamic fields */ - struct omap_overlay_manager *manager; - struct omap_dss_device *dst; }; @@ -742,12 +556,6 @@ struct omap_dss_driver { void *buf, size_t size, u16 x, u16 y, u16 w, u16 h); - void (*get_resolution)(struct omap_dss_device *dssdev, - u16 *xres, u16 *yres); - void (*get_dimensions)(struct omap_dss_device *dssdev, - u32 *width, u32 *height); - int (*get_recommended_bpp)(struct omap_dss_device *dssdev); - int (*check_timings)(struct omap_dss_device *dssdev, struct videomode *vm); void (*set_timings)(struct omap_dss_device *dssdev, @@ -761,12 +569,19 @@ struct omap_dss_driver { int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); bool (*detect)(struct omap_dss_device *dssdev); + int (*register_hpd_cb)(struct omap_dss_device *dssdev, + void (*cb)(void *cb_data, + enum drm_connector_status status), + void *cb_data); + void (*unregister_hpd_cb)(struct omap_dss_device *dssdev); + void (*enable_hpd)(struct omap_dss_device *dssdev); + void (*disable_hpd)(struct omap_dss_device *dssdev); + int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev, const struct hdmi_avi_infoframe *avi); }; -enum omapdss_version omapdss_get_version(void); bool omapdss_is_initialized(void); int omap_dss_register_driver(struct omap_dss_driver *); @@ -781,35 +596,22 @@ void omap_dss_put_device(struct omap_dss_device *dssdev); struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); struct omap_dss_device *omap_dss_find_device(void *data, int (*match)(struct omap_dss_device *dssdev, void *data)); -const char *omapdss_get_default_display_name(void); - -int dss_feat_get_num_mgrs(void); -int dss_feat_get_num_ovls(void); -enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane); - int omap_dss_get_num_overlay_managers(void); -struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); int omap_dss_get_num_overlays(void); -struct omap_overlay *omap_dss_get_overlay(int num); int omapdss_register_output(struct omap_dss_device *output); void omapdss_unregister_output(struct omap_dss_device *output); struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id); -struct omap_dss_device *omap_dss_find_output(const char *name); struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port); int omapdss_output_set_device(struct omap_dss_device *out, struct omap_dss_device *dssdev); int omapdss_output_unset_device(struct omap_dss_device *out); struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev); -struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev); -void omapdss_default_get_resolution(struct omap_dss_device *dssdev, - u16 *xres, u16 *yres); -int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); void omapdss_default_get_timings(struct omap_dss_device *dssdev, struct videomode *vm); @@ -881,7 +683,6 @@ void dss_mgr_unregister_framedone_handler(enum omap_channel channel, struct dispc_ops { u32 (*read_irqstatus)(void); void (*clear_irqstatus)(u32 mask); - u32 (*read_irqenable)(void); void (*write_irqenable)(u32 mask); int (*request_irq)(irq_handler_t handler, void *dev_id); @@ -913,14 +714,12 @@ struct dispc_ops { unsigned int length); int (*ovl_enable)(enum omap_plane_id plane, bool enable); - bool (*ovl_enabled)(enum omap_plane_id plane); - void (*ovl_set_channel_out)(enum omap_plane_id plane, - enum omap_channel channel); int (*ovl_setup)(enum omap_plane_id plane, const struct omap_overlay_info *oi, - const struct videomode *vm, bool mem_to_mem); + const struct videomode *vm, bool mem_to_mem, + enum omap_channel channel); - enum omap_color_mode (*ovl_get_color_modes)(enum omap_plane_id plane); + const u32 *(*ovl_get_color_modes)(enum omap_plane_id plane); }; void dispc_set_ops(const struct dispc_ops *o); diff --git a/drivers/gpu/drm/omapdrm/dss/output.c b/drivers/gpu/drm/omapdrm/dss/output.c index 655c5d73eac9..3c572b699ed3 100644 --- a/drivers/gpu/drm/omapdrm/dss/output.c +++ b/drivers/gpu/drm/omapdrm/dss/output.c @@ -133,19 +133,6 @@ struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id) } EXPORT_SYMBOL(omap_dss_get_output); -struct omap_dss_device *omap_dss_find_output(const char *name) -{ - struct omap_dss_device *out; - - list_for_each_entry(out, &output_list, list) { - if (strcmp(out->name, name) == 0) - return omap_dss_get_device(out); - } - - return NULL; -} -EXPORT_SYMBOL(omap_dss_find_output); - struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port) { struct device_node *src_node; diff --git a/drivers/gpu/drm/omapdrm/dss/pll.c b/drivers/gpu/drm/omapdrm/dss/pll.c index 5e221302768b..9d9d9d42009b 100644 --- a/drivers/gpu/drm/omapdrm/dss/pll.c +++ b/drivers/gpu/drm/omapdrm/dss/pll.c @@ -215,8 +215,8 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, dss_pll_calc_func func, void *data) { const struct dss_pll_hw *hw = pll->hw; - int n, n_min, n_max; - int m, m_min, m_max; + int n, n_start, n_stop, n_inc; + int m, m_start, m_stop, m_inc; unsigned long fint, clkdco; unsigned long pll_hw_max; unsigned long fint_hw_min, fint_hw_max; @@ -226,22 +226,33 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, fint_hw_min = hw->fint_min; fint_hw_max = hw->fint_max; - n_min = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); - n_max = min((unsigned)(clkin / fint_hw_min), hw->n_max); + n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); + n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max); + n_inc = 1; + + if (hw->errata_i886) { + swap(n_start, n_stop); + n_inc = -1; + } pll_max = pll_max ? pll_max : ULONG_MAX; - /* Try to find high N & M to avoid jitter (DRA7 errata i886) */ - for (n = n_max; n >= n_min; --n) { + for (n = n_start; n != n_stop; n += n_inc) { fint = clkin / n; - m_min = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), + m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), 1ul); - m_max = min3((unsigned)(pll_max / fint / 2), + m_stop = min3((unsigned)(pll_max / fint / 2), (unsigned)(pll_hw_max / fint / 2), hw->m_max); + m_inc = 1; + + if (hw->errata_i886) { + swap(m_start, m_stop); + m_inc = -1; + } - for (m = m_max; m >= m_min; --m) { + for (m = m_start; m != m_stop; m += m_inc) { clkdco = 2 * m * fint; if (func(n, m, fint, clkdco, data)) diff --git a/drivers/gpu/drm/omapdrm/dss/rfbi.c b/drivers/gpu/drm/omapdrm/dss/rfbi.c deleted file mode 100644 index 09724757366a..000000000000 --- a/drivers/gpu/drm/omapdrm/dss/rfbi.c +++ /dev/null @@ -1,1083 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/rfbi.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "RFBI" - -#include <linux/kernel.h> -#include <linux/dma-mapping.h> -#include <linux/export.h> -#include <linux/vmalloc.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/kfifo.h> -#include <linux/ktime.h> -#include <linux/hrtimer.h> -#include <linux/seq_file.h> -#include <linux/semaphore.h> -#include <linux/platform_device.h> -#include <linux/pm_runtime.h> -#include <linux/component.h> - -#include "omapdss.h" -#include "dss.h" - -struct rfbi_reg { u16 idx; }; - -#define RFBI_REG(idx) ((const struct rfbi_reg) { idx }) - -#define RFBI_REVISION RFBI_REG(0x0000) -#define RFBI_SYSCONFIG RFBI_REG(0x0010) -#define RFBI_SYSSTATUS RFBI_REG(0x0014) -#define RFBI_CONTROL RFBI_REG(0x0040) -#define RFBI_PIXEL_CNT RFBI_REG(0x0044) -#define RFBI_LINE_NUMBER RFBI_REG(0x0048) -#define RFBI_CMD RFBI_REG(0x004c) -#define RFBI_PARAM RFBI_REG(0x0050) -#define RFBI_DATA RFBI_REG(0x0054) -#define RFBI_READ RFBI_REG(0x0058) -#define RFBI_STATUS RFBI_REG(0x005c) - -#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18) -#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18) -#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18) -#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18) -#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18) -#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18) - -#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090) -#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094) - -#define REG_FLD_MOD(idx, val, start, end) \ - rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end)) - -enum omap_rfbi_cycleformat { - OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0, - OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1, - OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2, - OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3, -}; - -enum omap_rfbi_datatype { - OMAP_DSS_RFBI_DATATYPE_12 = 0, - OMAP_DSS_RFBI_DATATYPE_16 = 1, - OMAP_DSS_RFBI_DATATYPE_18 = 2, - OMAP_DSS_RFBI_DATATYPE_24 = 3, -}; - -enum omap_rfbi_parallelmode { - OMAP_DSS_RFBI_PARALLELMODE_8 = 0, - OMAP_DSS_RFBI_PARALLELMODE_9 = 1, - OMAP_DSS_RFBI_PARALLELMODE_12 = 2, - OMAP_DSS_RFBI_PARALLELMODE_16 = 3, -}; - -static int rfbi_convert_timings(struct rfbi_timings *t); -static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div); - -static struct { - struct platform_device *pdev; - void __iomem *base; - - unsigned long l4_khz; - - enum omap_rfbi_datatype datatype; - enum omap_rfbi_parallelmode parallelmode; - - enum omap_rfbi_te_mode te_mode; - int te_enabled; - - void (*framedone_callback)(void *data); - void *framedone_callback_data; - - struct omap_dss_device *dssdev[2]; - - struct semaphore bus_lock; - - struct videomode vm; - int pixel_size; - int data_lines; - struct rfbi_timings intf_timings; - - struct omap_dss_device output; -} rfbi; - -static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val) -{ - __raw_writel(val, rfbi.base + idx.idx); -} - -static inline u32 rfbi_read_reg(const struct rfbi_reg idx) -{ - return __raw_readl(rfbi.base + idx.idx); -} - -static int rfbi_runtime_get(void) -{ - int r; - - DSSDBG("rfbi_runtime_get\n"); - - r = pm_runtime_get_sync(&rfbi.pdev->dev); - WARN_ON(r < 0); - return r < 0 ? r : 0; -} - -static void rfbi_runtime_put(void) -{ - int r; - - DSSDBG("rfbi_runtime_put\n"); - - r = pm_runtime_put_sync(&rfbi.pdev->dev); - WARN_ON(r < 0 && r != -ENOSYS); -} - -static void rfbi_bus_lock(void) -{ - down(&rfbi.bus_lock); -} - -static void rfbi_bus_unlock(void) -{ - up(&rfbi.bus_lock); -} - -static void rfbi_write_command(const void *buf, u32 len) -{ - switch (rfbi.parallelmode) { - case OMAP_DSS_RFBI_PARALLELMODE_8: - { - const u8 *b = buf; - for (; len; len--) - rfbi_write_reg(RFBI_CMD, *b++); - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_16: - { - const u16 *w = buf; - BUG_ON(len & 1); - for (; len; len -= 2) - rfbi_write_reg(RFBI_CMD, *w++); - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_9: - case OMAP_DSS_RFBI_PARALLELMODE_12: - default: - BUG(); - } -} - -static void rfbi_read_data(void *buf, u32 len) -{ - switch (rfbi.parallelmode) { - case OMAP_DSS_RFBI_PARALLELMODE_8: - { - u8 *b = buf; - for (; len; len--) { - rfbi_write_reg(RFBI_READ, 0); - *b++ = rfbi_read_reg(RFBI_READ); - } - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_16: - { - u16 *w = buf; - BUG_ON(len & ~1); - for (; len; len -= 2) { - rfbi_write_reg(RFBI_READ, 0); - *w++ = rfbi_read_reg(RFBI_READ); - } - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_9: - case OMAP_DSS_RFBI_PARALLELMODE_12: - default: - BUG(); - } -} - -static void rfbi_write_data(const void *buf, u32 len) -{ - switch (rfbi.parallelmode) { - case OMAP_DSS_RFBI_PARALLELMODE_8: - { - const u8 *b = buf; - for (; len; len--) - rfbi_write_reg(RFBI_PARAM, *b++); - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_16: - { - const u16 *w = buf; - BUG_ON(len & 1); - for (; len; len -= 2) - rfbi_write_reg(RFBI_PARAM, *w++); - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_9: - case OMAP_DSS_RFBI_PARALLELMODE_12: - default: - BUG(); - - } -} - -static void rfbi_write_pixels(const void __iomem *buf, int scr_width, - u16 x, u16 y, - u16 w, u16 h) -{ - int start_offset = scr_width * y + x; - int horiz_offset = scr_width - w; - int i; - - if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && - rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { - const u16 __iomem *pd = buf; - pd += start_offset; - - for (; h; --h) { - for (i = 0; i < w; ++i) { - const u8 __iomem *b = (const u8 __iomem *)pd; - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); - ++pd; - } - pd += horiz_offset; - } - } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 && - rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { - const u32 __iomem *pd = buf; - pd += start_offset; - - for (; h; --h) { - for (i = 0; i < w; ++i) { - const u8 __iomem *b = (const u8 __iomem *)pd; - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2)); - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); - ++pd; - } - pd += horiz_offset; - } - } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && - rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) { - const u16 __iomem *pd = buf; - pd += start_offset; - - for (; h; --h) { - for (i = 0; i < w; ++i) { - rfbi_write_reg(RFBI_PARAM, __raw_readw(pd)); - ++pd; - } - pd += horiz_offset; - } - } else { - BUG(); - } -} - -static int rfbi_transfer_area(struct omap_dss_device *dssdev, - void (*callback)(void *data), void *data) -{ - u32 l; - int r; - struct omap_overlay_manager *mgr = rfbi.output.manager; - u16 width = rfbi.vm.hactive; - u16 height = rfbi.vm.vactive; - - /*BUG_ON(callback == 0);*/ - BUG_ON(rfbi.framedone_callback != NULL); - - DSSDBG("rfbi_transfer_area %dx%d\n", width, height); - - dss_mgr_set_timings(mgr, &rfbi.vm); - - r = dss_mgr_enable(mgr); - if (r) - return r; - - rfbi.framedone_callback = callback; - rfbi.framedone_callback_data = data; - - rfbi_write_reg(RFBI_PIXEL_CNT, width * height); - - l = rfbi_read_reg(RFBI_CONTROL); - l = FLD_MOD(l, 1, 0, 0); /* enable */ - if (!rfbi.te_enabled) - l = FLD_MOD(l, 1, 4, 4); /* ITE */ - - rfbi_write_reg(RFBI_CONTROL, l); - - return 0; -} - -static void framedone_callback(void *data) -{ - void (*callback)(void *data); - - DSSDBG("FRAMEDONE\n"); - - REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); - - callback = rfbi.framedone_callback; - rfbi.framedone_callback = NULL; - - if (callback != NULL) - callback(rfbi.framedone_callback_data); -} - -#if 1 /* VERBOSE */ -static void rfbi_print_timings(void) -{ - u32 l; - u32 time; - - l = rfbi_read_reg(RFBI_CONFIG(0)); - time = 1000000000 / rfbi.l4_khz; - if (l & (1 << 4)) - time *= 2; - - DSSDBG("Tick time %u ps\n", time); - l = rfbi_read_reg(RFBI_ONOFF_TIME(0)); - DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, " - "REONTIME %d, REOFFTIME %d\n", - l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f, - (l >> 20) & 0x0f, (l >> 24) & 0x3f); - - l = rfbi_read_reg(RFBI_CYCLE_TIME(0)); - DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, " - "ACCESSTIME %d\n", - (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f, - (l >> 22) & 0x3f); -} -#else -static void rfbi_print_timings(void) {} -#endif - - - - -static u32 extif_clk_period; - -static inline unsigned long round_to_extif_ticks(unsigned long ps, int div) -{ - int bus_tick = extif_clk_period * div; - return (ps + bus_tick - 1) / bus_tick * bus_tick; -} - -static int calc_reg_timing(struct rfbi_timings *t, int div) -{ - t->clk_div = div; - - t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div); - - t->we_on_time = round_to_extif_ticks(t->we_on_time, div); - t->we_off_time = round_to_extif_ticks(t->we_off_time, div); - t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div); - - t->re_on_time = round_to_extif_ticks(t->re_on_time, div); - t->re_off_time = round_to_extif_ticks(t->re_off_time, div); - t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div); - - t->access_time = round_to_extif_ticks(t->access_time, div); - t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div); - t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div); - - DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n", - t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time); - DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n", - t->we_on_time, t->we_off_time, t->re_cycle_time, - t->we_cycle_time); - DSSDBG("[reg]rdaccess %d cspulse %d\n", - t->access_time, t->cs_pulse_width); - - return rfbi_convert_timings(t); -} - -static int calc_extif_timings(struct rfbi_timings *t) -{ - u32 max_clk_div; - int div; - - rfbi_get_clk_info(&extif_clk_period, &max_clk_div); - for (div = 1; div <= max_clk_div; div++) { - if (calc_reg_timing(t, div) == 0) - break; - } - - if (div <= max_clk_div) - return 0; - - DSSERR("can't setup timings\n"); - return -1; -} - - -static void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t) -{ - int r; - - if (!t->converted) { - r = calc_extif_timings(t); - if (r < 0) - DSSERR("Failed to calc timings\n"); - } - - BUG_ON(!t->converted); - - rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]); - rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]); - - /* TIMEGRANULARITY */ - REG_FLD_MOD(RFBI_CONFIG(rfbi_module), - (t->tim[2] ? 1 : 0), 4, 4); - - rfbi_print_timings(); -} - -static int ps_to_rfbi_ticks(int time, int div) -{ - unsigned long tick_ps; - int ret; - - /* Calculate in picosecs to yield more exact results */ - tick_ps = 1000000000 / (rfbi.l4_khz) * div; - - ret = (time + tick_ps - 1) / tick_ps; - - return ret; -} - -static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div) -{ - *clk_period = 1000000000 / rfbi.l4_khz; - *max_clk_div = 2; -} - -static int rfbi_convert_timings(struct rfbi_timings *t) -{ - u32 l; - int reon, reoff, weon, weoff, cson, csoff, cs_pulse; - int actim, recyc, wecyc; - int div = t->clk_div; - - if (div <= 0 || div > 2) - return -1; - - /* Make sure that after conversion it still holds that: - * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff, - * csoff > cson, csoff >= max(weoff, reoff), actim > reon - */ - weon = ps_to_rfbi_ticks(t->we_on_time, div); - weoff = ps_to_rfbi_ticks(t->we_off_time, div); - if (weoff <= weon) - weoff = weon + 1; - if (weon > 0x0f) - return -1; - if (weoff > 0x3f) - return -1; - - reon = ps_to_rfbi_ticks(t->re_on_time, div); - reoff = ps_to_rfbi_ticks(t->re_off_time, div); - if (reoff <= reon) - reoff = reon + 1; - if (reon > 0x0f) - return -1; - if (reoff > 0x3f) - return -1; - - cson = ps_to_rfbi_ticks(t->cs_on_time, div); - csoff = ps_to_rfbi_ticks(t->cs_off_time, div); - if (csoff <= cson) - csoff = cson + 1; - if (csoff < max(weoff, reoff)) - csoff = max(weoff, reoff); - if (cson > 0x0f) - return -1; - if (csoff > 0x3f) - return -1; - - l = cson; - l |= csoff << 4; - l |= weon << 10; - l |= weoff << 14; - l |= reon << 20; - l |= reoff << 24; - - t->tim[0] = l; - - actim = ps_to_rfbi_ticks(t->access_time, div); - if (actim <= reon) - actim = reon + 1; - if (actim > 0x3f) - return -1; - - wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div); - if (wecyc < weoff) - wecyc = weoff; - if (wecyc > 0x3f) - return -1; - - recyc = ps_to_rfbi_ticks(t->re_cycle_time, div); - if (recyc < reoff) - recyc = reoff; - if (recyc > 0x3f) - return -1; - - cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div); - if (cs_pulse > 0x3f) - return -1; - - l = wecyc; - l |= recyc << 6; - l |= cs_pulse << 12; - l |= actim << 22; - - t->tim[1] = l; - - t->tim[2] = div - 1; - - t->converted = 1; - - return 0; -} - -/* xxx FIX module selection missing */ -static int rfbi_setup_te(enum omap_rfbi_te_mode mode, - unsigned hs_pulse_time, unsigned vs_pulse_time, - int hs_pol_inv, int vs_pol_inv, int extif_div) -{ - int hs, vs; - int min; - u32 l; - - hs = ps_to_rfbi_ticks(hs_pulse_time, 1); - vs = ps_to_rfbi_ticks(vs_pulse_time, 1); - if (hs < 2) - return -EDOM; - if (mode == OMAP_DSS_RFBI_TE_MODE_2) - min = 2; - else /* OMAP_DSS_RFBI_TE_MODE_1 */ - min = 4; - if (vs < min) - return -EDOM; - if (vs == hs) - return -EINVAL; - rfbi.te_mode = mode; - DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n", - mode, hs, vs, hs_pol_inv, vs_pol_inv); - - rfbi_write_reg(RFBI_HSYNC_WIDTH, hs); - rfbi_write_reg(RFBI_VSYNC_WIDTH, vs); - - l = rfbi_read_reg(RFBI_CONFIG(0)); - if (hs_pol_inv) - l &= ~(1 << 21); - else - l |= 1 << 21; - if (vs_pol_inv) - l &= ~(1 << 20); - else - l |= 1 << 20; - - return 0; -} - -/* xxx FIX module selection missing */ -static int rfbi_enable_te(bool enable, unsigned line) -{ - u32 l; - - DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode); - if (line > (1 << 11) - 1) - return -EINVAL; - - l = rfbi_read_reg(RFBI_CONFIG(0)); - l &= ~(0x3 << 2); - if (enable) { - rfbi.te_enabled = 1; - l |= rfbi.te_mode << 2; - } else - rfbi.te_enabled = 0; - rfbi_write_reg(RFBI_CONFIG(0), l); - rfbi_write_reg(RFBI_LINE_NUMBER, line); - - return 0; -} - -static int rfbi_configure_bus(int rfbi_module, int bpp, int lines) -{ - u32 l; - int cycle1 = 0, cycle2 = 0, cycle3 = 0; - enum omap_rfbi_cycleformat cycleformat; - enum omap_rfbi_datatype datatype; - enum omap_rfbi_parallelmode parallelmode; - - switch (bpp) { - case 12: - datatype = OMAP_DSS_RFBI_DATATYPE_12; - break; - case 16: - datatype = OMAP_DSS_RFBI_DATATYPE_16; - break; - case 18: - datatype = OMAP_DSS_RFBI_DATATYPE_18; - break; - case 24: - datatype = OMAP_DSS_RFBI_DATATYPE_24; - break; - default: - BUG(); - return 1; - } - rfbi.datatype = datatype; - - switch (lines) { - case 8: - parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8; - break; - case 9: - parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9; - break; - case 12: - parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12; - break; - case 16: - parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16; - break; - default: - BUG(); - return 1; - } - rfbi.parallelmode = parallelmode; - - if ((bpp % lines) == 0) { - switch (bpp / lines) { - case 1: - cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1; - break; - case 2: - cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1; - break; - case 3: - cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1; - break; - default: - BUG(); - return 1; - } - } else if ((2 * bpp % lines) == 0) { - if ((2 * bpp / lines) == 3) - cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2; - else { - BUG(); - return 1; - } - } else { - BUG(); - return 1; - } - - switch (cycleformat) { - case OMAP_DSS_RFBI_CYCLEFORMAT_1_1: - cycle1 = lines; - break; - - case OMAP_DSS_RFBI_CYCLEFORMAT_2_1: - cycle1 = lines; - cycle2 = lines; - break; - - case OMAP_DSS_RFBI_CYCLEFORMAT_3_1: - cycle1 = lines; - cycle2 = lines; - cycle3 = lines; - break; - - case OMAP_DSS_RFBI_CYCLEFORMAT_3_2: - cycle1 = lines; - cycle2 = (lines / 2) | ((lines / 2) << 16); - cycle3 = (lines << 16); - break; - } - - REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */ - - l = 0; - l |= FLD_VAL(parallelmode, 1, 0); - l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */ - l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */ - l |= FLD_VAL(datatype, 6, 5); - /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ - l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */ - l |= FLD_VAL(cycleformat, 10, 9); - l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */ - l |= FLD_VAL(0, 16, 16); /* A0POLARITY */ - l |= FLD_VAL(0, 17, 17); /* REPOLARITY */ - l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */ - l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */ - l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */ - l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */ - rfbi_write_reg(RFBI_CONFIG(rfbi_module), l); - - rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1); - rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2); - rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3); - - - l = rfbi_read_reg(RFBI_CONTROL); - l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ - l = FLD_MOD(l, 0, 1, 1); /* clear bypass */ - rfbi_write_reg(RFBI_CONTROL, l); - - - DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n", - bpp, lines, cycle1, cycle2, cycle3); - - return 0; -} - -static int rfbi_configure(struct omap_dss_device *dssdev) -{ - return rfbi_configure_bus(dssdev->phy.rfbi.channel, rfbi.pixel_size, - rfbi.data_lines); -} - -static int rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *), - void *data) -{ - return rfbi_transfer_area(dssdev, callback, data); -} - -static void rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h) -{ - rfbi.vm.hactive = w; - rfbi.vm.vactive = h; -} - -static void rfbi_set_pixel_size(struct omap_dss_device *dssdev, int pixel_size) -{ - rfbi.pixel_size = pixel_size; -} - -static void rfbi_set_data_lines(struct omap_dss_device *dssdev, int data_lines) -{ - rfbi.data_lines = data_lines; -} - -static void rfbi_set_interface_timings(struct omap_dss_device *dssdev, - struct rfbi_timings *timings) -{ - rfbi.intf_timings = *timings; -} - -static void rfbi_dump_regs(struct seq_file *s) -{ -#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) - - if (rfbi_runtime_get()) - return; - - DUMPREG(RFBI_REVISION); - DUMPREG(RFBI_SYSCONFIG); - DUMPREG(RFBI_SYSSTATUS); - DUMPREG(RFBI_CONTROL); - DUMPREG(RFBI_PIXEL_CNT); - DUMPREG(RFBI_LINE_NUMBER); - DUMPREG(RFBI_CMD); - DUMPREG(RFBI_PARAM); - DUMPREG(RFBI_DATA); - DUMPREG(RFBI_READ); - DUMPREG(RFBI_STATUS); - - DUMPREG(RFBI_CONFIG(0)); - DUMPREG(RFBI_ONOFF_TIME(0)); - DUMPREG(RFBI_CYCLE_TIME(0)); - DUMPREG(RFBI_DATA_CYCLE1(0)); - DUMPREG(RFBI_DATA_CYCLE2(0)); - DUMPREG(RFBI_DATA_CYCLE3(0)); - - DUMPREG(RFBI_CONFIG(1)); - DUMPREG(RFBI_ONOFF_TIME(1)); - DUMPREG(RFBI_CYCLE_TIME(1)); - DUMPREG(RFBI_DATA_CYCLE1(1)); - DUMPREG(RFBI_DATA_CYCLE2(1)); - DUMPREG(RFBI_DATA_CYCLE3(1)); - - DUMPREG(RFBI_VSYNC_WIDTH); - DUMPREG(RFBI_HSYNC_WIDTH); - - rfbi_runtime_put(); -#undef DUMPREG -} - -static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev) -{ - struct omap_overlay_manager *mgr = rfbi.output.manager; - struct dss_lcd_mgr_config mgr_config; - - mgr_config.io_pad_mode = DSS_IO_PAD_MODE_RFBI; - - mgr_config.stallmode = true; - /* Do we need fifohandcheck for RFBI? */ - mgr_config.fifohandcheck = false; - - mgr_config.video_port_width = rfbi.pixel_size; - mgr_config.lcden_sig_polarity = 0; - - dss_mgr_set_lcd_config(mgr, &mgr_config); - - /* - * Set rfbi.timings with default values, the hactive and vactive fields - * are expected to be already configured by the panel driver via - * omapdss_rfbi_set_size() - */ - rfbi.vm.hsync_len = 1; - rfbi.vm.hfront_porch = 1; - rfbi.vm.hback_porch = 1; - rfbi.vm.vsync_len = 1; - rfbi.vm.vfront_porch = 0; - rfbi.vm.vback_porch = 0; - - rfbi.vm.flags &= ~DISPLAY_FLAGS_INTERLACED; - rfbi.vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; - rfbi.vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; - rfbi.vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; - rfbi.vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; - rfbi.vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; - rfbi.vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; - rfbi.vm.flags &= ~DISPLAY_FLAGS_DE_LOW; - rfbi.vm.flags |= DISPLAY_FLAGS_DE_HIGH; - rfbi.vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; - rfbi.vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; - - dss_mgr_set_timings(mgr, &rfbi.vm); -} - -static int rfbi_display_enable(struct omap_dss_device *dssdev) -{ - struct omap_dss_device *out = &rfbi.output; - int r; - - if (!out->dispc_channel_connected) { - DSSERR("failed to enable display: no output/manager\n"); - return -ENODEV; - } - - r = rfbi_runtime_get(); - if (r) - return r; - - r = dss_mgr_register_framedone_handler(out->manager, - framedone_callback, NULL); - if (r) { - DSSERR("can't get FRAMEDONE irq\n"); - goto err1; - } - - rfbi_config_lcd_manager(dssdev); - - rfbi_configure_bus(dssdev->phy.rfbi.channel, rfbi.pixel_size, - rfbi.data_lines); - - rfbi_set_timings(dssdev->phy.rfbi.channel, &rfbi.intf_timings); - - return 0; -err1: - rfbi_runtime_put(); - return r; -} - -static void rfbi_display_disable(struct omap_dss_device *dssdev) -{ - struct omap_dss_device *out = &rfbi.output; - - dss_mgr_unregister_framedone_handler(out->manager, - framedone_callback, NULL); - - rfbi_runtime_put(); -} - -static int rfbi_init_display(struct omap_dss_device *dssdev) -{ - rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev; - return 0; -} - -static void rfbi_init_output(struct platform_device *pdev) -{ - struct omap_dss_device *out = &rfbi.output; - - out->dev = &pdev->dev; - out->id = OMAP_DSS_OUTPUT_DBI; - out->output_type = OMAP_DISPLAY_TYPE_DBI; - out->name = "rfbi.0"; - out->dispc_channel = OMAP_DSS_CHANNEL_LCD; - out->owner = THIS_MODULE; - - omapdss_register_output(out); -} - -static void rfbi_uninit_output(struct platform_device *pdev) -{ - struct omap_dss_device *out = &rfbi.output; - - omapdss_unregister_output(out); -} - -/* RFBI HW IP initialisation */ -static int rfbi_bind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - u32 rev; - struct resource *rfbi_mem; - struct clk *clk; - int r; - - rfbi.pdev = pdev; - - sema_init(&rfbi.bus_lock, 1); - - rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0); - if (!rfbi_mem) { - DSSERR("can't get IORESOURCE_MEM RFBI\n"); - return -EINVAL; - } - - rfbi.base = devm_ioremap(&pdev->dev, rfbi_mem->start, - resource_size(rfbi_mem)); - if (!rfbi.base) { - DSSERR("can't ioremap RFBI\n"); - return -ENOMEM; - } - - clk = clk_get(&pdev->dev, "ick"); - if (IS_ERR(clk)) { - DSSERR("can't get ick\n"); - return PTR_ERR(clk); - } - - rfbi.l4_khz = clk_get_rate(clk) / 1000; - - clk_put(clk); - - pm_runtime_enable(&pdev->dev); - - r = rfbi_runtime_get(); - if (r) - goto err_runtime_get; - - msleep(10); - - rev = rfbi_read_reg(RFBI_REVISION); - dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n", - FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); - - rfbi_runtime_put(); - - dss_debugfs_create_file("rfbi", rfbi_dump_regs); - - rfbi_init_output(pdev); - - return 0; - -err_runtime_get: - pm_runtime_disable(&pdev->dev); - return r; -} - -static void rfbi_unbind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - - rfbi_uninit_output(pdev); - - pm_runtime_disable(&pdev->dev); - - return 0; -} - -static const struct component_ops rfbi_component_ops = { - .bind = rfbi_bind, - .unbind = rfbi_unbind, -}; - -static int rfbi_probe(struct platform_device *pdev) -{ - return component_add(&pdev->dev, &rfbi_component_ops); -} - -static int rfbi_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &rfbi_component_ops); - return 0; -} - -static int rfbi_runtime_suspend(struct device *dev) -{ - dispc_runtime_put(); - - return 0; -} - -static int rfbi_runtime_resume(struct device *dev) -{ - int r; - - r = dispc_runtime_get(); - if (r < 0) - return r; - - return 0; -} - -static const struct dev_pm_ops rfbi_pm_ops = { - .runtime_suspend = rfbi_runtime_suspend, - .runtime_resume = rfbi_runtime_resume, -}; - -static struct platform_driver omap_rfbihw_driver = { - .probe = rfbi_probe, - .remove = rfbi_remove, - .driver = { - .name = "omapdss_rfbi", - .pm = &rfbi_pm_ops, - .suppress_bind_attrs = true, - }, -}; - -int __init rfbi_init_platform_driver(void) -{ - return platform_driver_register(&omap_rfbihw_driver); -} - -void rfbi_uninit_platform_driver(void) -{ - platform_driver_unregister(&omap_rfbihw_driver); -} diff --git a/drivers/gpu/drm/omapdrm/dss/sdi.c b/drivers/gpu/drm/omapdrm/dss/sdi.c index 0620b9f8c231..d18ad58c5a19 100644 --- a/drivers/gpu/drm/omapdrm/dss/sdi.c +++ b/drivers/gpu/drm/omapdrm/dss/sdi.c @@ -27,7 +27,6 @@ #include <linux/platform_device.h> #include <linux/string.h> #include <linux/of.h> -#include <linux/component.h> #include "omapdss.h" #include "dss.h" @@ -253,11 +252,6 @@ static int sdi_check_timings(struct omap_dss_device *dssdev, return 0; } -static void sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs) -{ - sdi.datapairs = datapairs; -} - static int sdi_init_regulator(void) { struct regulator *vdds_sdi; @@ -327,8 +321,6 @@ static const struct omapdss_sdi_ops sdi_ops = { .check_timings = sdi_check_timings, .set_timings = sdi_set_timings, .get_timings = sdi_get_timings, - - .set_datapairs = sdi_set_datapairs, }; static void sdi_init_output(struct platform_device *pdev) @@ -355,59 +347,6 @@ static void sdi_uninit_output(struct platform_device *pdev) omapdss_unregister_output(out); } -static int sdi_bind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - - sdi.pdev = pdev; - - sdi_init_output(pdev); - - return 0; -} - -static void sdi_unbind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - - sdi_uninit_output(pdev); -} - -static const struct component_ops sdi_component_ops = { - .bind = sdi_bind, - .unbind = sdi_unbind, -}; - -static int sdi_probe(struct platform_device *pdev) -{ - return component_add(&pdev->dev, &sdi_component_ops); -} - -static int sdi_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &sdi_component_ops); - return 0; -} - -static struct platform_driver omap_sdi_driver = { - .probe = sdi_probe, - .remove = sdi_remove, - .driver = { - .name = "omapdss_sdi", - .suppress_bind_attrs = true, - }, -}; - -int __init sdi_init_platform_driver(void) -{ - return platform_driver_register(&omap_sdi_driver); -} - -void sdi_uninit_platform_driver(void) -{ - platform_driver_unregister(&omap_sdi_driver); -} - int sdi_init_port(struct platform_device *pdev, struct device_node *port) { struct device_node *ep; diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c index 19d14957f566..d58da6f32693 100644 --- a/drivers/gpu/drm/omapdrm/dss/venc.c +++ b/drivers/gpu/drm/omapdrm/dss/venc.c @@ -37,10 +37,10 @@ #include <linux/of.h> #include <linux/of_graph.h> #include <linux/component.h> +#include <linux/sys_soc.h> #include "omapdss.h" #include "dss.h" -#include "dss_features.h" /* Venc registers */ #define VENC_REV_ID 0x00 @@ -263,7 +263,13 @@ static const struct venc_config venc_config_pal_bdghi = { .fid_ext_start_y__fid_ext_offset_y = 0x01380005, }; -const struct videomode omap_dss_pal_vm = { +enum venc_videomode { + VENC_MODE_UNKNOWN, + VENC_MODE_PAL, + VENC_MODE_NTSC, +}; + +static const struct videomode omap_dss_pal_vm = { .hactive = 720, .vactive = 574, .pixelclock = 13500000, @@ -279,9 +285,8 @@ const struct videomode omap_dss_pal_vm = { DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_NEGEDGE, }; -EXPORT_SYMBOL(omap_dss_pal_vm); -const struct videomode omap_dss_ntsc_vm = { +static const struct videomode omap_dss_ntsc_vm = { .hactive = 720, .vactive = 482, .pixelclock = 13500000, @@ -297,7 +302,24 @@ const struct videomode omap_dss_ntsc_vm = { DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_NEGEDGE, }; -EXPORT_SYMBOL(omap_dss_ntsc_vm); + +static enum venc_videomode venc_get_videomode(const struct videomode *vm) +{ + if (!(vm->flags & DISPLAY_FLAGS_INTERLACED)) + return VENC_MODE_UNKNOWN; + + if (vm->pixelclock == omap_dss_pal_vm.pixelclock && + vm->hactive == omap_dss_pal_vm.hactive && + vm->vactive == omap_dss_pal_vm.vactive) + return VENC_MODE_PAL; + + if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock && + vm->hactive == omap_dss_ntsc_vm.hactive && + vm->vactive == omap_dss_ntsc_vm.vactive) + return VENC_MODE_NTSC; + + return VENC_MODE_UNKNOWN; +} static struct { struct platform_device *pdev; @@ -311,6 +333,7 @@ static struct { struct videomode vm; enum omap_dss_venc_type type; bool invert_polarity; + bool requires_tv_dac_clk; struct omap_dss_device output; } venc; @@ -424,14 +447,14 @@ static void venc_runtime_put(void) static const struct venc_config *venc_timings_to_config(struct videomode *vm) { - if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0) + switch (venc_get_videomode(vm)) { + default: + WARN_ON_ONCE(1); + case VENC_MODE_PAL: return &venc_config_pal_trm; - - if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0) + case VENC_MODE_NTSC: return &venc_config_ntsc_trm; - - BUG(); - return NULL; + } } static int venc_power_on(struct omap_dss_device *dssdev) @@ -542,15 +565,28 @@ static void venc_display_disable(struct omap_dss_device *dssdev) static void venc_set_timings(struct omap_dss_device *dssdev, struct videomode *vm) { + struct videomode actual_vm; + DSSDBG("venc_set_timings\n"); mutex_lock(&venc.venc_lock); + switch (venc_get_videomode(vm)) { + default: + WARN_ON_ONCE(1); + case VENC_MODE_PAL: + actual_vm = omap_dss_pal_vm; + break; + case VENC_MODE_NTSC: + actual_vm = omap_dss_ntsc_vm; + break; + } + /* Reset WSS data when the TV standard changes. */ - if (memcmp(&venc.vm, vm, sizeof(*vm))) + if (memcmp(&venc.vm, &actual_vm, sizeof(actual_vm))) venc.wss_data = 0; - venc.vm = *vm; + venc.vm = actual_vm; dispc_set_tv_pclk(13500000); @@ -562,13 +598,13 @@ static int venc_check_timings(struct omap_dss_device *dssdev, { DSSDBG("venc_check_timings\n"); - if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0) - return 0; - - if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0) + switch (venc_get_videomode(vm)) { + case VENC_MODE_PAL: + case VENC_MODE_NTSC: return 0; - - return -EINVAL; + default: + return -EINVAL; + } } static void venc_get_timings(struct omap_dss_device *dssdev, @@ -616,26 +652,6 @@ err: return r; } -static void venc_set_type(struct omap_dss_device *dssdev, - enum omap_dss_venc_type type) -{ - mutex_lock(&venc.venc_lock); - - venc.type = type; - - mutex_unlock(&venc.venc_lock); -} - -static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev, - bool invert_polarity) -{ - mutex_lock(&venc.venc_lock); - - venc.invert_polarity = invert_polarity; - - mutex_unlock(&venc.venc_lock); -} - static int venc_init_regulator(void) { struct regulator *vdda_dac; @@ -643,11 +659,7 @@ static int venc_init_regulator(void) if (venc.vdda_dac_reg != NULL) return 0; - if (venc.pdev->dev.of_node) - vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda"); - else - vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac"); - + vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda"); if (IS_ERR(vdda_dac)) { if (PTR_ERR(vdda_dac) != -EPROBE_DEFER) DSSERR("can't get VDDA_DAC regulator\n"); @@ -717,7 +729,7 @@ static int venc_get_clocks(struct platform_device *pdev) { struct clk *clk; - if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) { + if (venc.requires_tv_dac_clk) { clk = devm_clk_get(&pdev->dev, "tv_dac_clk"); if (IS_ERR(clk)) { DSSERR("can't get tv_dac_clk\n"); @@ -783,9 +795,6 @@ static const struct omapdss_atv_ops venc_ops = { .set_timings = venc_set_timings, .get_timings = venc_get_timings, - .set_type = venc_set_type, - .invert_vid_out_polarity = venc_invert_vid_out_polarity, - .set_wss = venc_set_wss, .get_wss = venc_get_wss, }; @@ -855,6 +864,12 @@ err: } /* VENC HW IP initialisation */ +static const struct soc_device_attribute venc_soc_devices[] = { + { .machine = "OMAP3[45]*" }, + { .machine = "AM35*" }, + { /* sentinel */ } +}; + static int venc_bind(struct device *dev, struct device *master, void *data) { struct platform_device *pdev = to_platform_device(dev); @@ -864,22 +879,18 @@ static int venc_bind(struct device *dev, struct device *master, void *data) venc.pdev = pdev; + /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ + if (soc_device_match(venc_soc_devices)) + venc.requires_tv_dac_clk = true; + mutex_init(&venc.venc_lock); venc.wss_data = 0; venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); - if (!venc_mem) { - DSSERR("can't get IORESOURCE_MEM VENC\n"); - return -EINVAL; - } - - venc.base = devm_ioremap(&pdev->dev, venc_mem->start, - resource_size(venc_mem)); - if (!venc.base) { - DSSERR("can't ioremap VENC\n"); - return -ENOMEM; - } + venc.base = devm_ioremap_resource(&pdev->dev, venc_mem); + if (IS_ERR(venc.base)) + return PTR_ERR(venc.base); r = venc_get_clocks(pdev); if (r) @@ -896,12 +907,10 @@ static int venc_bind(struct device *dev, struct device *master, void *data) venc_runtime_put(); - if (pdev->dev.of_node) { - r = venc_probe_of(pdev); - if (r) { - DSSERR("Invalid DT data\n"); - goto err_probe_of; - } + r = venc_probe_of(pdev); + if (r) { + DSSERR("Invalid DT data\n"); + goto err_probe_of; } dss_debugfs_create_file("venc", venc_dump_regs); diff --git a/drivers/gpu/drm/omapdrm/dss/video-pll.c b/drivers/gpu/drm/omapdrm/dss/video-pll.c index 7429de928d4e..38a239cc5e04 100644 --- a/drivers/gpu/drm/omapdrm/dss/video-pll.c +++ b/drivers/gpu/drm/omapdrm/dss/video-pll.c @@ -19,7 +19,6 @@ #include "omapdss.h" #include "dss.h" -#include "dss_features.h" struct dss_video_pll { struct dss_pll pll; @@ -131,6 +130,8 @@ static const struct dss_pll_hw dss_dra7_video_pll_hw = { .mX_lsb[3] = 5, .has_refsel = true, + + .errata_i886 = true, }; struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, @@ -150,33 +151,17 @@ struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, /* PLL CONTROL */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]); - if (!res) { - dev_err(&pdev->dev, - "missing platform resource data for pll%d\n", id); - return ERR_PTR(-ENODEV); - } - pll_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pll_base)) { - dev_err(&pdev->dev, "failed to ioremap pll%d reg_name\n", id); + if (IS_ERR(pll_base)) return ERR_CAST(pll_base); - } /* CLOCK CONTROL */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, clkctrl_name[id]); - if (!res) { - dev_err(&pdev->dev, - "missing platform resource data for pll%d\n", id); - return ERR_PTR(-ENODEV); - } - clkctrl_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(clkctrl_base)) { - dev_err(&pdev->dev, "failed to ioremap pll%d clkctrl\n", id); + if (IS_ERR(clkctrl_base)) return ERR_CAST(clkctrl_base); - } /* CLKIN */ diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c b/drivers/gpu/drm/omapdrm/omap_connector.c index c24b6b783e9a..aa5ba9ae2191 100644 --- a/drivers/gpu/drm/omapdrm/omap_connector.c +++ b/drivers/gpu/drm/omapdrm/omap_connector.c @@ -35,6 +35,23 @@ struct omap_connector { bool hdmi_mode; }; +static void omap_connector_hpd_cb(void *cb_data, + enum drm_connector_status status) +{ + struct omap_connector *omap_connector = cb_data; + struct drm_connector *connector = &omap_connector->base; + struct drm_device *dev = connector->dev; + enum drm_connector_status old_status; + + mutex_lock(&dev->mode_config.mutex); + old_status = connector->status; + connector->status = status; + mutex_unlock(&dev->mode_config.mutex); + + if (old_status != status) + drm_kms_helper_hotplug_event(dev); +} + bool omap_connector_get_hdmi_mode(struct drm_connector *connector) { struct omap_connector *omap_connector = to_omap_connector(connector); @@ -75,6 +92,10 @@ static void omap_connector_destroy(struct drm_connector *connector) struct omap_dss_device *dssdev = omap_connector->dssdev; DBG("%s", omap_connector->dssdev->name); + if (connector->polled == DRM_CONNECTOR_POLL_HPD && + dssdev->driver->unregister_hpd_cb) { + dssdev->driver->unregister_hpd_cb(dssdev); + } drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree(omap_connector); @@ -195,7 +216,6 @@ static int omap_connector_mode_valid(struct drm_connector *connector, } static const struct drm_connector_funcs omap_connector_funcs = { - .dpms = drm_atomic_helper_connector_dpms, .reset = drm_atomic_helper_connector_reset, .detect = omap_connector_detect, .fill_modes = drm_helper_probe_single_connector_modes, @@ -216,6 +236,7 @@ struct drm_connector *omap_connector_init(struct drm_device *dev, { struct drm_connector *connector = NULL; struct omap_connector *omap_connector; + bool hpd_supported = false; DBG("%s", dssdev->name); @@ -233,7 +254,20 @@ struct drm_connector *omap_connector_init(struct drm_device *dev, connector_type); drm_connector_helper_add(connector, &omap_connector_helper_funcs); - if (dssdev->driver->detect) + if (dssdev->driver->register_hpd_cb) { + int ret = dssdev->driver->register_hpd_cb(dssdev, + omap_connector_hpd_cb, + omap_connector); + if (!ret) + hpd_supported = true; + else if (ret != -ENOTSUPP) + DBG("%s: Failed to register HPD callback (%d).", + dssdev->name, ret); + } + + if (hpd_supported) + connector->polled = DRM_CONNECTOR_POLL_HPD; + else if (dssdev->driver->detect) connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; else diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index dccd03726796..cc85c16cbc2a 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -26,6 +26,16 @@ #include "omap_drv.h" +#define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base) + +struct omap_crtc_state { + /* Must be first. */ + struct drm_crtc_state base; + /* Shadow values for legacy userspace support. */ + unsigned int rotation; + unsigned int zpos; +}; + #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) struct omap_crtc { @@ -343,7 +353,21 @@ static void omap_crtc_destroy(struct drm_crtc *crtc) kfree(omap_crtc); } -static void omap_crtc_enable(struct drm_crtc *crtc) +static void omap_crtc_arm_event(struct drm_crtc *crtc) +{ + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + + WARN_ON(omap_crtc->pending); + omap_crtc->pending = true; + + if (crtc->state->event) { + omap_crtc->event = crtc->state->event; + crtc->state->event = NULL; + } +} + +static void omap_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); int ret; @@ -355,17 +379,24 @@ static void omap_crtc_enable(struct drm_crtc *crtc) ret = drm_crtc_vblank_get(crtc); WARN_ON(ret != 0); - WARN_ON(omap_crtc->pending); - omap_crtc->pending = true; + omap_crtc_arm_event(crtc); spin_unlock_irq(&crtc->dev->event_lock); } -static void omap_crtc_disable(struct drm_crtc *crtc) +static void omap_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); DBG("%s", omap_crtc->name); + spin_lock_irq(&crtc->dev->event_lock); + if (crtc->state->event) { + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; + } + spin_unlock_irq(&crtc->dev->event_lock); + drm_crtc_vblank_off(crtc); } @@ -424,6 +455,8 @@ static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) static int omap_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { + struct drm_plane_state *pri_state; + if (state->color_mgmt_changed && state->gamma_lut) { uint length = state->gamma_lut->length / sizeof(struct drm_color_lut); @@ -432,6 +465,16 @@ static int omap_crtc_atomic_check(struct drm_crtc *crtc, return -EINVAL; } + pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary); + if (pri_state) { + struct omap_crtc_state *omap_crtc_state = + to_omap_crtc_state(state); + + /* Mirror new values for zpos and rotation in omap_crtc_state */ + omap_crtc_state->zpos = pri_state->zpos; + omap_crtc_state->rotation = pri_state->rotation; + } + return 0; } @@ -473,48 +516,36 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, spin_lock_irq(&crtc->dev->event_lock); priv->dispc_ops->mgr_go(omap_crtc->channel); - - WARN_ON(omap_crtc->pending); - omap_crtc->pending = true; - - if (crtc->state->event) - omap_crtc->event = crtc->state->event; + omap_crtc_arm_event(crtc); spin_unlock_irq(&crtc->dev->event_lock); } -static bool omap_crtc_is_plane_prop(struct drm_crtc *crtc, - struct drm_property *property) -{ - struct drm_device *dev = crtc->dev; - struct omap_drm_private *priv = dev->dev_private; - - return property == priv->zorder_prop || - property == crtc->primary->rotation_property; -} - static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, struct drm_crtc_state *state, struct drm_property *property, uint64_t val) { - if (omap_crtc_is_plane_prop(crtc, property)) { - struct drm_plane_state *plane_state; - struct drm_plane *plane = crtc->primary; - - /* - * Delegate property set to the primary plane. Get the plane - * state and set the property directly. - */ - - plane_state = drm_atomic_get_plane_state(state->state, plane); - if (IS_ERR(plane_state)) - return PTR_ERR(plane_state); + struct omap_drm_private *priv = crtc->dev->dev_private; + struct drm_plane_state *plane_state; - return drm_atomic_plane_set_property(plane, plane_state, - property, val); - } + /* + * Delegate property set to the primary plane. Get the plane state and + * set the property directly, the shadow copy will be assigned in the + * omap_crtc_atomic_check callback. This way updates to plane state will + * always be mirrored in the crtc state correctly. + */ + plane_state = drm_atomic_get_plane_state(state->state, crtc->primary); + if (IS_ERR(plane_state)) + return PTR_ERR(plane_state); + + if (property == crtc->primary->rotation_property) + plane_state->rotation = val; + else if (property == priv->zorder_prop) + plane_state->zpos = val; + else + return -EINVAL; - return -EINVAL; + return 0; } static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, @@ -522,28 +553,60 @@ static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, struct drm_property *property, uint64_t *val) { - if (omap_crtc_is_plane_prop(crtc, property)) { - /* - * Delegate property get to the primary plane. The - * drm_atomic_plane_get_property() function isn't exported, but - * can be called through drm_object_property_get_value() as that - * will call drm_atomic_get_property() for atomic drivers. - */ - return drm_object_property_get_value(&crtc->primary->base, - property, val); - } + struct omap_drm_private *priv = crtc->dev->dev_private; + struct omap_crtc_state *omap_state = to_omap_crtc_state(state); + + if (property == crtc->primary->rotation_property) + *val = omap_state->rotation; + else if (property == priv->zorder_prop) + *val = omap_state->zpos; + else + return -EINVAL; + + return 0; +} + +static void omap_crtc_reset(struct drm_crtc *crtc) +{ + if (crtc->state) + __drm_atomic_helper_crtc_destroy_state(crtc->state); + + kfree(crtc->state); + crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL); + + if (crtc->state) + crtc->state->crtc = crtc; +} + +static struct drm_crtc_state * +omap_crtc_duplicate_state(struct drm_crtc *crtc) +{ + struct omap_crtc_state *state, *current_state; + + if (WARN_ON(!crtc->state)) + return NULL; + + current_state = to_omap_crtc_state(crtc->state); + + state = kmalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return NULL; + + __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); + + state->zpos = current_state->zpos; + state->rotation = current_state->rotation; - return -EINVAL; + return &state->base; } static const struct drm_crtc_funcs omap_crtc_funcs = { - .reset = drm_atomic_helper_crtc_reset, + .reset = omap_crtc_reset, .set_config = drm_atomic_helper_set_config, .destroy = omap_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .gamma_set = drm_atomic_helper_legacy_gamma_set, - .set_property = drm_atomic_helper_crtc_set_property, - .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_duplicate_state = omap_crtc_duplicate_state, .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, .atomic_set_property = omap_crtc_atomic_set_property, .atomic_get_property = omap_crtc_atomic_get_property, @@ -553,11 +616,11 @@ static const struct drm_crtc_funcs omap_crtc_funcs = { static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { .mode_set_nofb = omap_crtc_mode_set_nofb, - .disable = omap_crtc_disable, - .enable = omap_crtc_enable, .atomic_check = omap_crtc_atomic_check, .atomic_begin = omap_crtc_atomic_begin, .atomic_flush = omap_crtc_atomic_flush, + .atomic_enable = omap_crtc_atomic_enable, + .atomic_disable = omap_crtc_atomic_disable, }; /* ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c index 3cab06661a08..1dd3dafc59af 100644 --- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c +++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c @@ -388,7 +388,7 @@ struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w, u32 min_align = 128; int ret; unsigned long flags; - size_t slot_bytes; + u32 slot_bytes; BUG_ON(!validfmt(fmt)); diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index e1f47f0b3ccf..cdf5b0601eba 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -17,7 +17,7 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <linux/wait.h> +#include <linux/sys_soc.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> @@ -54,23 +54,16 @@ static void omap_fb_output_poll_changed(struct drm_device *dev) drm_fb_helper_hotplug_event(priv->fbdev); } -struct omap_atomic_state_commit { - struct work_struct work; - struct drm_device *dev; - struct drm_atomic_state *state; - u32 crtcs; -}; - static void omap_atomic_wait_for_completion(struct drm_device *dev, struct drm_atomic_state *old_state) { - struct drm_crtc_state *old_crtc_state; + struct drm_crtc_state *new_crtc_state; struct drm_crtc *crtc; unsigned int i; int ret; - for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { - if (!crtc->state->enable) + for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) { + if (!new_crtc_state->active) continue; ret = omap_crtc_wait_pending(crtc); @@ -81,128 +74,67 @@ static void omap_atomic_wait_for_completion(struct drm_device *dev, } } -static void omap_atomic_complete(struct omap_atomic_state_commit *commit) +static void omap_atomic_commit_tail(struct drm_atomic_state *old_state) { - struct drm_device *dev = commit->dev; + struct drm_device *dev = old_state->dev; struct omap_drm_private *priv = dev->dev_private; - struct drm_atomic_state *old_state = commit->state; - /* Apply the atomic update. */ priv->dispc_ops->runtime_get(); + /* Apply the atomic update. */ drm_atomic_helper_commit_modeset_disables(dev, old_state); - /* With the current dss dispc implementation we have to enable - * the new modeset before we can commit planes. The dispc ovl - * configuration relies on the video mode configuration been - * written into the HW when the ovl configuration is - * calculated. - * - * This approach is not ideal because after a mode change the - * plane update is executed only after the first vblank - * interrupt. The dispc implementation should be fixed so that - * it is able use uncommitted drm state information. - */ - drm_atomic_helper_commit_modeset_enables(dev, old_state); - omap_atomic_wait_for_completion(dev, old_state); - - drm_atomic_helper_commit_planes(dev, old_state, 0); + if (priv->omaprev != 0x3430) { + /* With the current dss dispc implementation we have to enable + * the new modeset before we can commit planes. The dispc ovl + * configuration relies on the video mode configuration been + * written into the HW when the ovl configuration is + * calculated. + * + * This approach is not ideal because after a mode change the + * plane update is executed only after the first vblank + * interrupt. The dispc implementation should be fixed so that + * it is able use uncommitted drm state information. + */ + drm_atomic_helper_commit_modeset_enables(dev, old_state); + omap_atomic_wait_for_completion(dev, old_state); + + drm_atomic_helper_commit_planes(dev, old_state, 0); + + drm_atomic_helper_commit_hw_done(old_state); + } else { + /* + * OMAP3 DSS seems to have issues with the work-around above, + * resulting in endless sync losts if a crtc is enabled without + * a plane. For now, skip the WA for OMAP3. + */ + drm_atomic_helper_commit_planes(dev, old_state, 0); + + drm_atomic_helper_commit_modeset_enables(dev, old_state); + + drm_atomic_helper_commit_hw_done(old_state); + } + /* + * Wait for completion of the page flips to ensure that old buffers + * can't be touched by the hardware anymore before cleaning up planes. + */ omap_atomic_wait_for_completion(dev, old_state); drm_atomic_helper_cleanup_planes(dev, old_state); priv->dispc_ops->runtime_put(); - - drm_atomic_state_put(old_state); - - /* Complete the commit, wake up any waiter. */ - spin_lock(&priv->commit.lock); - priv->commit.pending &= ~commit->crtcs; - spin_unlock(&priv->commit.lock); - - wake_up_all(&priv->commit.wait); - - kfree(commit); -} - -static void omap_atomic_work(struct work_struct *work) -{ - struct omap_atomic_state_commit *commit = - container_of(work, struct omap_atomic_state_commit, work); - - omap_atomic_complete(commit); -} - -static bool omap_atomic_is_pending(struct omap_drm_private *priv, - struct omap_atomic_state_commit *commit) -{ - bool pending; - - spin_lock(&priv->commit.lock); - pending = priv->commit.pending & commit->crtcs; - spin_unlock(&priv->commit.lock); - - return pending; } -static int omap_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, bool nonblock) -{ - struct omap_drm_private *priv = dev->dev_private; - struct omap_atomic_state_commit *commit; - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - int i, ret; - - ret = drm_atomic_helper_prepare_planes(dev, state); - if (ret) - return ret; - - /* Allocate the commit object. */ - commit = kzalloc(sizeof(*commit), GFP_KERNEL); - if (commit == NULL) { - ret = -ENOMEM; - goto error; - } - - INIT_WORK(&commit->work, omap_atomic_work); - commit->dev = dev; - commit->state = state; - - /* Wait until all affected CRTCs have completed previous commits and - * mark them as pending. - */ - for_each_crtc_in_state(state, crtc, crtc_state, i) - commit->crtcs |= drm_crtc_mask(crtc); - - wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit)); - - spin_lock(&priv->commit.lock); - priv->commit.pending |= commit->crtcs; - spin_unlock(&priv->commit.lock); - - /* Swap the state, this is the point of no return. */ - drm_atomic_helper_swap_state(state, true); - - drm_atomic_state_get(state); - if (nonblock) - schedule_work(&commit->work); - else - omap_atomic_complete(commit); - - return 0; - -error: - drm_atomic_helper_cleanup_planes(dev, state); - return ret; -} +static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = { + .atomic_commit_tail = omap_atomic_commit_tail, +}; static const struct drm_mode_config_funcs omap_mode_config_funcs = { .fb_create = omap_framebuffer_create, .output_poll_changed = omap_fb_output_poll_changed, .atomic_check = drm_atomic_helper_check, - .atomic_commit = omap_atomic_commit, + .atomic_commit = drm_atomic_helper_commit, }; static int get_connector_type(struct omap_dss_device *dssdev) @@ -214,6 +146,14 @@ static int get_connector_type(struct omap_dss_device *dssdev) return DRM_MODE_CONNECTOR_DVID; case OMAP_DISPLAY_TYPE_DSI: return DRM_MODE_CONNECTOR_DSI; + case OMAP_DISPLAY_TYPE_DPI: + case OMAP_DISPLAY_TYPE_DBI: + return DRM_MODE_CONNECTOR_DPI; + case OMAP_DISPLAY_TYPE_VENC: + /* TODO: This could also be composite */ + return DRM_MODE_CONNECTOR_SVIDEO; + case OMAP_DISPLAY_TYPE_SDI: + return DRM_MODE_CONNECTOR_LVDS; default: return DRM_MODE_CONNECTOR_Unknown; } @@ -261,8 +201,10 @@ cleanup: static int omap_modeset_init_properties(struct drm_device *dev) { struct omap_drm_private *priv = dev->dev_private; + unsigned int num_planes = priv->dispc_ops->get_num_ovls(); - priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3); + priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, + num_planes - 1); if (!priv->zorder_prop) return -ENOMEM; @@ -385,6 +327,7 @@ static int omap_modeset_init(struct drm_device *dev) dev->mode_config.max_height = 2048; dev->mode_config.funcs = &omap_mode_config_funcs; + dev->mode_config.helper_private = &omap_mode_config_helper_funcs; drm_mode_config_reset(dev); @@ -394,6 +337,32 @@ static int omap_modeset_init(struct drm_device *dev) } /* + * Enable the HPD in external components if supported + */ +static void omap_modeset_enable_external_hpd(void) +{ + struct omap_dss_device *dssdev = NULL; + + for_each_dss_dev(dssdev) { + if (dssdev->driver->enable_hpd) + dssdev->driver->enable_hpd(dssdev); + } +} + +/* + * Disable the HPD in external components if supported + */ +static void omap_modeset_disable_external_hpd(void) +{ + struct omap_dss_device *dssdev = NULL; + + for_each_dss_dev(dssdev) { + if (dssdev->driver->disable_hpd) + dssdev->driver->disable_hpd(dssdev); + } +} + +/* * drm ioctl funcs */ @@ -447,53 +416,6 @@ static int ioctl_gem_new(struct drm_device *dev, void *data, &args->handle); } -static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_omap_gem_cpu_prep *args = data; - struct drm_gem_object *obj; - int ret; - - VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op); - - obj = drm_gem_object_lookup(file_priv, args->handle); - if (!obj) - return -ENOENT; - - ret = omap_gem_op_sync(obj, args->op); - - if (!ret) - ret = omap_gem_op_start(obj, args->op); - - drm_gem_object_unreference_unlocked(obj); - - return ret; -} - -static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_omap_gem_cpu_fini *args = data; - struct drm_gem_object *obj; - int ret; - - VERB("%p:%p: handle=%d", dev, file_priv, args->handle); - - obj = drm_gem_object_lookup(file_priv, args->handle); - if (!obj) - return -ENOENT; - - /* XXX flushy, flushy */ - ret = 0; - - if (!ret) - ret = omap_gem_op_finish(obj, args->op); - - drm_gem_object_unreference_unlocked(obj); - - return ret; -} - static int ioctl_gem_info(struct drm_device *dev, void *data, struct drm_file *file_priv) { @@ -522,9 +444,11 @@ static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY), DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_AUTH | DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, + /* Deprecated, to be removed. */ + DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop, DRM_AUTH | DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, + /* Deprecated, to be removed. */ + DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop, DRM_AUTH | DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_AUTH | DRM_RENDER_ALLOW), @@ -553,44 +477,11 @@ static int dev_open(struct drm_device *dev, struct drm_file *file) */ static void dev_lastclose(struct drm_device *dev) { - int i; - - /* we don't support vga_switcheroo.. so just make sure the fbdev - * mode is active - */ struct omap_drm_private *priv = dev->dev_private; int ret; DBG("lastclose: dev=%p", dev); - /* need to restore default rotation state.. not sure - * if there is a cleaner way to restore properties to - * default state? Maybe a flag that properties should - * automatically be restored to default state on - * lastclose? - */ - for (i = 0; i < priv->num_crtcs; i++) { - struct drm_crtc *crtc = priv->crtcs[i]; - - if (!crtc->primary->rotation_property) - continue; - - drm_object_property_set_value(&crtc->base, - crtc->primary->rotation_property, - DRM_ROTATE_0); - } - - for (i = 0; i < priv->num_planes; i++) { - struct drm_plane *plane = priv->planes[i]; - - if (!plane->rotation_property) - continue; - - drm_object_property_set_value(&plane->base, - plane->rotation_property, - DRM_ROTATE_0); - } - if (priv->fbdev) { ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); if (ret) @@ -608,6 +499,7 @@ static const struct file_operations omapdriver_fops = { .owner = THIS_MODULE, .open = drm_open, .unlocked_ioctl = drm_ioctl, + .compat_ioctl = drm_compat_ioctl, .release = drm_release, .mmap = omap_gem_mmap, .poll = drm_poll, @@ -631,7 +523,6 @@ static struct drm_driver omap_drm_driver = { .gem_vm_ops = &omap_gem_vm_ops, .dumb_create = omap_gem_dumb_create, .dumb_map_offset = omap_gem_dumb_map_offset, - .dumb_destroy = drm_gem_dumb_destroy, .ioctls = ioctls, .num_ioctls = DRM_OMAP_NUM_IOCTLS, .fops = &omapdriver_fops, @@ -643,9 +534,17 @@ static struct drm_driver omap_drm_driver = { .patchlevel = DRIVER_PATCHLEVEL, }; +static const struct soc_device_attribute omapdrm_soc_devices[] = { + { .family = "OMAP3", .data = (void *)0x3430 }, + { .family = "OMAP4", .data = (void *)0x4430 }, + { .family = "OMAP5", .data = (void *)0x5430 }, + { .family = "DRA7", .data = (void *)0x0752 }, + { /* sentinel */ } +}; + static int pdev_probe(struct platform_device *pdev) { - struct omap_drm_platform_data *pdata = pdev->dev.platform_data; + const struct soc_device_attribute *soc; struct omap_drm_private *priv; struct drm_device *ddev; unsigned int i; @@ -656,6 +555,12 @@ static int pdev_probe(struct platform_device *pdev) if (omapdss_is_initialized() == false) return -EPROBE_DEFER; + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(&pdev->dev, "Failed to set the DMA mask\n"); + return ret; + } + omap_crtc_pre_init(); ret = omap_connect_dssdevs(); @@ -671,11 +576,10 @@ static int pdev_probe(struct platform_device *pdev) priv->dispc_ops = dispc_get_ops(); - priv->omaprev = pdata->omaprev; + soc = soc_device_match(omapdrm_soc_devices); + priv->omaprev = soc ? (unsigned int)soc->data : 0; priv->wq = alloc_ordered_workqueue("omapdrm", 0); - init_waitqueue_head(&priv->commit.wait); - spin_lock_init(&priv->commit.lock); spin_lock_init(&priv->list_lock); INIT_LIST_HEAD(&priv->obj_list); @@ -710,6 +614,7 @@ static int pdev_probe(struct platform_device *pdev) priv->fbdev = omap_fbdev_init(ddev); drm_kms_helper_poll_init(ddev); + omap_modeset_enable_external_hpd(); /* * Register the DRM device with the core and the connectors with @@ -722,6 +627,7 @@ static int pdev_probe(struct platform_device *pdev) return 0; err_cleanup_helpers: + omap_modeset_disable_external_hpd(); drm_kms_helper_poll_fini(ddev); if (priv->fbdev) omap_fbdev_free(ddev); @@ -750,6 +656,7 @@ static int pdev_remove(struct platform_device *pdev) drm_dev_unregister(ddev); + omap_modeset_disable_external_hpd(); drm_kms_helper_poll_fini(ddev); if (priv->fbdev) @@ -841,7 +748,7 @@ static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume); static struct platform_driver pdev = { .driver = { - .name = DRIVER_NAME, + .name = "omapdrm", .pm = &omapdrm_pm_ops, }, .probe = pdev_probe, diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index 7a4c57eb6536..4bd1e9070b31 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -21,9 +21,8 @@ #define __OMAP_DRV_H__ #include <linux/module.h> -#include <linux/platform_data/omap_drm.h> #include <linux/types.h> -#include <linux/wait.h> +#include <linux/workqueue.h> #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> @@ -39,15 +38,6 @@ struct omap_drm_usergart; -/* parameters which describe (unrotated) coordinates of scanout within a fb: */ -struct omap_drm_window { - uint32_t rotation; - int32_t crtc_x, crtc_y; /* signed because can be offscreen */ - uint32_t crtc_w, crtc_h; - uint32_t src_x, src_y; - uint32_t src_w, src_h; -}; - /* For KMS code that needs to wait for a certain # of IRQs: */ struct omap_irq_wait; @@ -93,13 +83,6 @@ struct omap_drm_private { spinlock_t wait_lock; /* protects the wait_list */ struct list_head wait_list; /* list of omap_irq_wait */ uint32_t irq_mask; /* enabled irqs in addition to wait_list */ - - /* atomic commit */ - struct { - wait_queue_head_t wait; - u32 pending; - spinlock_t lock; /* Protects commit.pending */ - } commit; }; @@ -158,8 +141,6 @@ struct drm_encoder *omap_connector_attached_encoder( struct drm_connector *connector); bool omap_connector_get_hdmi_mode(struct drm_connector *connector); -uint32_t omap_framebuffer_get_formats(uint32_t *pixel_formats, - uint32_t max_formats, enum omap_color_mode supported_modes); struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, @@ -167,7 +148,7 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, int omap_framebuffer_pin(struct drm_framebuffer *fb); void omap_framebuffer_unpin(struct drm_framebuffer *fb); void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, - struct omap_drm_window *win, struct omap_overlay_info *info); + struct drm_plane_state *state, struct omap_overlay_info *info); struct drm_connector *omap_framebuffer_get_next_connector( struct drm_framebuffer *fb, struct drm_connector *from); bool omap_framebuffer_supports_rotation(struct drm_framebuffer *fb); @@ -191,24 +172,18 @@ int omap_gem_mmap(struct file *filp, struct vm_area_struct *vma); int omap_gem_mmap_obj(struct drm_gem_object *obj, struct vm_area_struct *vma); int omap_gem_fault(struct vm_fault *vmf); -int omap_gem_op_start(struct drm_gem_object *obj, enum omap_gem_op op); -int omap_gem_op_finish(struct drm_gem_object *obj, enum omap_gem_op op); -int omap_gem_op_sync(struct drm_gem_object *obj, enum omap_gem_op op); -int omap_gem_op_async(struct drm_gem_object *obj, enum omap_gem_op op, - void (*fxn)(void *arg), void *arg); int omap_gem_roll(struct drm_gem_object *obj, uint32_t roll); -void omap_gem_cpu_sync(struct drm_gem_object *obj, int pgoff); -void omap_gem_dma_sync(struct drm_gem_object *obj, +void omap_gem_cpu_sync_page(struct drm_gem_object *obj, int pgoff); +void omap_gem_dma_sync_buffer(struct drm_gem_object *obj, enum dma_data_direction dir); -int omap_gem_get_paddr(struct drm_gem_object *obj, - dma_addr_t *paddr, bool remap); -void omap_gem_put_paddr(struct drm_gem_object *obj); +int omap_gem_pin(struct drm_gem_object *obj, dma_addr_t *dma_addr); +void omap_gem_unpin(struct drm_gem_object *obj); int omap_gem_get_pages(struct drm_gem_object *obj, struct page ***pages, bool remap); int omap_gem_put_pages(struct drm_gem_object *obj); uint32_t omap_gem_flags(struct drm_gem_object *obj); -int omap_gem_rotated_paddr(struct drm_gem_object *obj, uint32_t orient, - int x, int y, dma_addr_t *paddr); +int omap_gem_rotated_dma_addr(struct drm_gem_object *obj, uint32_t orient, + int x, int y, dma_addr_t *dma_addr); uint64_t omap_gem_mmap_offset(struct drm_gem_object *obj); size_t omap_gem_mmap_size(struct drm_gem_object *obj); int omap_gem_tiled_stride(struct drm_gem_object *obj, uint32_t orient); diff --git a/drivers/gpu/drm/omapdrm/omap_encoder.c b/drivers/gpu/drm/omapdrm/omap_encoder.c index 86c977b7189a..624f5b50b755 100644 --- a/drivers/gpu/drm/omapdrm/omap_encoder.c +++ b/drivers/gpu/drm/omapdrm/omap_encoder.c @@ -85,7 +85,8 @@ static void omap_encoder_mode_set(struct drm_encoder *encoder, if (hdmi_mode && dssdev->driver->set_hdmi_infoframe) { struct hdmi_avi_infoframe avi; - r = drm_hdmi_avi_infoframe_from_display_mode(&avi, adjusted_mode); + r = drm_hdmi_avi_infoframe_from_display_mode(&avi, adjusted_mode, + false); if (r == 0) dssdev->driver->set_hdmi_infoframe(dssdev, &avi); } diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index 29dc677dd4d3..b1a762b70cbf 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -29,52 +29,34 @@ * framebuffer funcs */ -/* DSS to DRM formats mapping */ -static const struct { - enum omap_color_mode dss_format; - uint32_t pixel_format; -} formats[] = { +static const u32 formats[] = { /* 16bpp [A]RGB: */ - { OMAP_DSS_COLOR_RGB16, DRM_FORMAT_RGB565 }, /* RGB16-565 */ - { OMAP_DSS_COLOR_RGB12U, DRM_FORMAT_RGBX4444 }, /* RGB12x-4444 */ - { OMAP_DSS_COLOR_RGBX16, DRM_FORMAT_XRGB4444 }, /* xRGB12-4444 */ - { OMAP_DSS_COLOR_RGBA16, DRM_FORMAT_RGBA4444 }, /* RGBA12-4444 */ - { OMAP_DSS_COLOR_ARGB16, DRM_FORMAT_ARGB4444 }, /* ARGB16-4444 */ - { OMAP_DSS_COLOR_XRGB16_1555, DRM_FORMAT_XRGB1555 }, /* xRGB15-1555 */ - { OMAP_DSS_COLOR_ARGB16_1555, DRM_FORMAT_ARGB1555 }, /* ARGB16-1555 */ + DRM_FORMAT_RGB565, /* RGB16-565 */ + DRM_FORMAT_RGBX4444, /* RGB12x-4444 */ + DRM_FORMAT_XRGB4444, /* xRGB12-4444 */ + DRM_FORMAT_RGBA4444, /* RGBA12-4444 */ + DRM_FORMAT_ARGB4444, /* ARGB16-4444 */ + DRM_FORMAT_XRGB1555, /* xRGB15-1555 */ + DRM_FORMAT_ARGB1555, /* ARGB16-1555 */ /* 24bpp RGB: */ - { OMAP_DSS_COLOR_RGB24P, DRM_FORMAT_RGB888 }, /* RGB24-888 */ + DRM_FORMAT_RGB888, /* RGB24-888 */ /* 32bpp [A]RGB: */ - { OMAP_DSS_COLOR_RGBX32, DRM_FORMAT_RGBX8888 }, /* RGBx24-8888 */ - { OMAP_DSS_COLOR_RGB24U, DRM_FORMAT_XRGB8888 }, /* xRGB24-8888 */ - { OMAP_DSS_COLOR_RGBA32, DRM_FORMAT_RGBA8888 }, /* RGBA32-8888 */ - { OMAP_DSS_COLOR_ARGB32, DRM_FORMAT_ARGB8888 }, /* ARGB32-8888 */ + DRM_FORMAT_RGBX8888, /* RGBx24-8888 */ + DRM_FORMAT_XRGB8888, /* xRGB24-8888 */ + DRM_FORMAT_RGBA8888, /* RGBA32-8888 */ + DRM_FORMAT_ARGB8888, /* ARGB32-8888 */ /* YUV: */ - { OMAP_DSS_COLOR_NV12, DRM_FORMAT_NV12 }, - { OMAP_DSS_COLOR_YUV2, DRM_FORMAT_YUYV }, - { OMAP_DSS_COLOR_UYVY, DRM_FORMAT_UYVY }, + DRM_FORMAT_NV12, + DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY, }; -/* convert from overlay's pixel formats bitmask to an array of fourcc's */ -uint32_t omap_framebuffer_get_formats(uint32_t *pixel_formats, - uint32_t max_formats, enum omap_color_mode supported_modes) -{ - uint32_t nformats = 0; - int i = 0; - - for (i = 0; i < ARRAY_SIZE(formats) && nformats < max_formats; i++) - if (formats[i].dss_format & supported_modes) - pixel_formats[nformats++] = formats[i].pixel_format; - - return nformats; -} - /* per-plane info for the fb: */ struct plane { struct drm_gem_object *bo; uint32_t pitch; uint32_t offset; - dma_addr_t paddr; + dma_addr_t dma_addr; }; #define to_omap_framebuffer(x) container_of(x, struct omap_framebuffer, base) @@ -83,9 +65,8 @@ struct omap_framebuffer { struct drm_framebuffer base; int pin_count; const struct drm_format_info *format; - enum omap_color_mode dss_format; struct plane planes[2]; - /* lock for pinning (pin_count and planes.paddr) */ + /* lock for pinning (pin_count and planes.dma_addr) */ struct mutex lock; }; @@ -130,7 +111,7 @@ static uint32_t get_linear_addr(struct plane *plane, + (x * format->cpp[n] / (n == 0 ? 1 : format->hsub)) + (y * plane->pitch / (n == 0 ? 1 : format->vsub)); - return plane->paddr + offset; + return plane->dma_addr + offset; } bool omap_framebuffer_supports_rotation(struct drm_framebuffer *fb) @@ -141,99 +122,123 @@ bool omap_framebuffer_supports_rotation(struct drm_framebuffer *fb) return omap_gem_flags(plane->bo) & OMAP_BO_TILED; } +/* Note: DRM rotates counter-clockwise, TILER & DSS rotates clockwise */ +static uint32_t drm_rotation_to_tiler(unsigned int drm_rot) +{ + uint32_t orient; + + switch (drm_rot & DRM_MODE_ROTATE_MASK) { + default: + case DRM_MODE_ROTATE_0: + orient = 0; + break; + case DRM_MODE_ROTATE_90: + orient = MASK_XY_FLIP | MASK_X_INVERT; + break; + case DRM_MODE_ROTATE_180: + orient = MASK_X_INVERT | MASK_Y_INVERT; + break; + case DRM_MODE_ROTATE_270: + orient = MASK_XY_FLIP | MASK_Y_INVERT; + break; + } + + if (drm_rot & DRM_MODE_REFLECT_X) + orient ^= MASK_X_INVERT; + + if (drm_rot & DRM_MODE_REFLECT_Y) + orient ^= MASK_Y_INVERT; + + return orient; +} + /* update ovl info for scanout, handles cases of multi-planar fb's, etc. */ void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, - struct omap_drm_window *win, struct omap_overlay_info *info) + struct drm_plane_state *state, struct omap_overlay_info *info) { struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb); const struct drm_format_info *format = omap_fb->format; struct plane *plane = &omap_fb->planes[0]; uint32_t x, y, orient = 0; - info->color_mode = omap_fb->dss_format; + info->fourcc = fb->format->format; - info->pos_x = win->crtc_x; - info->pos_y = win->crtc_y; - info->out_width = win->crtc_w; - info->out_height = win->crtc_h; - info->width = win->src_w; - info->height = win->src_h; + info->pos_x = state->crtc_x; + info->pos_y = state->crtc_y; + info->out_width = state->crtc_w; + info->out_height = state->crtc_h; + info->width = state->src_w >> 16; + info->height = state->src_h >> 16; - x = win->src_x; - y = win->src_y; + /* DSS driver wants the w & h in rotated orientation */ + if (drm_rotation_90_or_270(state->rotation)) + swap(info->width, info->height); - if (omap_gem_flags(plane->bo) & OMAP_BO_TILED) { - uint32_t w = win->src_w; - uint32_t h = win->src_h; + x = state->src_x >> 16; + y = state->src_y >> 16; - switch (win->rotation & DRM_ROTATE_MASK) { - default: - dev_err(fb->dev->dev, "invalid rotation: %02x", - (uint32_t)win->rotation); - /* fallthru to default to no rotation */ - case 0: - case DRM_ROTATE_0: - orient = 0; - break; - case DRM_ROTATE_90: - orient = MASK_XY_FLIP | MASK_X_INVERT; - break; - case DRM_ROTATE_180: - orient = MASK_X_INVERT | MASK_Y_INVERT; - break; - case DRM_ROTATE_270: - orient = MASK_XY_FLIP | MASK_Y_INVERT; - break; + if (omap_gem_flags(plane->bo) & OMAP_BO_TILED) { + uint32_t w = state->src_w >> 16; + uint32_t h = state->src_h >> 16; + + orient = drm_rotation_to_tiler(state->rotation); + + /* + * omap_gem_rotated_paddr() wants the x & y in tiler units. + * Usually tiler unit size is the same as the pixel size, except + * for YUV422 formats, for which the tiler unit size is 32 bits + * and pixel size is 16 bits. + */ + if (fb->format->format == DRM_FORMAT_UYVY || + fb->format->format == DRM_FORMAT_YUYV) { + x /= 2; + w /= 2; } - if (win->rotation & DRM_REFLECT_X) - orient ^= MASK_X_INVERT; - - if (win->rotation & DRM_REFLECT_Y) - orient ^= MASK_Y_INVERT; - - /* adjust x,y offset for flip/invert: */ - if (orient & MASK_XY_FLIP) - swap(w, h); + /* adjust x,y offset for invert: */ if (orient & MASK_Y_INVERT) y += h - 1; if (orient & MASK_X_INVERT) x += w - 1; - omap_gem_rotated_paddr(plane->bo, orient, x, y, &info->paddr); + /* Note: x and y are in TILER units, not pixels */ + omap_gem_rotated_dma_addr(plane->bo, orient, x, y, + &info->paddr); info->rotation_type = OMAP_DSS_ROT_TILER; + info->rotation = state->rotation ?: DRM_MODE_ROTATE_0; + /* Note: stride in TILER units, not pixels */ info->screen_width = omap_gem_tiled_stride(plane->bo, orient); } else { - switch (win->rotation & DRM_ROTATE_MASK) { + switch (state->rotation & DRM_MODE_ROTATE_MASK) { case 0: - case DRM_ROTATE_0: + case DRM_MODE_ROTATE_0: /* OK */ break; default: dev_warn(fb->dev->dev, "rotation '%d' ignored for non-tiled fb\n", - win->rotation); - win->rotation = 0; + state->rotation); break; } info->paddr = get_linear_addr(plane, format, 0, x, y); - info->rotation_type = OMAP_DSS_ROT_DMA; + info->rotation_type = OMAP_DSS_ROT_NONE; + info->rotation = DRM_MODE_ROTATE_0; info->screen_width = plane->pitch; } /* convert to pixels: */ info->screen_width /= format->cpp[0]; - if (omap_fb->dss_format == OMAP_DSS_COLOR_NV12) { + if (fb->format->format == DRM_FORMAT_NV12) { plane = &omap_fb->planes[1]; if (info->rotation_type == OMAP_DSS_ROT_TILER) { WARN_ON(!(omap_gem_flags(plane->bo) & OMAP_BO_TILED)); - omap_gem_rotated_paddr(plane->bo, orient, - x/2, y/2, &info->p_uv_addr); + omap_gem_rotated_dma_addr(plane->bo, orient, x/2, y/2, + &info->p_uv_addr); } else { info->p_uv_addr = get_linear_addr(plane, format, 1, x, y); } @@ -258,10 +263,10 @@ int omap_framebuffer_pin(struct drm_framebuffer *fb) for (i = 0; i < n; i++) { struct plane *plane = &omap_fb->planes[i]; - ret = omap_gem_get_paddr(plane->bo, &plane->paddr, true); + ret = omap_gem_pin(plane->bo, &plane->dma_addr); if (ret) goto fail; - omap_gem_dma_sync(plane->bo, DMA_TO_DEVICE); + omap_gem_dma_sync_buffer(plane->bo, DMA_TO_DEVICE); } omap_fb->pin_count++; @@ -273,8 +278,8 @@ int omap_framebuffer_pin(struct drm_framebuffer *fb) fail: for (i--; i >= 0; i--) { struct plane *plane = &omap_fb->planes[i]; - omap_gem_put_paddr(plane->bo); - plane->paddr = 0; + omap_gem_unpin(plane->bo); + plane->dma_addr = 0; } mutex_unlock(&omap_fb->lock); @@ -299,8 +304,8 @@ void omap_framebuffer_unpin(struct drm_framebuffer *fb) for (i = 0; i < n; i++) { struct plane *plane = &omap_fb->planes[i]; - omap_gem_put_paddr(plane->bo); - plane->paddr = 0; + omap_gem_unpin(plane->bo); + plane->dma_addr = 0; } mutex_unlock(&omap_fb->lock); @@ -374,7 +379,7 @@ struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, return fb; error: - while (--i > 0) + while (--i >= 0) drm_gem_object_unreference_unlocked(bos[i]); return fb; @@ -386,7 +391,6 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, const struct drm_format_info *format = NULL; struct omap_framebuffer *omap_fb = NULL; struct drm_framebuffer *fb = NULL; - enum omap_color_mode dss_format = 0; unsigned int pitch = mode_cmd->pitches[0]; int ret, i; @@ -397,13 +401,11 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, format = drm_format_info(mode_cmd->pixel_format); for (i = 0; i < ARRAY_SIZE(formats); i++) { - if (formats[i].pixel_format == mode_cmd->pixel_format) { - dss_format = formats[i].dss_format; + if (formats[i] == mode_cmd->pixel_format) break; - } } - if (!format || !dss_format) { + if (!format || i == ARRAY_SIZE(formats)) { dev_dbg(dev->dev, "unsupported pixel format: %4.4s\n", (char *)&mode_cmd->pixel_format); ret = -EINVAL; @@ -418,7 +420,6 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, fb = &omap_fb->base; omap_fb->format = format; - omap_fb->dss_format = dss_format; mutex_init(&omap_fb->lock); /* @@ -449,7 +450,7 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, if (size > omap_gem_mmap_size(bos[i]) - mode_cmd->offsets[i]) { dev_dbg(dev->dev, - "provided buffer object is too small! %d < %d\n", + "provided buffer object is too small! %zu < %d\n", bos[i]->size - mode_cmd->offsets[i], size); ret = -EINVAL; goto fail; @@ -458,7 +459,7 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, plane->bo = bos[i]; plane->offset = mode_cmd->offsets[i]; plane->pitch = pitch; - plane->paddr = 0; + plane->dma_addr = 0; } drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); diff --git a/drivers/gpu/drm/omapdrm/omap_fbdev.c b/drivers/gpu/drm/omapdrm/omap_fbdev.c index 4e89dd537862..9273118040b7 100644 --- a/drivers/gpu/drm/omapdrm/omap_fbdev.c +++ b/drivers/gpu/drm/omapdrm/omap_fbdev.c @@ -106,7 +106,7 @@ static int omap_fbdev_create(struct drm_fb_helper *helper, union omap_gem_size gsize; struct fb_info *fbi = NULL; struct drm_mode_fb_cmd2 mode_cmd = {0}; - dma_addr_t paddr; + dma_addr_t dma_addr; int ret; sizes->surface_bpp = 32; @@ -162,10 +162,9 @@ static int omap_fbdev_create(struct drm_fb_helper *helper, * to it). Then we just need to be sure that we are able to re- * pin it in case of an opps. */ - ret = omap_gem_get_paddr(fbdev->bo, &paddr, true); + ret = omap_gem_pin(fbdev->bo, &dma_addr); if (ret) { - dev_err(dev->dev, - "could not map (paddr)! Skipping framebuffer alloc\n"); + dev_err(dev->dev, "could not pin framebuffer\n"); ret = -ENOMEM; goto fail; } @@ -185,7 +184,6 @@ static int omap_fbdev_create(struct drm_fb_helper *helper, helper->fb = fb; fbi->par = helper; - fbi->flags = FBINFO_DEFAULT; fbi->fbops = &omap_fb_ops; strcpy(fbi->fix.id, MODULE_NAME); @@ -193,11 +191,11 @@ static int omap_fbdev_create(struct drm_fb_helper *helper, drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth); drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height); - dev->mode_config.fb_base = paddr; + dev->mode_config.fb_base = dma_addr; fbi->screen_base = omap_gem_vaddr(fbdev->bo); fbi->screen_size = fbdev->bo->size; - fbi->fix.smem_start = paddr; + fbi->fix.smem_start = dma_addr; fbi->fix.smem_len = fbdev->bo->size; /* if we have DMM, then we can use it for scrolling by just @@ -303,8 +301,8 @@ void omap_fbdev_free(struct drm_device *dev) fbdev = to_omap_fbdev(priv->fbdev); - /* release the ref taken in omap_fbdev_create() */ - omap_gem_put_paddr(fbdev->bo); + /* unpin the GEM object pinned in omap_fbdev_create() */ + omap_gem_unpin(fbdev->bo); /* this will free the backing object */ if (fbdev->fb) diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c b/drivers/gpu/drm/omapdrm/omap_gem.c index 68a75b829b71..5c5c86ddd6f4 100644 --- a/drivers/gpu/drm/omapdrm/omap_gem.c +++ b/drivers/gpu/drm/omapdrm/omap_gem.c @@ -50,7 +50,7 @@ struct omap_gem_object { uint32_t roll; /** - * paddr contains the buffer DMA address. It is valid for + * dma_addr contains the buffer DMA address. It is valid for * * - buffers allocated through the DMA mapping API (with the * OMAP_BO_MEM_DMA_API flag set) @@ -58,24 +58,24 @@ struct omap_gem_object { * - buffers imported from dmabuf (with the OMAP_BO_MEM_DMABUF flag set) * if they are physically contiguous (when sgt->orig_nents == 1) * - * - buffers mapped through the TILER when paddr_cnt is not zero, in + * - buffers mapped through the TILER when dma_addr_cnt is not zero, in * which case the DMA address points to the TILER aperture * * Physically contiguous buffers have their DMA address equal to the * physical address as we don't remap those buffers through the TILER. * * Buffers mapped to the TILER have their DMA address pointing to the - * TILER aperture. As TILER mappings are refcounted (through paddr_cnt) - * the DMA address must be accessed through omap_get_get_paddr() to - * ensure that the mapping won't disappear unexpectedly. References must - * be released with omap_gem_put_paddr(). + * TILER aperture. As TILER mappings are refcounted (through + * dma_addr_cnt) the DMA address must be accessed through omap_gem_pin() + * to ensure that the mapping won't disappear unexpectedly. References + * must be released with omap_gem_unpin(). */ - dma_addr_t paddr; + dma_addr_t dma_addr; /** - * # of users of paddr + * # of users of dma_addr */ - uint32_t paddr_cnt; + uint32_t dma_addr_cnt; /** * If the buffer has been imported from a dmabuf the OMAP_DB_DMABUF flag @@ -95,25 +95,12 @@ struct omap_gem_object { struct page **pages; /** addresses corresponding to pages in above array */ - dma_addr_t *addrs; + dma_addr_t *dma_addrs; /** * Virtual address, if mapped. */ void *vaddr; - - /** - * sync-object allocated on demand (if needed) - * - * Per-buffer sync-object for tracking pending and completed hw/dma - * read and write operations. - */ - struct { - uint32_t write_pending; - uint32_t write_complete; - uint32_t read_pending; - uint32_t read_complete; - } *sync; }; #define to_omap_bo(x) container_of(x, struct omap_gem_object, base) @@ -132,7 +119,7 @@ struct omap_gem_object { #define NUM_USERGART_ENTRIES 2 struct omap_drm_usergart_entry { struct tiler_block *block; /* the reserved tiler block */ - dma_addr_t paddr; + dma_addr_t dma_addr; struct drm_gem_object *obj; /* the current pinned obj */ pgoff_t obj_pgoff; /* page offset of obj currently mapped in */ @@ -195,7 +182,7 @@ static void evict_entry(struct drm_gem_object *obj, size_t size = PAGE_SIZE * n; loff_t off = mmap_offset(obj) + (entry->obj_pgoff << PAGE_SHIFT); - const int m = 1 + ((omap_obj->width << fmt) / PAGE_SIZE); + const int m = DIV_ROUND_UP(omap_obj->width << fmt, PAGE_SIZE); if (m > 1) { int i; @@ -267,7 +254,7 @@ static int omap_gem_attach_pages(struct drm_gem_object *obj) for (i = 0; i < npages; i++) { addrs[i] = dma_map_page(dev->dev, pages[i], - 0, PAGE_SIZE, DMA_BIDIRECTIONAL); + 0, PAGE_SIZE, DMA_TO_DEVICE); if (dma_mapping_error(dev->dev, addrs[i])) { dev_warn(dev->dev, @@ -275,7 +262,7 @@ static int omap_gem_attach_pages(struct drm_gem_object *obj) for (i = i - 1; i >= 0; --i) { dma_unmap_page(dev->dev, addrs[i], - PAGE_SIZE, DMA_BIDIRECTIONAL); + PAGE_SIZE, DMA_TO_DEVICE); } ret = -ENOMEM; @@ -290,7 +277,7 @@ static int omap_gem_attach_pages(struct drm_gem_object *obj) } } - omap_obj->addrs = addrs; + omap_obj->dma_addrs = addrs; omap_obj->pages = pages; return 0; @@ -329,22 +316,17 @@ static int get_pages(struct drm_gem_object *obj, struct page ***pages) static void omap_gem_detach_pages(struct drm_gem_object *obj) { struct omap_gem_object *omap_obj = to_omap_bo(obj); + unsigned int npages = obj->size >> PAGE_SHIFT; + unsigned int i; - /* for non-cached buffers, ensure the new pages are clean because - * DSS, GPU, etc. are not cache coherent: - */ - if (omap_obj->flags & (OMAP_BO_WC|OMAP_BO_UNCACHED)) { - int i, npages = obj->size >> PAGE_SHIFT; - for (i = 0; i < npages; i++) { - if (omap_obj->addrs[i]) - dma_unmap_page(obj->dev->dev, - omap_obj->addrs[i], - PAGE_SIZE, DMA_BIDIRECTIONAL); - } + for (i = 0; i < npages; i++) { + if (omap_obj->dma_addrs[i]) + dma_unmap_page(obj->dev->dev, omap_obj->dma_addrs[i], + PAGE_SIZE, DMA_TO_DEVICE); } - kfree(omap_obj->addrs); - omap_obj->addrs = NULL; + kfree(omap_obj->dma_addrs); + omap_obj->dma_addrs = NULL; drm_gem_put_pages(obj, omap_obj->pages, true, false); omap_obj->pages = NULL; @@ -401,11 +383,11 @@ static int fault_1d(struct drm_gem_object *obj, pgoff = (vmf->address - vma->vm_start) >> PAGE_SHIFT; if (omap_obj->pages) { - omap_gem_cpu_sync(obj, pgoff); + omap_gem_cpu_sync_page(obj, pgoff); pfn = page_to_pfn(omap_obj->pages[pgoff]); } else { BUG_ON(!is_contiguous(omap_obj)); - pfn = (omap_obj->paddr >> PAGE_SHIFT) + pgoff; + pfn = (omap_obj->dma_addr >> PAGE_SHIFT) + pgoff; } VERB("Inserting %p pfn %lx, pa %lx", (void *)vmf->address, @@ -442,7 +424,7 @@ static int fault_2d(struct drm_gem_object *obj, * into account in some of the math, so figure out virtual stride * in pages */ - const int m = 1 + ((omap_obj->width << fmt) / PAGE_SIZE); + const int m = DIV_ROUND_UP(omap_obj->width << fmt, PAGE_SIZE); /* We don't use vmf->pgoff since that has the fake offset: */ pgoff = (vmf->address - vma->vm_start) >> PAGE_SHIFT; @@ -498,7 +480,7 @@ static int fault_2d(struct drm_gem_object *obj, return ret; } - pfn = entry->paddr >> PAGE_SHIFT; + pfn = entry->dma_addr >> PAGE_SHIFT; VERB("Inserting %p pfn %lx, pa %lx", (void *)vmf->address, pfn, pfn << PAGE_SHIFT); @@ -732,77 +714,92 @@ fail: * Memory Management & DMA Sync */ -/** - * shmem buffers that are mapped cached can simulate coherency via using - * page faulting to keep track of dirty pages +/* + * shmem buffers that are mapped cached are not coherent. + * + * We keep track of dirty pages using page faulting to perform cache management. + * When a page is mapped to the CPU in read/write mode the device can't access + * it and omap_obj->dma_addrs[i] is NULL. When a page is mapped to the device + * the omap_obj->dma_addrs[i] is set to the DMA address, and the page is + * unmapped from the CPU. */ static inline bool is_cached_coherent(struct drm_gem_object *obj) { struct omap_gem_object *omap_obj = to_omap_bo(obj); - return (omap_obj->flags & OMAP_BO_MEM_SHMEM) && - ((omap_obj->flags & OMAP_BO_CACHE_MASK) == OMAP_BO_CACHED); + return !((omap_obj->flags & OMAP_BO_MEM_SHMEM) && + ((omap_obj->flags & OMAP_BO_CACHE_MASK) == OMAP_BO_CACHED)); } /* Sync the buffer for CPU access.. note pages should already be * attached, ie. omap_gem_get_pages() */ -void omap_gem_cpu_sync(struct drm_gem_object *obj, int pgoff) +void omap_gem_cpu_sync_page(struct drm_gem_object *obj, int pgoff) { struct drm_device *dev = obj->dev; struct omap_gem_object *omap_obj = to_omap_bo(obj); - if (is_cached_coherent(obj) && omap_obj->addrs[pgoff]) { - dma_unmap_page(dev->dev, omap_obj->addrs[pgoff], - PAGE_SIZE, DMA_BIDIRECTIONAL); - omap_obj->addrs[pgoff] = 0; + if (is_cached_coherent(obj)) + return; + + if (omap_obj->dma_addrs[pgoff]) { + dma_unmap_page(dev->dev, omap_obj->dma_addrs[pgoff], + PAGE_SIZE, DMA_TO_DEVICE); + omap_obj->dma_addrs[pgoff] = 0; } } /* sync the buffer for DMA access */ -void omap_gem_dma_sync(struct drm_gem_object *obj, +void omap_gem_dma_sync_buffer(struct drm_gem_object *obj, enum dma_data_direction dir) { struct drm_device *dev = obj->dev; struct omap_gem_object *omap_obj = to_omap_bo(obj); + int i, npages = obj->size >> PAGE_SHIFT; + struct page **pages = omap_obj->pages; + bool dirty = false; - if (is_cached_coherent(obj)) { - int i, npages = obj->size >> PAGE_SHIFT; - struct page **pages = omap_obj->pages; - bool dirty = false; - - for (i = 0; i < npages; i++) { - if (!omap_obj->addrs[i]) { - dma_addr_t addr; - - addr = dma_map_page(dev->dev, pages[i], 0, - PAGE_SIZE, DMA_BIDIRECTIONAL); + if (is_cached_coherent(obj)) + return; - if (dma_mapping_error(dev->dev, addr)) { - dev_warn(dev->dev, - "%s: failed to map page\n", - __func__); - break; - } + for (i = 0; i < npages; i++) { + if (!omap_obj->dma_addrs[i]) { + dma_addr_t addr; - dirty = true; - omap_obj->addrs[i] = addr; + addr = dma_map_page(dev->dev, pages[i], 0, + PAGE_SIZE, dir); + if (dma_mapping_error(dev->dev, addr)) { + dev_warn(dev->dev, "%s: failed to map page\n", + __func__); + break; } - } - if (dirty) { - unmap_mapping_range(obj->filp->f_mapping, 0, - omap_gem_mmap_size(obj), 1); + dirty = true; + omap_obj->dma_addrs[i] = addr; } } + + if (dirty) { + unmap_mapping_range(obj->filp->f_mapping, 0, + omap_gem_mmap_size(obj), 1); + } } -/* Get physical address for DMA.. if 'remap' is true, and the buffer is not - * already contiguous, remap it to pin in physically contiguous memory.. (ie. - * map in TILER) +/** + * omap_gem_pin() - Pin a GEM object in memory + * @obj: the GEM object + * @dma_addr: the DMA address + * + * Pin the given GEM object in memory and fill the dma_addr pointer with the + * object's DMA address. If the buffer is not physically contiguous it will be + * remapped through the TILER to provide a contiguous view. + * + * Pins are reference-counted, calling this function multiple times is allowed + * as long the corresponding omap_gem_unpin() calls are balanced. + * + * Return 0 on success or a negative error code otherwise. */ -int omap_gem_get_paddr(struct drm_gem_object *obj, - dma_addr_t *paddr, bool remap) +int omap_gem_pin(struct drm_gem_object *obj, dma_addr_t *dma_addr) { struct omap_drm_private *priv = obj->dev->dev_private; struct omap_gem_object *omap_obj = to_omap_bo(obj); @@ -810,8 +807,8 @@ int omap_gem_get_paddr(struct drm_gem_object *obj, mutex_lock(&obj->dev->struct_mutex); - if (!is_contiguous(omap_obj) && remap && priv->has_dmm) { - if (omap_obj->paddr_cnt == 0) { + if (!is_contiguous(omap_obj) && priv->has_dmm) { + if (omap_obj->dma_addr_cnt == 0) { struct page **pages; uint32_t npages = obj->size >> PAGE_SHIFT; enum tiler_fmt fmt = gem2fmt(omap_obj->flags); @@ -848,17 +845,17 @@ int omap_gem_get_paddr(struct drm_gem_object *obj, goto fail; } - omap_obj->paddr = tiler_ssptr(block); + omap_obj->dma_addr = tiler_ssptr(block); omap_obj->block = block; - DBG("got paddr: %pad", &omap_obj->paddr); + DBG("got dma address: %pad", &omap_obj->dma_addr); } - omap_obj->paddr_cnt++; + omap_obj->dma_addr_cnt++; - *paddr = omap_obj->paddr; + *dma_addr = omap_obj->dma_addr; } else if (is_contiguous(omap_obj)) { - *paddr = omap_obj->paddr; + *dma_addr = omap_obj->dma_addr; } else { ret = -EINVAL; goto fail; @@ -870,18 +867,23 @@ fail: return ret; } -/* Release physical address, when DMA is no longer being performed.. this - * could potentially unpin and unmap buffers from TILER +/** + * omap_gem_unpin() - Unpin a GEM object from memory + * @obj: the GEM object + * + * Unpin the given GEM object previously pinned with omap_gem_pin(). Pins are + * reference-counted, the actualy unpin will only be performed when the number + * of calls to this function matches the number of calls to omap_gem_pin(). */ -void omap_gem_put_paddr(struct drm_gem_object *obj) +void omap_gem_unpin(struct drm_gem_object *obj) { struct omap_gem_object *omap_obj = to_omap_bo(obj); int ret; mutex_lock(&obj->dev->struct_mutex); - if (omap_obj->paddr_cnt > 0) { - omap_obj->paddr_cnt--; - if (omap_obj->paddr_cnt == 0) { + if (omap_obj->dma_addr_cnt > 0) { + omap_obj->dma_addr_cnt--; + if (omap_obj->dma_addr_cnt == 0) { ret = tiler_unpin(omap_obj->block); if (ret) { dev_err(obj->dev->dev, @@ -892,7 +894,7 @@ void omap_gem_put_paddr(struct drm_gem_object *obj) dev_err(obj->dev->dev, "could not release unmap: %d\n", ret); } - omap_obj->paddr = 0; + omap_obj->dma_addr = 0; omap_obj->block = NULL; } } @@ -904,16 +906,16 @@ void omap_gem_put_paddr(struct drm_gem_object *obj) * specified orientation and x,y offset from top-left corner of buffer * (only valid for tiled 2d buffers) */ -int omap_gem_rotated_paddr(struct drm_gem_object *obj, uint32_t orient, - int x, int y, dma_addr_t *paddr) +int omap_gem_rotated_dma_addr(struct drm_gem_object *obj, uint32_t orient, + int x, int y, dma_addr_t *dma_addr) { struct omap_gem_object *omap_obj = to_omap_bo(obj); int ret = -EINVAL; mutex_lock(&obj->dev->struct_mutex); - if ((omap_obj->paddr_cnt > 0) && omap_obj->block && + if ((omap_obj->dma_addr_cnt > 0) && omap_obj->block && (omap_obj->flags & OMAP_BO_TILED)) { - *paddr = tiler_tsptr(omap_obj->block, orient, x, y); + *dma_addr = tiler_tsptr(omap_obj->block, orient, x, y); ret = 0; } mutex_unlock(&obj->dev->struct_mutex); @@ -934,9 +936,9 @@ int omap_gem_tiled_stride(struct drm_gem_object *obj, uint32_t orient) * increasing the pin count (which we don't really do yet anyways, * because we don't support swapping pages back out). And 'remap' * might not be quite the right name, but I wanted to keep it working - * similarly to omap_gem_get_paddr(). Note though that mutex is not + * similarly to omap_gem_pin(). Note though that mutex is not * aquired if !remap (because this can be called in atomic ctxt), - * but probably omap_gem_get_paddr() should be changed to work in the + * but probably omap_gem_unpin() should be changed to work in the * same way. If !remap, a matching omap_gem_put_pages() call is not * required (and should not be made). */ @@ -1034,7 +1036,7 @@ void omap_gem_describe(struct drm_gem_object *obj, struct seq_file *m) seq_printf(m, "%08x: %2d (%2d) %08llx %pad (%2d) %p %4d", omap_obj->flags, obj->name, kref_read(&obj->refcount), - off, &omap_obj->paddr, omap_obj->paddr_cnt, + off, &omap_obj->dma_addr, omap_obj->dma_addr_cnt, omap_obj->vaddr, omap_obj->roll); if (omap_obj->flags & OMAP_BO_TILED) { @@ -1046,7 +1048,7 @@ void omap_gem_describe(struct drm_gem_object *obj, struct seq_file *m) area->p1.x, area->p1.y); } } else { - seq_printf(m, " %d", obj->size); + seq_printf(m, " %zu", obj->size); } seq_printf(m, "\n"); @@ -1071,205 +1073,6 @@ void omap_gem_describe_objects(struct list_head *list, struct seq_file *m) #endif /* ----------------------------------------------------------------------------- - * Buffer Synchronization - */ - -static DEFINE_SPINLOCK(sync_lock); - -struct omap_gem_sync_waiter { - struct list_head list; - struct omap_gem_object *omap_obj; - enum omap_gem_op op; - uint32_t read_target, write_target; - /* notify called w/ sync_lock held */ - void (*notify)(void *arg); - void *arg; -}; - -/* list of omap_gem_sync_waiter.. the notify fxn gets called back when - * the read and/or write target count is achieved which can call a user - * callback (ex. to kick 3d and/or 2d), wakeup blocked task (prep for - * cpu access), etc. - */ -static LIST_HEAD(waiters); - -static inline bool is_waiting(struct omap_gem_sync_waiter *waiter) -{ - struct omap_gem_object *omap_obj = waiter->omap_obj; - if ((waiter->op & OMAP_GEM_READ) && - (omap_obj->sync->write_complete < waiter->write_target)) - return true; - if ((waiter->op & OMAP_GEM_WRITE) && - (omap_obj->sync->read_complete < waiter->read_target)) - return true; - return false; -} - -/* macro for sync debug.. */ -#define SYNCDBG 0 -#define SYNC(fmt, ...) do { if (SYNCDBG) \ - pr_err("%s:%d: " fmt "\n", __func__, __LINE__, ##__VA_ARGS__); \ - } while (0) - - -static void sync_op_update(void) -{ - struct omap_gem_sync_waiter *waiter, *n; - list_for_each_entry_safe(waiter, n, &waiters, list) { - if (!is_waiting(waiter)) { - list_del(&waiter->list); - SYNC("notify: %p", waiter); - waiter->notify(waiter->arg); - kfree(waiter); - } - } -} - -static inline int sync_op(struct drm_gem_object *obj, - enum omap_gem_op op, bool start) -{ - struct omap_gem_object *omap_obj = to_omap_bo(obj); - int ret = 0; - - spin_lock(&sync_lock); - - if (!omap_obj->sync) { - omap_obj->sync = kzalloc(sizeof(*omap_obj->sync), GFP_ATOMIC); - if (!omap_obj->sync) { - ret = -ENOMEM; - goto unlock; - } - } - - if (start) { - if (op & OMAP_GEM_READ) - omap_obj->sync->read_pending++; - if (op & OMAP_GEM_WRITE) - omap_obj->sync->write_pending++; - } else { - if (op & OMAP_GEM_READ) - omap_obj->sync->read_complete++; - if (op & OMAP_GEM_WRITE) - omap_obj->sync->write_complete++; - sync_op_update(); - } - -unlock: - spin_unlock(&sync_lock); - - return ret; -} - -/* mark the start of read and/or write operation */ -int omap_gem_op_start(struct drm_gem_object *obj, enum omap_gem_op op) -{ - return sync_op(obj, op, true); -} - -int omap_gem_op_finish(struct drm_gem_object *obj, enum omap_gem_op op) -{ - return sync_op(obj, op, false); -} - -static DECLARE_WAIT_QUEUE_HEAD(sync_event); - -static void sync_notify(void *arg) -{ - struct task_struct **waiter_task = arg; - *waiter_task = NULL; - wake_up_all(&sync_event); -} - -int omap_gem_op_sync(struct drm_gem_object *obj, enum omap_gem_op op) -{ - struct omap_gem_object *omap_obj = to_omap_bo(obj); - int ret = 0; - if (omap_obj->sync) { - struct task_struct *waiter_task = current; - struct omap_gem_sync_waiter *waiter = - kzalloc(sizeof(*waiter), GFP_KERNEL); - - if (!waiter) - return -ENOMEM; - - waiter->omap_obj = omap_obj; - waiter->op = op; - waiter->read_target = omap_obj->sync->read_pending; - waiter->write_target = omap_obj->sync->write_pending; - waiter->notify = sync_notify; - waiter->arg = &waiter_task; - - spin_lock(&sync_lock); - if (is_waiting(waiter)) { - SYNC("waited: %p", waiter); - list_add_tail(&waiter->list, &waiters); - spin_unlock(&sync_lock); - ret = wait_event_interruptible(sync_event, - (waiter_task == NULL)); - spin_lock(&sync_lock); - if (waiter_task) { - SYNC("interrupted: %p", waiter); - /* we were interrupted */ - list_del(&waiter->list); - waiter_task = NULL; - } else { - /* freed in sync_op_update() */ - waiter = NULL; - } - } - spin_unlock(&sync_lock); - kfree(waiter); - } - return ret; -} - -/* call fxn(arg), either synchronously or asynchronously if the op - * is currently blocked.. fxn() can be called from any context - * - * (TODO for now fxn is called back from whichever context calls - * omap_gem_op_finish().. but this could be better defined later - * if needed) - * - * TODO more code in common w/ _sync().. - */ -int omap_gem_op_async(struct drm_gem_object *obj, enum omap_gem_op op, - void (*fxn)(void *arg), void *arg) -{ - struct omap_gem_object *omap_obj = to_omap_bo(obj); - if (omap_obj->sync) { - struct omap_gem_sync_waiter *waiter = - kzalloc(sizeof(*waiter), GFP_ATOMIC); - - if (!waiter) - return -ENOMEM; - - waiter->omap_obj = omap_obj; - waiter->op = op; - waiter->read_target = omap_obj->sync->read_pending; - waiter->write_target = omap_obj->sync->write_pending; - waiter->notify = fxn; - waiter->arg = arg; - - spin_lock(&sync_lock); - if (is_waiting(waiter)) { - SYNC("waited: %p", waiter); - list_add_tail(&waiter->list, &waiters); - spin_unlock(&sync_lock); - return 0; - } - - spin_unlock(&sync_lock); - - kfree(waiter); - } - - /* no waiting.. */ - fxn(arg); - - return 0; -} - -/* ----------------------------------------------------------------------------- * Constructor & Destructor */ @@ -1290,7 +1093,7 @@ void omap_gem_free_object(struct drm_gem_object *obj) /* this means the object is still pinned.. which really should * not happen. I think.. */ - WARN_ON(omap_obj->paddr_cnt > 0); + WARN_ON(omap_obj->dma_addr_cnt > 0); if (omap_obj->pages) { if (omap_obj->flags & OMAP_BO_MEM_DMABUF) @@ -1301,15 +1104,13 @@ void omap_gem_free_object(struct drm_gem_object *obj) if (omap_obj->flags & OMAP_BO_MEM_DMA_API) { dma_free_wc(dev->dev, obj->size, omap_obj->vaddr, - omap_obj->paddr); + omap_obj->dma_addr); } else if (omap_obj->vaddr) { vunmap(omap_obj->vaddr); } else if (obj->import_attach) { drm_prime_gem_destroy(obj, omap_obj->sgt); } - kfree(omap_obj->sync); - drm_gem_object_release(obj); kfree(omap_obj); @@ -1400,7 +1201,7 @@ struct drm_gem_object *omap_gem_new(struct drm_device *dev, /* Allocate memory if needed. */ if (flags & OMAP_BO_MEM_DMA_API) { omap_obj->vaddr = dma_alloc_wc(dev->dev, size, - &omap_obj->paddr, + &omap_obj->dma_addr, GFP_KERNEL); if (!omap_obj->vaddr) goto err_release; @@ -1444,7 +1245,7 @@ struct drm_gem_object *omap_gem_new_dmabuf(struct drm_device *dev, size_t size, omap_obj->sgt = sgt; if (sgt->orig_nents == 1) { - omap_obj->paddr = sg_dma_address(sgt->sgl); + omap_obj->dma_addr = sg_dma_address(sgt->sgl); } else { /* Create pages list from sgt */ struct sg_page_iter iter; @@ -1551,11 +1352,11 @@ void omap_gem_init(struct drm_device *dev) i, j, PTR_ERR(block)); return; } - entry->paddr = tiler_ssptr(block); + entry->dma_addr = tiler_ssptr(block); entry->block = block; - DBG("%d:%d: %dx%d: paddr=%pad stride=%d", i, j, w, h, - &entry->paddr, + DBG("%d:%d: %dx%d: dma_addr=%pad stride=%d", i, j, w, h, + &entry->dma_addr, usergart[i].stride_pfn << PAGE_SHIFT); } } diff --git a/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c b/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c index 0dbe0306953d..afdbad5c866a 100644 --- a/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c +++ b/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c @@ -31,7 +31,7 @@ static struct sg_table *omap_gem_map_dma_buf( { struct drm_gem_object *obj = attachment->dmabuf->priv; struct sg_table *sg; - dma_addr_t paddr; + dma_addr_t dma_addr; int ret; sg = kzalloc(sizeof(*sg), GFP_KERNEL); @@ -41,7 +41,7 @@ static struct sg_table *omap_gem_map_dma_buf( /* camera, etc, need physically contiguous.. but we need a * better way to know this.. */ - ret = omap_gem_get_paddr(obj, &paddr, true); + ret = omap_gem_pin(obj, &dma_addr); if (ret) goto out; @@ -51,11 +51,11 @@ static struct sg_table *omap_gem_map_dma_buf( sg_init_table(sg->sgl, 1); sg_dma_len(sg->sgl) = obj->size; - sg_set_page(sg->sgl, pfn_to_page(PFN_DOWN(paddr)), obj->size, 0); - sg_dma_address(sg->sgl) = paddr; + sg_set_page(sg->sgl, pfn_to_page(PFN_DOWN(dma_addr)), obj->size, 0); + sg_dma_address(sg->sgl) = dma_addr; - /* this should be after _get_paddr() to ensure we have pages attached */ - omap_gem_dma_sync(obj, dir); + /* this must be after omap_gem_pin() to ensure we have pages attached */ + omap_gem_dma_sync_buffer(obj, dir); return sg; out: @@ -67,21 +67,11 @@ static void omap_gem_unmap_dma_buf(struct dma_buf_attachment *attachment, struct sg_table *sg, enum dma_data_direction dir) { struct drm_gem_object *obj = attachment->dmabuf->priv; - omap_gem_put_paddr(obj); + omap_gem_unpin(obj); sg_free_table(sg); kfree(sg); } -static void omap_gem_dmabuf_release(struct dma_buf *buffer) -{ - struct drm_gem_object *obj = buffer->priv; - /* release reference that was taken when dmabuf was exported - * in omap_gem_prime_set().. - */ - drm_gem_object_unreference_unlocked(obj); -} - - static int omap_gem_dmabuf_begin_cpu_access(struct dma_buf *buffer, enum dma_data_direction dir) { @@ -112,7 +102,7 @@ static void *omap_gem_dmabuf_kmap_atomic(struct dma_buf *buffer, struct drm_gem_object *obj = buffer->priv; struct page **pages; omap_gem_get_pages(obj, &pages, false); - omap_gem_cpu_sync(obj, page_num); + omap_gem_cpu_sync_page(obj, page_num); return kmap_atomic(pages[page_num]); } @@ -128,7 +118,7 @@ static void *omap_gem_dmabuf_kmap(struct dma_buf *buffer, struct drm_gem_object *obj = buffer->priv; struct page **pages; omap_gem_get_pages(obj, &pages, false); - omap_gem_cpu_sync(obj, page_num); + omap_gem_cpu_sync_page(obj, page_num); return kmap(pages[page_num]); } @@ -154,10 +144,10 @@ static int omap_gem_dmabuf_mmap(struct dma_buf *buffer, return omap_gem_mmap_obj(obj, vma); } -static struct dma_buf_ops omap_dmabuf_ops = { +static const struct dma_buf_ops omap_dmabuf_ops = { .map_dma_buf = omap_gem_map_dma_buf, .unmap_dma_buf = omap_gem_unmap_dma_buf, - .release = omap_gem_dmabuf_release, + .release = drm_gem_dmabuf_release, .begin_cpu_access = omap_gem_dmabuf_begin_cpu_access, .end_cpu_access = omap_gem_dmabuf_end_cpu_access, .map_atomic = omap_gem_dmabuf_kmap_atomic, @@ -177,7 +167,7 @@ struct dma_buf *omap_gem_prime_export(struct drm_device *dev, exp_info.flags = flags; exp_info.priv = obj; - return dma_buf_export(&exp_info); + return drm_gem_dmabuf_export(dev, &exp_info); } /* ----------------------------------------------------------------------------- @@ -210,7 +200,7 @@ struct drm_gem_object *omap_gem_prime_import(struct drm_device *dev, get_dma_buf(dma_buf); - sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); + sgt = dma_buf_map_attachment(attach, DMA_TO_DEVICE); if (IS_ERR(sgt)) { ret = PTR_ERR(sgt); goto fail_detach; @@ -227,7 +217,7 @@ struct drm_gem_object *omap_gem_prime_import(struct drm_device *dev, return obj; fail_unmap: - dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL); + dma_buf_unmap_attachment(attach, sgt, DMA_TO_DEVICE); fail_detach: dma_buf_detach(dma_buf, attach); dma_buf_put(dma_buf); diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index 115104cdcc59..013b0bba712f 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -41,7 +41,6 @@ static void omap_irq_update(struct drm_device *dev) DBG("irqmask=%08x", irqmask); priv->dispc_ops->write_irqenable(irqmask); - priv->dispc_ops->read_irqenable(); /* flush posted write */ } static void omap_irq_wait_handler(struct omap_irq_wait *wait) @@ -183,12 +182,13 @@ static void omap_irq_fifo_underflow(struct omap_drm_private *priv, pr_cont("(0x%08x)\n", irqstatus); } -static void omap_irq_ocp_error_handler(u32 irqstatus) +static void omap_irq_ocp_error_handler(struct drm_device *dev, + u32 irqstatus) { if (!(irqstatus & DISPC_IRQ_OCP_ERR)) return; - DRM_ERROR("OCP error\n"); + dev_err_ratelimited(dev->dev, "OCP error\n"); } static irqreturn_t omap_irq_handler(int irq, void *arg) @@ -219,7 +219,7 @@ static irqreturn_t omap_irq_handler(int irq, void *arg) omap_crtc_error_irq(crtc, irqstatus); } - omap_irq_ocp_error_handler(irqstatus); + omap_irq_ocp_error_handler(dev, irqstatus); omap_irq_fifo_underflow(priv, irqstatus); spin_lock_irqsave(&priv->wait_lock, flags); diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 9168154d749e..15e5d5d325c6 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -34,23 +34,8 @@ struct omap_plane { struct drm_plane base; enum omap_plane_id id; const char *name; - - uint32_t nformats; - uint32_t formats[32]; -}; - -struct omap_plane_state { - struct drm_plane_state base; - - unsigned int zorder; }; -static inline struct omap_plane_state * -to_omap_plane_state(struct drm_plane_state *state) -{ - return container_of(state, struct omap_plane_state, base); -} - static int omap_plane_prepare_fb(struct drm_plane *plane, struct drm_plane_state *new_state) { @@ -73,44 +58,19 @@ static void omap_plane_atomic_update(struct drm_plane *plane, struct omap_drm_private *priv = plane->dev->dev_private; struct omap_plane *omap_plane = to_omap_plane(plane); struct drm_plane_state *state = plane->state; - struct omap_plane_state *omap_state = to_omap_plane_state(state); struct omap_overlay_info info; - struct omap_drm_window win; int ret; DBG("%s, crtc=%p fb=%p", omap_plane->name, state->crtc, state->fb); memset(&info, 0, sizeof(info)); - info.rotation_type = OMAP_DSS_ROT_DMA; - info.rotation = OMAP_DSS_ROT_0; + info.rotation_type = OMAP_DSS_ROT_NONE; + info.rotation = DRM_MODE_ROTATE_0; info.global_alpha = 0xff; - info.mirror = 0; - info.zorder = omap_state->zorder; - - memset(&win, 0, sizeof(win)); - win.rotation = state->rotation; - win.crtc_x = state->crtc_x; - win.crtc_y = state->crtc_y; - win.crtc_w = state->crtc_w; - win.crtc_h = state->crtc_h; - - /* - * src values are in Q16 fixed point, convert to integer. - * omap_framebuffer_update_scanout() takes adjusted src. - */ - win.src_x = state->src_x >> 16; - win.src_y = state->src_y >> 16; - - if (drm_rotation_90_or_270(state->rotation)) { - win.src_w = state->src_h >> 16; - win.src_h = state->src_w >> 16; - } else { - win.src_w = state->src_w >> 16; - win.src_h = state->src_h >> 16; - } + info.zorder = state->zpos; /* update scanout: */ - omap_framebuffer_update_scanout(state->fb, &win, &info); + omap_framebuffer_update_scanout(state->fb, state, &info); DBG("%dx%d -> %dx%d (%d)", info.width, info.height, info.out_width, info.out_height, @@ -118,12 +78,10 @@ static void omap_plane_atomic_update(struct drm_plane *plane, DBG("%d,%d %pad %pad", info.pos_x, info.pos_y, &info.paddr, &info.p_uv_addr); - priv->dispc_ops->ovl_set_channel_out(omap_plane->id, - omap_crtc_channel(state->crtc)); - /* and finally, update omapdss: */ ret = priv->dispc_ops->ovl_setup(omap_plane->id, &info, - omap_crtc_timings(state->crtc), false); + omap_crtc_timings(state->crtc), false, + omap_crtc_channel(state->crtc)); if (ret) { dev_err(plane->dev->dev, "Failed to setup plane %s\n", omap_plane->name); @@ -138,11 +96,10 @@ static void omap_plane_atomic_disable(struct drm_plane *plane, struct drm_plane_state *old_state) { struct omap_drm_private *priv = plane->dev->dev_private; - struct omap_plane_state *omap_state = to_omap_plane_state(plane->state); struct omap_plane *omap_plane = to_omap_plane(plane); - plane->state->rotation = DRM_ROTATE_0; - omap_state->zorder = plane->type == DRM_PLANE_TYPE_PRIMARY + plane->state->rotation = DRM_MODE_ROTATE_0; + plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : omap_plane->id; priv->dispc_ops->ovl_enable(omap_plane->id, false); @@ -177,7 +134,7 @@ static int omap_plane_atomic_check(struct drm_plane *plane, if (state->crtc_y + state->crtc_h > crtc_state->adjusted_mode.vdisplay) return -EINVAL; - if (state->rotation != DRM_ROTATE_0 && + if (state->rotation != DRM_MODE_ROTATE_0 && !omap_framebuffer_supports_rotation(state->fb)) return -EINVAL; @@ -213,70 +170,34 @@ void omap_plane_install_properties(struct drm_plane *plane, if (priv->has_dmm) { if (!plane->rotation_property) drm_plane_create_rotation_property(plane, - DRM_ROTATE_0, - DRM_ROTATE_0 | DRM_ROTATE_90 | - DRM_ROTATE_180 | DRM_ROTATE_270 | - DRM_REFLECT_X | DRM_REFLECT_Y); + DRM_MODE_ROTATE_0, + DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | + DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y); /* Attach the rotation property also to the crtc object */ if (plane->rotation_property && obj != &plane->base) drm_object_attach_property(obj, plane->rotation_property, - DRM_ROTATE_0); + DRM_MODE_ROTATE_0); } drm_object_attach_property(obj, priv->zorder_prop, 0); } -static struct drm_plane_state * -omap_plane_atomic_duplicate_state(struct drm_plane *plane) -{ - struct omap_plane_state *state; - struct omap_plane_state *copy; - - if (WARN_ON(!plane->state)) - return NULL; - - state = to_omap_plane_state(plane->state); - copy = kmemdup(state, sizeof(*state), GFP_KERNEL); - if (copy == NULL) - return NULL; - - __drm_atomic_helper_plane_duplicate_state(plane, ©->base); - - return ©->base; -} - -static void omap_plane_atomic_destroy_state(struct drm_plane *plane, - struct drm_plane_state *state) -{ - __drm_atomic_helper_plane_destroy_state(state); - kfree(to_omap_plane_state(state)); -} - static void omap_plane_reset(struct drm_plane *plane) { struct omap_plane *omap_plane = to_omap_plane(plane); - struct omap_plane_state *omap_state; - if (plane->state) { - omap_plane_atomic_destroy_state(plane, plane->state); - plane->state = NULL; - } - - omap_state = kzalloc(sizeof(*omap_state), GFP_KERNEL); - if (omap_state == NULL) + drm_atomic_helper_plane_reset(plane); + if (!plane->state) return; /* - * Set defaults depending on whether we are a primary or overlay + * Set the zpos default depending on whether we are a primary or overlay * plane. */ - omap_state->zorder = plane->type == DRM_PLANE_TYPE_PRIMARY + plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : omap_plane->id; - omap_state->base.rotation = DRM_ROTATE_0; - - plane->state = &omap_state->base; - plane->state->plane = plane; } static int omap_plane_atomic_set_property(struct drm_plane *plane, @@ -285,10 +206,9 @@ static int omap_plane_atomic_set_property(struct drm_plane *plane, uint64_t val) { struct omap_drm_private *priv = plane->dev->dev_private; - struct omap_plane_state *omap_state = to_omap_plane_state(state); if (property == priv->zorder_prop) - omap_state->zorder = val; + state->zpos = val; else return -EINVAL; @@ -301,11 +221,9 @@ static int omap_plane_atomic_get_property(struct drm_plane *plane, uint64_t *val) { struct omap_drm_private *priv = plane->dev->dev_private; - const struct omap_plane_state *omap_state = - container_of(state, const struct omap_plane_state, base); if (property == priv->zorder_prop) - *val = omap_state->zorder; + *val = state->zpos; else return -EINVAL; @@ -317,9 +235,8 @@ static const struct drm_plane_funcs omap_plane_funcs = { .disable_plane = drm_atomic_helper_disable_plane, .reset = omap_plane_reset, .destroy = omap_plane_destroy, - .set_property = drm_atomic_helper_plane_set_property, - .atomic_duplicate_state = omap_plane_atomic_duplicate_state, - .atomic_destroy_state = omap_plane_atomic_destroy_state, + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, .atomic_set_property = omap_plane_atomic_set_property, .atomic_get_property = omap_plane_atomic_get_property, }; @@ -344,10 +261,13 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, u32 possible_crtcs) { struct omap_drm_private *priv = dev->dev_private; + unsigned int num_planes = priv->dispc_ops->get_num_ovls(); struct drm_plane *plane; struct omap_plane *omap_plane; enum omap_plane_id id; int ret; + u32 nformats; + const u32 *formats; if (WARN_ON(idx >= ARRAY_SIZE(plane_idx_to_id))) return ERR_PTR(-EINVAL); @@ -360,23 +280,24 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, if (!omap_plane) return ERR_PTR(-ENOMEM); - omap_plane->nformats = omap_framebuffer_get_formats( - omap_plane->formats, ARRAY_SIZE(omap_plane->formats), - priv->dispc_ops->ovl_get_color_modes(id)); + formats = priv->dispc_ops->ovl_get_color_modes(id); + for (nformats = 0; formats[nformats]; ++nformats) + ; omap_plane->id = id; omap_plane->name = plane_id_to_name[id]; plane = &omap_plane->base; ret = drm_universal_plane_init(dev, plane, possible_crtcs, - &omap_plane_funcs, omap_plane->formats, - omap_plane->nformats, type, NULL); + &omap_plane_funcs, formats, + nformats, NULL, type, NULL); if (ret < 0) goto error; drm_plane_helper_add(plane, &omap_plane_helper_funcs); omap_plane_install_properties(plane, &plane->base); + drm_plane_create_zpos_property(plane, 0, 0, num_planes - 1); return plane; |