diff options
Diffstat (limited to 'drivers/net/ethernet/mscc')
| -rw-r--r-- | drivers/net/ethernet/mscc/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/mscc/ocelot.c | 24 | ||||
| -rw-r--r-- | drivers/net/ethernet/mscc/ocelot.h | 79 | ||||
| -rw-r--r-- | drivers/net/ethernet/mscc/ocelot_board.c | 75 | ||||
| -rw-r--r-- | drivers/net/ethernet/mscc/ocelot_dev_gmii.h | 154 | ||||
| -rw-r--r-- | drivers/net/ethernet/mscc/ocelot_hsio.h | 785 | ||||
| -rw-r--r-- | drivers/net/ethernet/mscc/ocelot_regs.c | 93 |
7 files changed, 97 insertions, 1115 deletions
diff --git a/drivers/net/ethernet/mscc/Kconfig b/drivers/net/ethernet/mscc/Kconfig index 36c84625d54e..bcec0587cf61 100644 --- a/drivers/net/ethernet/mscc/Kconfig +++ b/drivers/net/ethernet/mscc/Kconfig @@ -23,6 +23,8 @@ config MSCC_OCELOT_SWITCH config MSCC_OCELOT_SWITCH_OCELOT tristate "Ocelot switch driver on Ocelot" depends on MSCC_OCELOT_SWITCH + depends on GENERIC_PHY + depends on OF_NET help This driver supports the Ocelot network switch device as present on the Ocelot SoCs. diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 1a4f2bb48ead..3238b9ee42f3 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -133,9 +133,9 @@ static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) { unsigned int val, timeout = 10; - /* Wait for the issued mac table command to be completed, or timeout. - * When the command read from ANA_TABLES_MACACCESS is - * MACACCESS_CMD_IDLE, the issued command completed successfully. + /* Wait for the issued vlan table command to be completed, or timeout. + * When the command read from ANA_TABLES_VLANACCESS is + * VLANACCESS_CMD_IDLE, the issued command completed successfully. */ do { val = ocelot_read(ocelot, ANA_TABLES_VLANACCESS); @@ -472,6 +472,7 @@ static int ocelot_port_open(struct net_device *dev) { struct ocelot_port *port = netdev_priv(dev); struct ocelot *ocelot = port->ocelot; + enum phy_mode phy_mode; int err; /* Enable receiving frames on the port, and activate auto-learning of @@ -482,8 +483,21 @@ static int ocelot_port_open(struct net_device *dev) ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), ANA_PORT_PORT_CFG, port->chip_port); + if (port->serdes) { + if (port->phy_mode == PHY_INTERFACE_MODE_SGMII) + phy_mode = PHY_MODE_SGMII; + else + phy_mode = PHY_MODE_QSGMII; + + err = phy_set_mode(port->serdes, phy_mode); + if (err) { + netdev_err(dev, "Could not set mode of SerDes\n"); + return err; + } + } + err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, - PHY_INTERFACE_MODE_NA); + port->phy_mode); if (err) { netdev_err(dev, "Could not attach to PHY\n"); return err; @@ -1606,7 +1620,7 @@ int ocelot_probe_port(struct ocelot *ocelot, u8 port, dev->ethtool_ops = &ocelot_ethtool_ops; dev->switchdev_ops = &ocelot_port_switchdev_ops; - dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; + dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS; dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h index 616bec30dfa3..62c7c8eb00d9 100644 --- a/drivers/net/ethernet/mscc/ocelot.h +++ b/drivers/net/ethernet/mscc/ocelot.h @@ -11,12 +11,13 @@ #include <linux/bitops.h> #include <linux/etherdevice.h> #include <linux/if_vlan.h> +#include <linux/phy.h> +#include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include "ocelot_ana.h" #include "ocelot_dev.h" -#include "ocelot_hsio.h" #include "ocelot_qsys.h" #include "ocelot_rew.h" #include "ocelot_sys.h" @@ -333,79 +334,6 @@ enum ocelot_reg { SYS_CM_DATA_RD, SYS_CM_OP, SYS_CM_DATA, - HSIO_PLL5G_CFG0 = HSIO << TARGET_OFFSET, - HSIO_PLL5G_CFG1, - HSIO_PLL5G_CFG2, - HSIO_PLL5G_CFG3, - HSIO_PLL5G_CFG4, - HSIO_PLL5G_CFG5, - HSIO_PLL5G_CFG6, - HSIO_PLL5G_STATUS0, - HSIO_PLL5G_STATUS1, - HSIO_PLL5G_BIST_CFG0, - HSIO_PLL5G_BIST_CFG1, - HSIO_PLL5G_BIST_CFG2, - HSIO_PLL5G_BIST_STAT0, - HSIO_PLL5G_BIST_STAT1, - HSIO_RCOMP_CFG0, - HSIO_RCOMP_STATUS, - HSIO_SYNC_ETH_CFG, - HSIO_SYNC_ETH_PLL_CFG, - HSIO_S1G_DES_CFG, - HSIO_S1G_IB_CFG, - HSIO_S1G_OB_CFG, - HSIO_S1G_SER_CFG, - HSIO_S1G_COMMON_CFG, - HSIO_S1G_PLL_CFG, - HSIO_S1G_PLL_STATUS, - HSIO_S1G_DFT_CFG0, - HSIO_S1G_DFT_CFG1, - HSIO_S1G_DFT_CFG2, - HSIO_S1G_TP_CFG, - HSIO_S1G_RC_PLL_BIST_CFG, - HSIO_S1G_MISC_CFG, - HSIO_S1G_DFT_STATUS, - HSIO_S1G_MISC_STATUS, - HSIO_MCB_S1G_ADDR_CFG, - HSIO_S6G_DIG_CFG, - HSIO_S6G_DFT_CFG0, - HSIO_S6G_DFT_CFG1, - HSIO_S6G_DFT_CFG2, - HSIO_S6G_TP_CFG0, - HSIO_S6G_TP_CFG1, - HSIO_S6G_RC_PLL_BIST_CFG, - HSIO_S6G_MISC_CFG, - HSIO_S6G_OB_ANEG_CFG, - HSIO_S6G_DFT_STATUS, - HSIO_S6G_ERR_CNT, - HSIO_S6G_MISC_STATUS, - HSIO_S6G_DES_CFG, - HSIO_S6G_IB_CFG, - HSIO_S6G_IB_CFG1, - HSIO_S6G_IB_CFG2, - HSIO_S6G_IB_CFG3, - HSIO_S6G_IB_CFG4, - HSIO_S6G_IB_CFG5, - HSIO_S6G_OB_CFG, - HSIO_S6G_OB_CFG1, - HSIO_S6G_SER_CFG, - HSIO_S6G_COMMON_CFG, - HSIO_S6G_PLL_CFG, - HSIO_S6G_ACJTAG_CFG, - HSIO_S6G_GP_CFG, - HSIO_S6G_IB_STATUS0, - HSIO_S6G_IB_STATUS1, - HSIO_S6G_ACJTAG_STATUS, - HSIO_S6G_PLL_STATUS, - HSIO_S6G_REVID, - HSIO_MCB_S6G_ADDR_CFG, - HSIO_HW_CFG, - HSIO_HW_QSGMII_CFG, - HSIO_HW_QSGMII_STAT, - HSIO_CLK_CFG, - HSIO_TEMP_SENSOR_CTRL, - HSIO_TEMP_SENSOR_CFG, - HSIO_TEMP_SENSOR_STAT, }; enum ocelot_regfield { @@ -527,6 +455,9 @@ struct ocelot_port { u8 vlan_aware; u64 *stats; + + phy_interface_t phy_mode; + struct phy *serdes; }; u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c index 26bb3b18f3be..4c23d18bbf44 100644 --- a/drivers/net/ethernet/mscc/ocelot_board.c +++ b/drivers/net/ethernet/mscc/ocelot_board.c @@ -6,9 +6,11 @@ */ #include <linux/interrupt.h> #include <linux/module.h> +#include <linux/of_net.h> #include <linux/netdevice.h> #include <linux/of_mdio.h> #include <linux/of_platform.h> +#include <linux/mfd/syscon.h> #include <linux/skbuff.h> #include "ocelot.h" @@ -91,7 +93,7 @@ static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) struct sk_buff *skb; struct net_device *dev; u32 *buf; - int sz, len; + int sz, len, buf_len; u32 ifh[4]; u32 val; struct frame_info info; @@ -116,14 +118,25 @@ static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) err = -ENOMEM; break; } - buf = (u32 *)skb_put(skb, info.len); + buf_len = info.len - ETH_FCS_LEN; + buf = (u32 *)skb_put(skb, buf_len); len = 0; do { sz = ocelot_rx_frame_word(ocelot, grp, false, &val); *buf++ = val; len += sz; - } while ((sz == 4) && (len < info.len)); + } while (len < buf_len); + + /* Read the FCS */ + sz = ocelot_rx_frame_word(ocelot, grp, false, &val); + /* Update the statistics if part of the FCS was read before */ + len -= ETH_FCS_LEN - sz; + + if (unlikely(dev->features & NETIF_F_RXFCS)) { + buf = (u32 *)skb_put(skb, ETH_FCS_LEN); + *buf = val; + } if (sz < 0) { err = sz; @@ -162,6 +175,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct device_node *ports, *portnp; struct ocelot *ocelot; + struct regmap *hsio; u32 val; struct { @@ -173,7 +187,6 @@ static int mscc_ocelot_probe(struct platform_device *pdev) { QSYS, "qsys" }, { ANA, "ana" }, { QS, "qs" }, - { HSIO, "hsio" }, }; if (!np && !pdev->dev.platform_data) @@ -196,6 +209,14 @@ static int mscc_ocelot_probe(struct platform_device *pdev) ocelot->targets[res[i].id] = target; } + hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); + if (IS_ERR(hsio)) { + dev_err(&pdev->dev, "missing hsio syscon\n"); + return PTR_ERR(hsio); + } + + ocelot->targets[HSIO] = hsio; + err = ocelot_chip_init(ocelot); if (err) return err; @@ -238,18 +259,11 @@ static int mscc_ocelot_probe(struct platform_device *pdev) INIT_LIST_HEAD(&ocelot->multicast); ocelot_init(ocelot); - ocelot_rmw(ocelot, HSIO_HW_CFG_DEV1G_4_MODE | - HSIO_HW_CFG_DEV1G_6_MODE | - HSIO_HW_CFG_DEV1G_9_MODE, - HSIO_HW_CFG_DEV1G_4_MODE | - HSIO_HW_CFG_DEV1G_6_MODE | - HSIO_HW_CFG_DEV1G_9_MODE, - HSIO_HW_CFG); - for_each_available_child_of_node(ports, portnp) { struct device_node *phy_node; struct phy_device *phy; struct resource *res; + struct phy *serdes; void __iomem *regs; char res_name[8]; u32 port; @@ -274,10 +288,43 @@ static int mscc_ocelot_probe(struct platform_device *pdev) continue; err = ocelot_probe_port(ocelot, port, regs, phy); - if (err) { - dev_err(&pdev->dev, "failed to probe ports\n"); + if (err) + return err; + + err = of_get_phy_mode(portnp); + if (err < 0) + ocelot->ports[port]->phy_mode = PHY_INTERFACE_MODE_NA; + else + ocelot->ports[port]->phy_mode = err; + + switch (ocelot->ports[port]->phy_mode) { + case PHY_INTERFACE_MODE_NA: + continue; + case PHY_INTERFACE_MODE_SGMII: + break; + case PHY_INTERFACE_MODE_QSGMII: + break; + default: + dev_err(ocelot->dev, + "invalid phy mode for port%d, (Q)SGMII only\n", + port); + return -EINVAL; + } + + serdes = devm_of_phy_get(ocelot->dev, portnp, NULL); + if (IS_ERR(serdes)) { + err = PTR_ERR(serdes); + if (err == -EPROBE_DEFER) + dev_dbg(ocelot->dev, "deferring probe\n"); + else + dev_err(ocelot->dev, + "missing SerDes phys for port%d\n", + port); + goto err_probe_ports; } + + ocelot->ports[port]->serdes = serdes; } register_netdevice_notifier(&ocelot_netdevice_nb); diff --git a/drivers/net/ethernet/mscc/ocelot_dev_gmii.h b/drivers/net/ethernet/mscc/ocelot_dev_gmii.h deleted file mode 100644 index 6aa40ea223a2..000000000000 --- a/drivers/net/ethernet/mscc/ocelot_dev_gmii.h +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Microsemi Ocelot Switch driver - * - * Copyright (c) 2017 Microsemi Corporation - */ - -#ifndef _MSCC_OCELOT_DEV_GMII_H_ -#define _MSCC_OCELOT_DEV_GMII_H_ - -#define DEV_GMII_PORT_MODE_CLOCK_CFG 0x0 - -#define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_TX_RST BIT(5) -#define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_RX_RST BIT(4) -#define DEV_GMII_PORT_MODE_CLOCK_CFG_PORT_RST BIT(3) -#define DEV_GMII_PORT_MODE_CLOCK_CFG_PHY_RST BIT(2) -#define DEV_GMII_PORT_MODE_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0)) -#define DEV_GMII_PORT_MODE_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0) - -#define DEV_GMII_PORT_MODE_PORT_MISC 0x4 - -#define DEV_GMII_PORT_MODE_PORT_MISC_MPLS_RX_ENA BIT(5) -#define DEV_GMII_PORT_MODE_PORT_MISC_FWD_ERROR_ENA BIT(4) -#define DEV_GMII_PORT_MODE_PORT_MISC_FWD_PAUSE_ENA BIT(3) -#define DEV_GMII_PORT_MODE_PORT_MISC_FWD_CTRL_ENA BIT(2) -#define DEV_GMII_PORT_MODE_PORT_MISC_GMII_LOOP_ENA BIT(1) -#define DEV_GMII_PORT_MODE_PORT_MISC_DEV_LOOP_ENA BIT(0) - -#define DEV_GMII_PORT_MODE_EVENTS 0x8 - -#define DEV_GMII_PORT_MODE_EEE_CFG 0xc - -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_ENA BIT(22) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15)) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8)) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1)) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1) -#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1) -#define DEV_GMII_PORT_MODE_EEE_CFG_PORT_LPI BIT(0) - -#define DEV_GMII_PORT_MODE_RX_PATH_DELAY 0x10 - -#define DEV_GMII_PORT_MODE_TX_PATH_DELAY 0x14 - -#define DEV_GMII_PORT_MODE_PTP_PREDICT_CFG 0x18 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_ENA_CFG 0x1c - -#define DEV_GMII_MAC_CFG_STATUS_MAC_ENA_CFG_RX_ENA BIT(4) -#define DEV_GMII_MAC_CFG_STATUS_MAC_ENA_CFG_TX_ENA BIT(0) - -#define DEV_GMII_MAC_CFG_STATUS_MAC_MODE_CFG 0x20 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) -#define DEV_GMII_MAC_CFG_STATUS_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) -#define DEV_GMII_MAC_CFG_STATUS_MAC_MODE_CFG_FDX_ENA BIT(0) - -#define DEV_GMII_MAC_CFG_STATUS_MAC_MAXLEN_CFG 0x24 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG 0x28 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16)) -#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16) -#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16) -#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_PB_ENA BIT(1) -#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) -#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2) - -#define DEV_GMII_MAC_CFG_STATUS_MAC_ADV_CHK_CFG 0x2c - -#define DEV_GMII_MAC_CFG_STATUS_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) - -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG 0x30 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8)) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4)) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0)) -#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0) - -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG 0x34 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_OB_ENA BIT(25) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_WEXC_DIS BIT(24) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16)) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_SEED_M GENMASK(23, 16) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_SEED_LOAD BIT(12) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0)) -#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0) - -#define DEV_GMII_MAC_CFG_STATUS_MAC_DBG_CFG 0x38 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_DBG_CFG_TBI_MODE BIT(4) -#define DEV_GMII_MAC_CFG_STATUS_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0) - -#define DEV_GMII_MAC_CFG_STATUS_MAC_FC_MAC_LOW_CFG 0x3c - -#define DEV_GMII_MAC_CFG_STATUS_MAC_FC_MAC_HIGH_CFG 0x40 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY 0x44 - -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_JUNK_STICKY BIT(5) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_JAM_STICKY BIT(3) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1) -#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_ABORT_STICKY BIT(0) - -#define DEV_GMII_MM_CONFIG_ENABLE_CONFIG 0x48 - -#define DEV_GMII_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA BIT(0) -#define DEV_GMII_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA BIT(4) -#define DEV_GMII_MM_CONFIG_ENABLE_CONFIG_KEEP_S_AFTER_D BIT(8) - -#define DEV_GMII_MM_CONFIG_VERIF_CONFIG 0x4c - -#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS BIT(0) -#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(x) (((x) << 4) & GENMASK(11, 4)) -#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M GENMASK(11, 4) -#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(x) (((x) & GENMASK(11, 4)) >> 4) -#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS(x) (((x) << 12) & GENMASK(13, 12)) -#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_M GENMASK(13, 12) -#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_X(x) (((x) & GENMASK(13, 12)) >> 12) - -#define DEV_GMII_MM_STATISTICS_MM_STATUS 0x50 - -#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_ACTIVE_STATUS BIT(0) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_ACTIVE_STICKY BIT(4) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_VERIFY_STATE(x) (((x) << 8) & GENMASK(10, 8)) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_VERIFY_STATE_M GENMASK(10, 8) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_VERIFY_STATE_X(x) (((x) & GENMASK(10, 8)) >> 8) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_UNEXP_RX_PFRM_STICKY BIT(12) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_UNEXP_TX_PFRM_STICKY BIT(16) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_MM_RX_FRAME_STATUS BIT(20) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_MM_TX_FRAME_STATUS BIT(24) -#define DEV_GMII_MM_STATISTICS_MM_STATUS_MM_TX_PRMPT_STATUS BIT(28) - -#endif diff --git a/drivers/net/ethernet/mscc/ocelot_hsio.h b/drivers/net/ethernet/mscc/ocelot_hsio.h deleted file mode 100644 index d93ddec3931b..000000000000 --- a/drivers/net/ethernet/mscc/ocelot_hsio.h +++ /dev/null @@ -1,785 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Microsemi Ocelot Switch driver - * - * Copyright (c) 2017 Microsemi Corporation - */ - -#ifndef _MSCC_OCELOT_HSIO_H_ -#define _MSCC_OCELOT_HSIO_H_ - -#define HSIO_PLL5G_CFG0_ENA_ROT BIT(31) -#define HSIO_PLL5G_CFG0_ENA_LANE BIT(30) -#define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29) -#define HSIO_PLL5G_CFG0_DIV4 BIT(28) -#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27) -#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23)) -#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23) -#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23) -#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18)) -#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18) -#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18) -#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) -#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16) -#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) -#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15) -#define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14) -#define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13) -#define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12) -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6)) -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6) -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6) -#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) -#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0) - -#define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18) -#define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17) -#define HSIO_PLL5G_CFG1_ROT_DIR BIT(16) -#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15) -#define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14) -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6) -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6) -#define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5) -#define HSIO_PLL5G_CFG1_PWD_TX BIT(4) -#define HSIO_PLL5G_CFG1_PWD_RX BIT(3) -#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2) -#define HSIO_PLL5G_CFG1_HALF_RATE BIT(1) -#define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0) - -#define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30) -#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29) -#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28) -#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27) -#define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26) -#define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25) -#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24) -#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16)) -#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16) -#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16) -#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15) -#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14) -#define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13) -#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12) -#define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11) -#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10) -#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5)) -#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5) -#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5) -#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4) -#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3) -#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2) -#define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1) -#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0) - -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22)) -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22) -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22) -#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19)) -#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19) -#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19) -#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18) -#define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17) -#define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16) -#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15) -#define HSIO_PLL5G_CFG3_RST_FB_N BIT(14) -#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13) -#define HSIO_PLL5G_CFG3_FORCE_LO BIT(12) -#define HSIO_PLL5G_CFG3_FORCE_HI BIT(11) -#define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10) -#define HSIO_PLL5G_CFG3_FORCE_CP BIT(9) -#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8) -#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0)) -#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0) - -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16)) -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16) -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16) -#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0)) -#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0) - -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16)) -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16) -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16) -#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0)) -#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0) - -#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23) -#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20)) -#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20) -#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20) -#define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19) -#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16)) -#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16) -#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16) -#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8)) -#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8) -#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8) -#define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7) -#define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6) -#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0)) -#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0) - -#define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12) -#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11) -#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10) -#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9) -#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1)) -#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1) -#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1) -#define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0) - -#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21)) -#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21) -#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21) -#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16)) -#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16) -#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16) -#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4)) -#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4) -#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4) -#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1)) -#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1) -#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1) -#define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0) - -#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31) -#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30) -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20)) -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20) -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20) -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16)) -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16) -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16) -#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0)) -#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0) - -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4)) -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4) -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2) -#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1) -#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0) - -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16)) -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16) -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16) -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0)) -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0) - -#define HSIO_RCOMP_CFG0_PWD_ENA BIT(13) -#define HSIO_RCOMP_CFG0_RUN_CAL BIT(12) -#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10)) -#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10) -#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10) -#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8)) -#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8) -#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8) -#define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4) -#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0)) -#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0) - -#define HSIO_RCOMP_STATUS_BUSY BIT(12) -#define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7) -#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0)) -#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0) - -#define HSIO_SYNC_ETH_CFG_RSZ 0x4 - -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4)) -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4) -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1)) -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1) -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1) -#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0) - -#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0) - -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13)) -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13) -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11)) -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11) -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11) -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8)) -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8) -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8) -#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5)) -#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5) -#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5) -#define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4) -#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1)) -#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1) -#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1) -#define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0) - -#define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27) -#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24)) -#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24) -#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24) -#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19)) -#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19) -#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19) -#define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14) -#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13) -#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12) -#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11) -#define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10) -#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9) -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6)) -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6) -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6) -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4)) -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4) -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4) -#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) -#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0) - -#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17)) -#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17) -#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17) -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13)) -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13) -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10)) -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10) -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10) -#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9) -#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8) -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4)) -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4) -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) -#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0) - -#define HSIO_S1G_SER_CFG_SER_IDLE BIT(9) -#define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8) -#define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7) -#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6) -#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4)) -#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4) -#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4) -#define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3) -#define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2) -#define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1) -#define HSIO_S1G_SER_CFG_SER_ENALI BIT(0) - -#define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31) -#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21) -#define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18) -#define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17) -#define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16) -#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13)) -#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13) -#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13) -#define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12) -#define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11) -#define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10) -#define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9) -#define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8) -#define HSIO_S1G_COMMON_CFG_HRATE BIT(7) -#define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0) - -#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22) -#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21) -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8)) -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8) -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8) -#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7) -#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6) -#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5) -#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3) - -#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12) -#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11) -#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10) -#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0)) -#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0) - -#define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31) -#define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23) -#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20)) -#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20) -#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20) -#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16)) -#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16) -#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16) -#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) -#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3) -#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2) -#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0) - -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8) -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4) -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3) -#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) -#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) -#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) - -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8) -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4) -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3) -#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) -#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) -#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) - -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16)) -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16) -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16) -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8)) -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8) -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8) -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0)) -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0) - -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11)) -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11) -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11) -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) -#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) -#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) -#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3) -#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2) -#define HSIO_S1G_MISC_CFG_LANE_RST BIT(0) - -#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) -#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6) -#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) -#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3) -#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2) -#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1) -#define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0) - -#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) - -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31) -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30) -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0)) -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0) - -#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16)) -#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16) -#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16) -#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7) -#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6) -#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3)) -#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3) -#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3) -#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0)) -#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0) - -#define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31) -#define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23) -#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20)) -#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20) -#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20) -#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16)) -#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16) -#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16) -#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) -#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3) -#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2) -#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0) - -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8) -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4) -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3) -#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) -#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) -#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) - -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8) -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4) -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3) -#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) -#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) -#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) - -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16)) -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16) -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16) -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8)) -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8) -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8) -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0)) -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0) - -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13)) -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13) -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13) -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11)) -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11) -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11) -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) -#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7) -#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6) -#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) -#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) -#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3) -#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2) -#define HSIO_S6G_MISC_CFG_LANE_RST BIT(0) - -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23)) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18)) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13)) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6)) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0)) -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0) - -#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8) -#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) -#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6) -#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) -#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3) -#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2) -#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1) -#define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0) - -#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) - -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13)) -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13) -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10)) -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10) -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10) -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8)) -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8) -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8) -#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5)) -#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5) -#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5) -#define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4) -#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1)) -#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1) -#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1) -#define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0) - -#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29)) -#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29) -#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29) -#define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28) -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24)) -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24) -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24) -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20)) -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20) -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20) -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18)) -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18) -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18) -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15)) -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15) -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13)) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11)) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9)) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7)) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7) -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7) -#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6) -#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5) -#define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4) -#define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3) -#define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2) -#define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1) -#define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0) - -#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17)) -#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17) -#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17) -#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12)) -#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12) -#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12) -#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8)) -#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8) -#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8) -#define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7) -#define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6) -#define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5) -#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4) -#define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3) -#define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2) -#define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1) -#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0) - -#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27)) -#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27) -#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27) -#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22)) -#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22) -#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22) -#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19)) -#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19) -#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19) -#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16)) -#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16) -#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16) -#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10)) -#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10) -#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10) -#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5)) -#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5) -#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5) -#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3)) -#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3) -#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3) -#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0)) -#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0) - -#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18)) -#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18) -#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) -#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12)) -#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12) -#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) -#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6)) -#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6) -#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) -#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0)) -#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0) - -#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18)) -#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18) -#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) -#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12)) -#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12) -#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) -#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6)) -#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6) -#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) -#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0)) -#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0) - -#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18)) -#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18) -#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) -#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12)) -#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12) -#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) -#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6)) -#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6) -#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) -#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0)) -#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0) - -#define HSIO_S6G_OB_CFG_OB_IDLE BIT(31) -#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30) -#define HSIO_S6G_OB_CFG_OB_POL BIT(29) -#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23)) -#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23) -#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23) -#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18)) -#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18) -#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18) -#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17) -#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16) -#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11)) -#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11) -#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11) -#define HSIO_S6G_OB_CFG_OB_R_COR BIT(10) -#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9) -#define HSIO_S6G_OB_CFG_OB_SR_H BIT(8) -#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4)) -#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4) -#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4) -#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) -#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0) - -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6)) -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6) -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6) -#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0)) -#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0) - -#define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8) -#define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7) -#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6) -#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4)) -#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4) -#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4) -#define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3) -#define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2) -#define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1) -#define HSIO_S6G_SER_CFG_SER_ENALI BIT(0) - -#define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17) -#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16) -#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15) -#define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14) -#define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13) -#define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12) -#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9)) -#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9) -#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9) -#define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8) -#define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7) -#define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6) -#define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5) -#define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4) -#define HSIO_S6G_COMMON_CFG_HRATE BIT(3) -#define HSIO_S6G_COMMON_CFG_QRATE BIT(2) -#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0)) -#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0) - -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16)) -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16) -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16) -#define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15) -#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14) -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6) -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6) -#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5) -#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4) -#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3) -#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2) -#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1) -#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0) - -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5) -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4) -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3) -#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2) -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1) -#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0) - -#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16)) -#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16) -#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16) -#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0)) -#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0) - -#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8) -#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7) -#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6) -#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5) -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4) -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3) -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2) -#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1) -#define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0) - -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18)) -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18) -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18) -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12)) -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12) -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12) -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6)) -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6) -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6) -#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0)) -#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0) - -#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2) -#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1) -#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0) - -#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10) -#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9) -#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8) -#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0)) -#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0) - -#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26)) -#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26) -#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26) -#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21)) -#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21) -#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21) -#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16)) -#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16) -#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16) -#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10)) -#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10) -#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10) -#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5)) -#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5) -#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5) -#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0)) -#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0) - -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31) -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30) -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0)) -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0) - -#define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6) -#define HSIO_HW_CFG_DEV1G_9_MODE BIT(5) -#define HSIO_HW_CFG_DEV1G_6_MODE BIT(4) -#define HSIO_HW_CFG_DEV1G_5_MODE BIT(3) -#define HSIO_HW_CFG_DEV1G_4_MODE BIT(2) -#define HSIO_HW_CFG_PCIE_ENA BIT(1) -#define HSIO_HW_CFG_QSGMII_ENA BIT(0) - -#define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3) -#define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2) -#define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1) -#define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0) - -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1)) -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1) -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1) -#define HSIO_HW_QSGMII_STAT_SYNC BIT(0) - -#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1)) -#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1) -#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1) -#define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0) - -#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5) -#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4) -#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3) -#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2) -#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1) -#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0) - -#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8)) -#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8) -#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8) -#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0)) -#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0) - -#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8) -#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0)) -#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0) - -#endif diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c b/drivers/net/ethernet/mscc/ocelot_regs.c index e334b406c40c..9271af18b93b 100644 --- a/drivers/net/ethernet/mscc/ocelot_regs.c +++ b/drivers/net/ethernet/mscc/ocelot_regs.c @@ -5,6 +5,7 @@ * Copyright (c) 2017 Microsemi Corporation */ #include "ocelot.h" +#include <soc/mscc/ocelot_hsio.h> static const u32 ocelot_ana_regmap[] = { REG(ANA_ADVLEARN, 0x009000), @@ -102,82 +103,6 @@ static const u32 ocelot_qs_regmap[] = { REG(QS_INH_DBG, 0x000048), }; -static const u32 ocelot_hsio_regmap[] = { - REG(HSIO_PLL5G_CFG0, 0x000000), - REG(HSIO_PLL5G_CFG1, 0x000004), - REG(HSIO_PLL5G_CFG2, 0x000008), - REG(HSIO_PLL5G_CFG3, 0x00000c), - REG(HSIO_PLL5G_CFG4, 0x000010), - REG(HSIO_PLL5G_CFG5, 0x000014), - REG(HSIO_PLL5G_CFG6, 0x000018), - REG(HSIO_PLL5G_STATUS0, 0x00001c), - REG(HSIO_PLL5G_STATUS1, 0x000020), - REG(HSIO_PLL5G_BIST_CFG0, 0x000024), - REG(HSIO_PLL5G_BIST_CFG1, 0x000028), - REG(HSIO_PLL5G_BIST_CFG2, 0x00002c), - REG(HSIO_PLL5G_BIST_STAT0, 0x000030), - REG(HSIO_PLL5G_BIST_STAT1, 0x000034), - REG(HSIO_RCOMP_CFG0, 0x000038), - REG(HSIO_RCOMP_STATUS, 0x00003c), - REG(HSIO_SYNC_ETH_CFG, 0x000040), - REG(HSIO_SYNC_ETH_PLL_CFG, 0x000048), - REG(HSIO_S1G_DES_CFG, 0x00004c), - REG(HSIO_S1G_IB_CFG, 0x000050), - REG(HSIO_S1G_OB_CFG, 0x000054), - REG(HSIO_S1G_SER_CFG, 0x000058), - REG(HSIO_S1G_COMMON_CFG, 0x00005c), - REG(HSIO_S1G_PLL_CFG, 0x000060), - REG(HSIO_S1G_PLL_STATUS, 0x000064), - REG(HSIO_S1G_DFT_CFG0, 0x000068), - REG(HSIO_S1G_DFT_CFG1, 0x00006c), - REG(HSIO_S1G_DFT_CFG2, 0x000070), - REG(HSIO_S1G_TP_CFG, 0x000074), - REG(HSIO_S1G_RC_PLL_BIST_CFG, 0x000078), - REG(HSIO_S1G_MISC_CFG, 0x00007c), - REG(HSIO_S1G_DFT_STATUS, 0x000080), - REG(HSIO_S1G_MISC_STATUS, 0x000084), - REG(HSIO_MCB_S1G_ADDR_CFG, 0x000088), - REG(HSIO_S6G_DIG_CFG, 0x00008c), - REG(HSIO_S6G_DFT_CFG0, 0x000090), - REG(HSIO_S6G_DFT_CFG1, 0x000094), - REG(HSIO_S6G_DFT_CFG2, 0x000098), - REG(HSIO_S6G_TP_CFG0, 0x00009c), - REG(HSIO_S6G_TP_CFG1, 0x0000a0), - REG(HSIO_S6G_RC_PLL_BIST_CFG, 0x0000a4), - REG(HSIO_S6G_MISC_CFG, 0x0000a8), - REG(HSIO_S6G_OB_ANEG_CFG, 0x0000ac), - REG(HSIO_S6G_DFT_STATUS, 0x0000b0), - REG(HSIO_S6G_ERR_CNT, 0x0000b4), - REG(HSIO_S6G_MISC_STATUS, 0x0000b8), - REG(HSIO_S6G_DES_CFG, 0x0000bc), - REG(HSIO_S6G_IB_CFG, 0x0000c0), - REG(HSIO_S6G_IB_CFG1, 0x0000c4), - REG(HSIO_S6G_IB_CFG2, 0x0000c8), - REG(HSIO_S6G_IB_CFG3, 0x0000cc), - REG(HSIO_S6G_IB_CFG4, 0x0000d0), - REG(HSIO_S6G_IB_CFG5, 0x0000d4), - REG(HSIO_S6G_OB_CFG, 0x0000d8), - REG(HSIO_S6G_OB_CFG1, 0x0000dc), - REG(HSIO_S6G_SER_CFG, 0x0000e0), - REG(HSIO_S6G_COMMON_CFG, 0x0000e4), - REG(HSIO_S6G_PLL_CFG, 0x0000e8), - REG(HSIO_S6G_ACJTAG_CFG, 0x0000ec), - REG(HSIO_S6G_GP_CFG, 0x0000f0), - REG(HSIO_S6G_IB_STATUS0, 0x0000f4), - REG(HSIO_S6G_IB_STATUS1, 0x0000f8), - REG(HSIO_S6G_ACJTAG_STATUS, 0x0000fc), - REG(HSIO_S6G_PLL_STATUS, 0x000100), - REG(HSIO_S6G_REVID, 0x000104), - REG(HSIO_MCB_S6G_ADDR_CFG, 0x000108), - REG(HSIO_HW_CFG, 0x00010c), - REG(HSIO_HW_QSGMII_CFG, 0x000110), - REG(HSIO_HW_QSGMII_STAT, 0x000114), - REG(HSIO_CLK_CFG, 0x000118), - REG(HSIO_TEMP_SENSOR_CTRL, 0x00011c), - REG(HSIO_TEMP_SENSOR_CFG, 0x000120), - REG(HSIO_TEMP_SENSOR_STAT, 0x000124), -}; - static const u32 ocelot_qsys_regmap[] = { REG(QSYS_PORT_MODE, 0x011200), REG(QSYS_SWITCH_PORT_MODE, 0x011234), @@ -302,7 +227,6 @@ static const u32 ocelot_sys_regmap[] = { static const u32 *ocelot_regmap[] = { [ANA] = ocelot_ana_regmap, [QS] = ocelot_qs_regmap, - [HSIO] = ocelot_hsio_regmap, [QSYS] = ocelot_qsys_regmap, [REW] = ocelot_rew_regmap, [SYS] = ocelot_sys_regmap, @@ -453,9 +377,11 @@ static void ocelot_pll5_init(struct ocelot *ocelot) /* Configure PLL5. This will need a proper CCF driver * The values are coming from the VTSS API for Ocelot */ - ocelot_write(ocelot, HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | - HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8), HSIO_PLL5G_CFG4); - ocelot_write(ocelot, HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, + HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | + HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, + HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | HSIO_PLL5G_CFG0_ENA_BIAS | HSIO_PLL5G_CFG0_ENA_VCO_BUF | @@ -465,13 +391,14 @@ static void ocelot_pll5_init(struct ocelot *ocelot) HSIO_PLL5G_CFG0_SELBGV820(4) | HSIO_PLL5G_CFG0_DIV4 | HSIO_PLL5G_CFG0_ENA_CLKTREE | - HSIO_PLL5G_CFG0_ENA_LANE, HSIO_PLL5G_CFG0); - ocelot_write(ocelot, HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | + HSIO_PLL5G_CFG0_ENA_LANE); + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, + HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | HSIO_PLL5G_CFG2_ENA_AMPCTRL | HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | - HSIO_PLL5G_CFG2_AMPC_SEL(0x10), HSIO_PLL5G_CFG2); + HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); } int ocelot_chip_init(struct ocelot *ocelot) |