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-rw-r--r--drivers/scsi/smartpqi/smartpqi.h44
-rw-r--r--drivers/scsi/smartpqi/smartpqi_init.c145
-rw-r--r--drivers/scsi/smartpqi/smartpqi_sas_transport.c9
-rw-r--r--drivers/scsi/smartpqi/smartpqi_sis.c111
-rw-r--r--drivers/scsi/smartpqi/smartpqi_sis.h4
5 files changed, 159 insertions, 154 deletions
diff --git a/drivers/scsi/smartpqi/smartpqi.h b/drivers/scsi/smartpqi/smartpqi.h
index e164ffade38a..dc3a0542a2e8 100644
--- a/drivers/scsi/smartpqi/smartpqi.h
+++ b/drivers/scsi/smartpqi/smartpqi.h
@@ -688,6 +688,28 @@ struct pqi_config_table_heartbeat {
__le32 heartbeat_counter;
};
+union pqi_reset_register {
+ struct {
+ u32 reset_type : 3;
+ u32 reserved : 2;
+ u32 reset_action : 3;
+ u32 hold_in_pd1 : 1;
+ u32 reserved2 : 23;
+ } bits;
+ u32 all_bits;
+};
+
+#define PQI_RESET_ACTION_RESET 0x1
+
+#define PQI_RESET_TYPE_NO_RESET 0x0
+#define PQI_RESET_TYPE_SOFT_RESET 0x1
+#define PQI_RESET_TYPE_FIRM_RESET 0x2
+#define PQI_RESET_TYPE_HARD_RESET 0x3
+
+#define PQI_RESET_ACTION_COMPLETED 0x2
+
+#define PQI_RESET_POLL_INTERVAL_MSECS 100
+
#define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0)
#define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32
#define PQI_MAX_TRANSFER_SIZE (1024U * 1024U)
@@ -995,6 +1017,7 @@ struct pqi_ctrl_info {
u8 inbound_spanning_supported : 1;
u8 outbound_spanning_supported : 1;
u8 pqi_mode_enabled : 1;
+ u8 pqi_reset_quiesce_supported : 1;
struct list_head scsi_device_list;
spinlock_t scsi_device_list_lock;
@@ -1056,9 +1079,9 @@ enum pqi_ctrl_mode {
#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
#define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
#define BMIC_WRITE_HOST_WELLNESS 0xa5
-#define BMIC_CACHE_FLUSH 0xc2
+#define BMIC_FLUSH_CACHE 0xc2
-#define SA_CACHE_FLUSH 0x1
+#define SA_FLUSH_CACHE 0x1
#define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0)
#define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f)
@@ -1164,6 +1187,23 @@ struct bmic_identify_physical_device {
u8 padding_to_multiple_of_512[9];
};
+struct bmic_flush_cache {
+ u8 disable_flag;
+ u8 system_power_action;
+ u8 ndu_flush;
+ u8 shutdown_event;
+ u8 reserved[28];
+};
+
+/* for shutdown_event member of struct bmic_flush_cache */
+enum bmic_flush_cache_shutdown_event {
+ NONE_CACHE_FLUSH_ONLY = 0,
+ SHUTDOWN = 1,
+ HIBERNATE = 2,
+ SUSPEND = 3,
+ RESTART = 4
+};
+
#pragma pack()
int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info);
diff --git a/drivers/scsi/smartpqi/smartpqi_init.c b/drivers/scsi/smartpqi/smartpqi_init.c
index cb8f886e705c..83bdbd84eb01 100644
--- a/drivers/scsi/smartpqi/smartpqi_init.c
+++ b/drivers/scsi/smartpqi/smartpqi_init.c
@@ -40,11 +40,11 @@
#define BUILD_TIMESTAMP
#endif
-#define DRIVER_VERSION "1.0.4-100"
+#define DRIVER_VERSION "1.1.2-125"
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 0
-#define DRIVER_RELEASE 4
-#define DRIVER_REVISION 100
+#define DRIVER_MINOR 1
+#define DRIVER_RELEASE 2
+#define DRIVER_REVISION 125
#define DRIVER_NAME "Microsemi PQI Driver (v" \
DRIVER_VERSION BUILD_TIMESTAMP ")"
@@ -431,10 +431,10 @@ static int pqi_build_raid_path_request(struct pqi_ctrl_info *ctrl_info,
cdb[1] = CISS_GET_RAID_MAP;
put_unaligned_be32(buffer_length, &cdb[6]);
break;
- case SA_CACHE_FLUSH:
+ case SA_FLUSH_CACHE:
request->data_direction = SOP_WRITE_FLAG;
cdb[0] = BMIC_WRITE;
- cdb[6] = BMIC_CACHE_FLUSH;
+ cdb[6] = BMIC_FLUSH_CACHE;
put_unaligned_be16(buffer_length, &cdb[7]);
break;
case BMIC_IDENTIFY_CONTROLLER:
@@ -585,14 +585,13 @@ static int pqi_identify_physical_device(struct pqi_ctrl_info *ctrl_info,
return rc;
}
-#define SA_CACHE_FLUSH_BUFFER_LENGTH 4
-
-static int pqi_flush_cache(struct pqi_ctrl_info *ctrl_info)
+static int pqi_flush_cache(struct pqi_ctrl_info *ctrl_info,
+ enum bmic_flush_cache_shutdown_event shutdown_event)
{
int rc;
struct pqi_raid_path_request request;
int pci_direction;
- u8 *buffer;
+ struct bmic_flush_cache *flush_cache;
/*
* Don't bother trying to flush the cache if the controller is
@@ -601,13 +600,15 @@ static int pqi_flush_cache(struct pqi_ctrl_info *ctrl_info)
if (pqi_ctrl_offline(ctrl_info))
return -ENXIO;
- buffer = kzalloc(SA_CACHE_FLUSH_BUFFER_LENGTH, GFP_KERNEL);
- if (!buffer)
+ flush_cache = kzalloc(sizeof(*flush_cache), GFP_KERNEL);
+ if (!flush_cache)
return -ENOMEM;
+ flush_cache->shutdown_event = shutdown_event;
+
rc = pqi_build_raid_path_request(ctrl_info, &request,
- SA_CACHE_FLUSH, RAID_CTLR_LUNID, buffer,
- SA_CACHE_FLUSH_BUFFER_LENGTH, 0, &pci_direction);
+ SA_FLUSH_CACHE, RAID_CTLR_LUNID, flush_cache,
+ sizeof(*flush_cache), 0, &pci_direction);
if (rc)
goto out;
@@ -618,7 +619,7 @@ static int pqi_flush_cache(struct pqi_ctrl_info *ctrl_info)
pci_direction);
out:
- kfree(buffer);
+ kfree(flush_cache);
return rc;
}
@@ -3007,11 +3008,9 @@ static void pqi_change_irq_mode(struct pqi_ctrl_info *ctrl_info,
break;
case IRQ_MODE_INTX:
pqi_configure_legacy_intx(ctrl_info, true);
- sis_disable_msix(ctrl_info);
sis_enable_intx(ctrl_info);
break;
case IRQ_MODE_NONE:
- sis_disable_msix(ctrl_info);
break;
}
break;
@@ -3019,14 +3018,12 @@ static void pqi_change_irq_mode(struct pqi_ctrl_info *ctrl_info,
switch (new_mode) {
case IRQ_MODE_MSIX:
pqi_configure_legacy_intx(ctrl_info, false);
- sis_disable_intx(ctrl_info);
sis_enable_msix(ctrl_info);
break;
case IRQ_MODE_INTX:
break;
case IRQ_MODE_NONE:
pqi_configure_legacy_intx(ctrl_info, false);
- sis_disable_intx(ctrl_info);
break;
}
break;
@@ -5498,6 +5495,7 @@ static int pqi_passthru_ioctl(struct pqi_ctrl_info *ctrl_info, void __user *arg)
case XFER_NONE:
case XFER_WRITE:
case XFER_READ:
+ case XFER_READ | XFER_WRITE:
break;
default:
return -EINVAL;
@@ -5538,6 +5536,9 @@ static int pqi_passthru_ioctl(struct pqi_ctrl_info *ctrl_info, void __user *arg)
case XFER_READ:
request.data_direction = SOP_READ_FLAG;
break;
+ case XFER_READ | XFER_WRITE:
+ request.data_direction = SOP_BIDIRECTIONAL;
+ break;
}
request.task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
@@ -5889,28 +5890,62 @@ static void pqi_unregister_scsi(struct pqi_ctrl_info *ctrl_info)
scsi_host_put(shost);
}
-#define PQI_RESET_ACTION_RESET 0x1
+static int pqi_wait_for_pqi_reset_completion(struct pqi_ctrl_info *ctrl_info)
+{
+ int rc = 0;
+ struct pqi_device_registers __iomem *pqi_registers;
+ unsigned long timeout;
+ unsigned int timeout_msecs;
+ union pqi_reset_register reset_reg;
-#define PQI_RESET_TYPE_NO_RESET 0x0
-#define PQI_RESET_TYPE_SOFT_RESET 0x1
-#define PQI_RESET_TYPE_FIRM_RESET 0x2
-#define PQI_RESET_TYPE_HARD_RESET 0x3
+ pqi_registers = ctrl_info->pqi_registers;
+ timeout_msecs = readw(&pqi_registers->max_reset_timeout) * 100;
+ timeout = msecs_to_jiffies(timeout_msecs) + jiffies;
+
+ while (1) {
+ msleep(PQI_RESET_POLL_INTERVAL_MSECS);
+ reset_reg.all_bits = readl(&pqi_registers->device_reset);
+ if (reset_reg.bits.reset_action == PQI_RESET_ACTION_COMPLETED)
+ break;
+ pqi_check_ctrl_health(ctrl_info);
+ if (pqi_ctrl_offline(ctrl_info)) {
+ rc = -ENXIO;
+ break;
+ }
+ if (time_after(jiffies, timeout)) {
+ rc = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ return rc;
+}
static int pqi_reset(struct pqi_ctrl_info *ctrl_info)
{
int rc;
- u32 reset_params;
+ union pqi_reset_register reset_reg;
+
+ if (ctrl_info->pqi_reset_quiesce_supported) {
+ rc = sis_pqi_reset_quiesce(ctrl_info);
+ if (rc) {
+ dev_err(&ctrl_info->pci_dev->dev,
+ "PQI reset failed during quiesce with error %d\n",
+ rc);
+ return rc;
+ }
+ }
- reset_params = (PQI_RESET_ACTION_RESET << 5) |
- PQI_RESET_TYPE_HARD_RESET;
+ reset_reg.all_bits = 0;
+ reset_reg.bits.reset_type = PQI_RESET_TYPE_HARD_RESET;
+ reset_reg.bits.reset_action = PQI_RESET_ACTION_RESET;
- writel(reset_params,
- &ctrl_info->pqi_registers->device_reset);
+ writel(reset_reg.all_bits, &ctrl_info->pqi_registers->device_reset);
- rc = pqi_wait_for_pqi_mode_ready(ctrl_info);
+ rc = pqi_wait_for_pqi_reset_completion(ctrl_info);
if (rc)
dev_err(&ctrl_info->pci_dev->dev,
- "PQI reset failed\n");
+ "PQI reset failed with error %d\n", rc);
return rc;
}
@@ -6007,7 +6042,12 @@ static int pqi_revert_to_sis_mode(struct pqi_ctrl_info *ctrl_info)
rc = pqi_reset(ctrl_info);
if (rc)
return rc;
- sis_reenable_sis_mode(ctrl_info);
+ rc = sis_reenable_sis_mode(ctrl_info);
+ if (rc) {
+ dev_err(&ctrl_info->pci_dev->dev,
+ "re-enabling SIS mode failed with error %d\n", rc);
+ return rc;
+ }
pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
return 0;
@@ -6659,7 +6699,8 @@ static void pqi_shutdown(struct pci_dev *pci_dev)
* Write all data in the controller's battery-backed cache to
* storage.
*/
- rc = pqi_flush_cache(ctrl_info);
+ rc = pqi_flush_cache(ctrl_info, SHUTDOWN);
+ pqi_reset(ctrl_info);
if (rc == 0)
return;
@@ -6703,7 +6744,7 @@ static __maybe_unused int pqi_suspend(struct pci_dev *pci_dev, pm_message_t stat
pqi_cancel_rescan_worker(ctrl_info);
pqi_wait_until_scan_finished(ctrl_info);
pqi_wait_until_lun_reset_finished(ctrl_info);
- pqi_flush_cache(ctrl_info);
+ pqi_flush_cache(ctrl_info, SUSPEND);
pqi_ctrl_block_requests(ctrl_info);
pqi_ctrl_wait_until_quiesced(ctrl_info);
pqi_wait_until_inbound_queues_empty(ctrl_info);
@@ -6781,7 +6822,7 @@ static const struct pci_device_id pqi_pci_id_table[] = {
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
- PCI_VENDOR_ID_ADAPTEC2, 0x0605)
+ PCI_VENDOR_ID_ADAPTEC2, 0x0608)
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
@@ -6813,6 +6854,10 @@ static const struct pci_device_id pqi_pci_id_table[] = {
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
+ PCI_VENDOR_ID_ADAPTEC2, 0x0807)
+ },
+ {
+ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
PCI_VENDOR_ID_ADAPTEC2, 0x0900)
},
{
@@ -6849,6 +6894,10 @@ static const struct pci_device_id pqi_pci_id_table[] = {
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
+ PCI_VENDOR_ID_ADAPTEC2, 0x090a)
+ },
+ {
+ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
PCI_VENDOR_ID_ADAPTEC2, 0x1200)
},
{
@@ -6881,6 +6930,10 @@ static const struct pci_device_id pqi_pci_id_table[] = {
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
+ PCI_VENDOR_ID_DELL, 0x1fe0)
+ },
+ {
+ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
PCI_VENDOR_ID_HP, 0x0600)
},
{
@@ -6897,11 +6950,7 @@ static const struct pci_device_id pqi_pci_id_table[] = {
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
- PCI_VENDOR_ID_HP, 0x0604)
- },
- {
- PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
- PCI_VENDOR_ID_HP, 0x0606)
+ PCI_VENDOR_ID_HP, 0x0609)
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
@@ -6929,14 +6978,6 @@ static const struct pci_device_id pqi_pci_id_table[] = {
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
- PCI_VENDOR_ID_HP, 0x0656)
- },
- {
- PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
- PCI_VENDOR_ID_HP, 0x0657)
- },
- {
- PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
PCI_VENDOR_ID_HP, 0x0700)
},
{
@@ -6957,14 +6998,6 @@ static const struct pci_device_id pqi_pci_id_table[] = {
},
{
PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
- PCI_VENDOR_ID_HP, 0x1102)
- },
- {
- PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
- PCI_VENDOR_ID_HP, 0x1150)
- },
- {
- PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
PCI_ANY_ID, PCI_ANY_ID)
},
{ 0 }
diff --git a/drivers/scsi/smartpqi/smartpqi_sas_transport.c b/drivers/scsi/smartpqi/smartpqi_sas_transport.c
index 0d89d3728b43..b209a35e482e 100644
--- a/drivers/scsi/smartpqi/smartpqi_sas_transport.c
+++ b/drivers/scsi/smartpqi/smartpqi_sas_transport.c
@@ -329,14 +329,6 @@ static int pqi_sas_phy_speed(struct sas_phy *phy,
return -EINVAL;
}
-/* SMP = Serial Management Protocol */
-
-static int pqi_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
- struct request *req)
-{
- return -EINVAL;
-}
-
struct sas_function_template pqi_sas_transport_functions = {
.get_linkerrors = pqi_sas_get_linkerrors,
.get_enclosure_identifier = pqi_sas_get_enclosure_identifier,
@@ -346,5 +338,4 @@ struct sas_function_template pqi_sas_transport_functions = {
.phy_setup = pqi_sas_phy_setup,
.phy_release = pqi_sas_phy_release,
.set_phy_speed = pqi_sas_phy_speed,
- .smp_handler = pqi_sas_smp_handler,
};
diff --git a/drivers/scsi/smartpqi/smartpqi_sis.c b/drivers/scsi/smartpqi/smartpqi_sis.c
index e55dfcf200e5..5141bd4c9f06 100644
--- a/drivers/scsi/smartpqi/smartpqi_sis.c
+++ b/drivers/scsi/smartpqi/smartpqi_sis.c
@@ -34,11 +34,13 @@
#define SIS_REENABLE_SIS_MODE 0x1
#define SIS_ENABLE_MSIX 0x40
#define SIS_ENABLE_INTX 0x80
-#define SIS_SOFT_RESET 0x100
-#define SIS_TRIGGER_SHUTDOWN 0x800000
#define SIS_CMD_READY 0x200
+#define SIS_TRIGGER_SHUTDOWN 0x800000
+#define SIS_PQI_RESET_QUIESCE 0x1000000
+
#define SIS_CMD_COMPLETE 0x1000
#define SIS_CLEAR_CTRL_TO_HOST_DOORBELL 0x1000
+
#define SIS_CMD_STATUS_SUCCESS 0x1
#define SIS_CMD_COMPLETE_TIMEOUT_SECS 30
#define SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS 10
@@ -47,6 +49,7 @@
#define SIS_EXTENDED_PROPERTIES_SUPPORTED 0x800000
#define SIS_SMARTARRAY_FEATURES_SUPPORTED 0x2
#define SIS_PQI_MODE_SUPPORTED 0x4
+#define SIS_PQI_RESET_QUIESCE_SUPPORTED 0x8
#define SIS_REQUIRED_EXTENDED_PROPERTIES \
(SIS_SMARTARRAY_FEATURES_SUPPORTED | SIS_PQI_MODE_SUPPORTED)
@@ -258,6 +261,9 @@ int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info)
SIS_REQUIRED_EXTENDED_PROPERTIES)
return -ENODEV;
+ if (extended_properties & SIS_PQI_RESET_QUIESCE_SUPPORTED)
+ ctrl_info->pqi_reset_quiesce_supported = true;
+
return 0;
}
@@ -336,9 +342,10 @@ out:
#define SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS 30
-static void sis_wait_for_doorbell_bit_to_clear(
+static int sis_wait_for_doorbell_bit_to_clear(
struct pqi_ctrl_info *ctrl_info, u32 bit)
{
+ int rc = 0;
u32 doorbell_register;
unsigned long timeout;
@@ -350,78 +357,38 @@ static void sis_wait_for_doorbell_bit_to_clear(
if ((doorbell_register & bit) == 0)
break;
if (readl(&ctrl_info->registers->sis_firmware_status) &
- SIS_CTRL_KERNEL_PANIC)
+ SIS_CTRL_KERNEL_PANIC) {
+ rc = -ENODEV;
break;
+ }
if (time_after(jiffies, timeout)) {
dev_err(&ctrl_info->pci_dev->dev,
"doorbell register bit 0x%x not cleared\n",
bit);
+ rc = -ETIMEDOUT;
break;
}
usleep_range(1000, 2000);
}
-}
-
-/* Enable MSI-X interrupts on the controller. */
-
-void sis_enable_msix(struct pqi_ctrl_info *ctrl_info)
-{
- u32 doorbell_register;
-
- doorbell_register =
- readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
- doorbell_register |= SIS_ENABLE_MSIX;
-
- writel(doorbell_register,
- &ctrl_info->registers->sis_host_to_ctrl_doorbell);
- sis_wait_for_doorbell_bit_to_clear(ctrl_info, SIS_ENABLE_MSIX);
+ return rc;
}
-/* Disable MSI-X interrupts on the controller. */
-
-void sis_disable_msix(struct pqi_ctrl_info *ctrl_info)
+static inline int sis_set_doorbell_bit(struct pqi_ctrl_info *ctrl_info, u32 bit)
{
- u32 doorbell_register;
-
- doorbell_register =
- readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
- doorbell_register &= ~SIS_ENABLE_MSIX;
+ writel(bit, &ctrl_info->registers->sis_host_to_ctrl_doorbell);
- writel(doorbell_register,
- &ctrl_info->registers->sis_host_to_ctrl_doorbell);
+ return sis_wait_for_doorbell_bit_to_clear(ctrl_info, bit);
}
-void sis_enable_intx(struct pqi_ctrl_info *ctrl_info)
+void sis_enable_msix(struct pqi_ctrl_info *ctrl_info)
{
- u32 doorbell_register;
-
- doorbell_register =
- readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
- doorbell_register |= SIS_ENABLE_INTX;
-
- writel(doorbell_register,
- &ctrl_info->registers->sis_host_to_ctrl_doorbell);
-
- sis_wait_for_doorbell_bit_to_clear(ctrl_info, SIS_ENABLE_INTX);
+ sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_MSIX);
}
-void sis_disable_intx(struct pqi_ctrl_info *ctrl_info)
-{
- u32 doorbell_register;
-
- doorbell_register =
- readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
- doorbell_register &= ~SIS_ENABLE_INTX;
-
- writel(doorbell_register,
- &ctrl_info->registers->sis_host_to_ctrl_doorbell);
-}
-
-void sis_soft_reset(struct pqi_ctrl_info *ctrl_info)
+void sis_enable_intx(struct pqi_ctrl_info *ctrl_info)
{
- writel(SIS_SOFT_RESET,
- &ctrl_info->registers->sis_host_to_ctrl_doorbell);
+ sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_INTX);
}
void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info)
@@ -434,38 +401,14 @@ void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info)
&ctrl_info->registers->sis_host_to_ctrl_doorbell);
}
-#define SIS_MODE_READY_TIMEOUT_SECS 30
+int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info)
+{
+ return sis_set_doorbell_bit(ctrl_info, SIS_PQI_RESET_QUIESCE);
+}
int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info)
{
- int rc;
- unsigned long timeout;
- struct pqi_ctrl_registers __iomem *registers;
- u32 doorbell;
-
- registers = ctrl_info->registers;
-
- writel(SIS_REENABLE_SIS_MODE,
- &registers->sis_host_to_ctrl_doorbell);
-
- rc = 0;
- timeout = (SIS_MODE_READY_TIMEOUT_SECS * HZ) + jiffies;
-
- while (1) {
- doorbell = readl(&registers->sis_ctrl_to_host_doorbell);
- if ((doorbell & SIS_REENABLE_SIS_MODE) == 0)
- break;
- if (time_after(jiffies, timeout)) {
- rc = -ETIMEDOUT;
- break;
- }
- }
-
- if (rc)
- dev_err(&ctrl_info->pci_dev->dev,
- "re-enabling SIS mode failed\n");
-
- return rc;
+ return sis_set_doorbell_bit(ctrl_info, SIS_REENABLE_SIS_MODE);
}
void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value)
diff --git a/drivers/scsi/smartpqi/smartpqi_sis.h b/drivers/scsi/smartpqi/smartpqi_sis.h
index 983184b69373..2bf889dbf5ab 100644
--- a/drivers/scsi/smartpqi/smartpqi_sis.h
+++ b/drivers/scsi/smartpqi/smartpqi_sis.h
@@ -27,11 +27,9 @@ int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info);
int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info);
int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info);
void sis_enable_msix(struct pqi_ctrl_info *ctrl_info);
-void sis_disable_msix(struct pqi_ctrl_info *ctrl_info);
void sis_enable_intx(struct pqi_ctrl_info *ctrl_info);
-void sis_disable_intx(struct pqi_ctrl_info *ctrl_info);
-void sis_soft_reset(struct pqi_ctrl_info *ctrl_info);
void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info);
+int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info);
int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info);
void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value);
u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info);
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-06-11 06:01:04 +0200