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path: root/drivers/spmi/spmi-pmic-arb.c
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Diffstat (limited to 'drivers/spmi/spmi-pmic-arb.c')
-rw-r--r--drivers/spmi/spmi-pmic-arb.c837
1 files changed, 493 insertions, 344 deletions
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index f4b7a98a7913..360b8218f322 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -29,6 +29,7 @@
#define PMIC_ARB_VERSION 0x0000
#define PMIC_ARB_VERSION_V2_MIN 0x20010000
#define PMIC_ARB_VERSION_V3_MIN 0x30000000
+#define PMIC_ARB_VERSION_V5_MIN 0x50000000
#define PMIC_ARB_INT_EN 0x0004
/* PMIC Arbiter channel registers offsets */
@@ -39,7 +40,6 @@
#define PMIC_ARB_WDATA1 0x14
#define PMIC_ARB_RDATA0 0x18
#define PMIC_ARB_RDATA1 0x1C
-#define PMIC_ARB_REG_CHNL(N) (0x800 + 0x4 * (N))
/* Mapping Table */
#define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
@@ -51,7 +51,9 @@
#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
#define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
-#define PMIC_ARB_CHAN_VALID BIT(15)
+#define PMIC_ARB_APID_VALID BIT(15)
+#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
+#define INVALID_EE 0xFF
/* Ownership Table */
#define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
@@ -86,6 +88,15 @@ enum pmic_arb_cmd_op_code {
PMIC_ARB_OP_ZERO_WRITE = 16,
};
+/*
+ * PMIC arbiter version 5 uses different register offsets for read/write vs
+ * observer channels.
+ */
+enum pmic_arb_channel {
+ PMIC_ARB_CHANNEL_RW,
+ PMIC_ARB_CHANNEL_OBS,
+};
+
/* Maximum number of support PMIC peripherals */
#define PMIC_ARB_MAX_PERIPHS 512
#define PMIC_ARB_TIMEOUT_US 100
@@ -97,22 +108,23 @@ enum pmic_arb_cmd_op_code {
/* interrupt enable bit */
#define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
-#define HWIRQ(slave_id, periph_id, irq_id, apid) \
+#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
((((slave_id) & 0xF) << 28) | \
(((periph_id) & 0xFF) << 20) | \
(((irq_id) & 0x7) << 16) | \
(((apid) & 0x1FF) << 0))
-#define HWIRQ_SID(hwirq) (((hwirq) >> 28) & 0xF)
-#define HWIRQ_PER(hwirq) (((hwirq) >> 20) & 0xFF)
-#define HWIRQ_IRQ(hwirq) (((hwirq) >> 16) & 0x7)
-#define HWIRQ_APID(hwirq) (((hwirq) >> 0) & 0x1FF)
+#define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
+#define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
+#define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
+#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x1FF)
struct pmic_arb_ver_ops;
struct apid_data {
u16 ppid;
- u8 owner;
+ u8 write_ee;
+ u8 irq_ee;
};
/**
@@ -128,12 +140,11 @@ struct apid_data {
* @ee: the current Execution Environment
* @min_apid: minimum APID (used for bounding IRQ search)
* @max_apid: maximum APID
- * @max_periph: maximum number of PMIC peripherals supported by HW.
* @mapping_table: in-memory copy of PPID -> APID mapping table.
* @domain: irq domain object for PMIC IRQ domain
* @spmic: SPMI controller object
* @ver_ops: version dependent operations.
- * @ppid_to_apid in-memory copy of PPID -> channel (APID) mapping table.
+ * @ppid_to_apid in-memory copy of PPID -> APID mapping table.
*/
struct spmi_pmic_arb {
void __iomem *rd_base;
@@ -148,7 +159,6 @@ struct spmi_pmic_arb {
u8 ee;
u16 min_apid;
u16 max_apid;
- u16 max_periph;
u32 *mapping_table;
DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
struct irq_domain *domain;
@@ -164,92 +174,94 @@ struct spmi_pmic_arb {
*
* @ver_str: version string.
* @ppid_to_apid: finds the apid for a given ppid.
- * @mode: access rights to specified pmic peripheral.
* @non_data_cmd: on v1 issues an spmi non-data command.
* on v2 no HW support, returns -EOPNOTSUPP.
* @offset: on v1 offset of per-ee channel.
* on v2 offset of per-ee and per-ppid channel.
* @fmt_cmd: formats a GENI/SPMI command.
- * @owner_acc_status: on v1 offset of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
- * on v2 offset of SPMI_PIC_OWNERm_ACC_STATUSn.
- * @acc_enable: on v1 offset of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
- * on v2 offset of SPMI_PIC_ACC_ENABLEn.
- * @irq_status: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
- * on v2 offset of SPMI_PIC_IRQ_STATUSn.
- * @irq_clear: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
- * on v2 offset of SPMI_PIC_IRQ_CLEARn.
+ * @owner_acc_status: on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
+ * on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
+ * @acc_enable: on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
+ * on v2 address of SPMI_PIC_ACC_ENABLEn.
+ * @irq_status: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
+ * on v2 address of SPMI_PIC_IRQ_STATUSn.
+ * @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
+ * on v2 address of SPMI_PIC_IRQ_CLEARn.
+ * @apid_map_offset: offset of PMIC_ARB_REG_CHNLn
*/
struct pmic_arb_ver_ops {
const char *ver_str;
- int (*ppid_to_apid)(struct spmi_pmic_arb *pa, u8 sid, u16 addr,
- u16 *apid);
- int (*mode)(struct spmi_pmic_arb *dev, u8 sid, u16 addr,
- mode_t *mode);
+ int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
/* spmi commands (read_cmd, write_cmd, cmd) functionality */
- int (*offset)(struct spmi_pmic_arb *dev, u8 sid, u16 addr,
- u32 *offset);
+ int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type);
u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
/* Interrupts controller functionality (offset of PIC registers) */
- u32 (*owner_acc_status)(u8 m, u16 n);
- u32 (*acc_enable)(u16 n);
- u32 (*irq_status)(u16 n);
- u32 (*irq_clear)(u16 n);
+ void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
+ u16 n);
+ void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
+ void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
+ void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
+ u32 (*apid_map_offset)(u16 n);
};
-static inline void pmic_arb_base_write(struct spmi_pmic_arb *pa,
+static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
u32 offset, u32 val)
{
- writel_relaxed(val, pa->wr_base + offset);
+ writel_relaxed(val, pmic_arb->wr_base + offset);
}
-static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pa,
+static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
u32 offset, u32 val)
{
- writel_relaxed(val, pa->rd_base + offset);
+ writel_relaxed(val, pmic_arb->rd_base + offset);
}
/**
- * pa_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
+ * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
* @bc: byte count -1. range: 0..3
* @reg: register's address
* @buf: output parameter, length must be bc + 1
*/
-static void pa_read_data(struct spmi_pmic_arb *pa, u8 *buf, u32 reg, u8 bc)
+static void
+pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
{
- u32 data = __raw_readl(pa->rd_base + reg);
+ u32 data = __raw_readl(pmic_arb->rd_base + reg);
memcpy(buf, &data, (bc & 3) + 1);
}
/**
- * pa_write_data: write 1..4 bytes from buf to pmic-arb's register
+ * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
* @bc: byte-count -1. range: 0..3.
* @reg: register's address.
* @buf: buffer to write. length must be bc + 1.
*/
-static void
-pa_write_data(struct spmi_pmic_arb *pa, const u8 *buf, u32 reg, u8 bc)
+static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
+ u32 reg, u8 bc)
{
u32 data = 0;
memcpy(&data, buf, (bc & 3) + 1);
- pmic_arb_base_write(pa, reg, data);
+ __raw_writel(data, pmic_arb->wr_base + reg);
}
static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
- void __iomem *base, u8 sid, u16 addr)
+ void __iomem *base, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
{
- struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
u32 status = 0;
u32 timeout = PMIC_ARB_TIMEOUT_US;
u32 offset;
int rc;
- rc = pa->ver_ops->offset(pa, sid, addr, &offset);
- if (rc)
+ rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
+ if (rc < 0)
return rc;
+ offset = rc;
offset += PMIC_ARB_STATUS;
while (timeout--) {
@@ -257,22 +269,19 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
if (status & PMIC_ARB_STATUS_DONE) {
if (status & PMIC_ARB_STATUS_DENIED) {
- dev_err(&ctrl->dev,
- "%s: transaction denied (0x%x)\n",
+ dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n",
__func__, status);
return -EPERM;
}
if (status & PMIC_ARB_STATUS_FAILURE) {
- dev_err(&ctrl->dev,
- "%s: transaction failed (0x%x)\n",
+ dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n",
__func__, status);
return -EIO;
}
if (status & PMIC_ARB_STATUS_DROPPED) {
- dev_err(&ctrl->dev,
- "%s: transaction dropped (0x%x)\n",
+ dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n",
__func__, status);
return -EIO;
}
@@ -282,8 +291,7 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
udelay(1);
}
- dev_err(&ctrl->dev,
- "%s: timeout, status 0x%x\n",
+ dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n",
__func__, status);
return -ETIMEDOUT;
}
@@ -291,22 +299,24 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
static int
pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
{
- struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
unsigned long flags;
u32 cmd;
int rc;
u32 offset;
- rc = pa->ver_ops->offset(pa, sid, 0, &offset);
- if (rc)
+ rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
+ if (rc < 0)
return rc;
+ offset = rc;
cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
- raw_spin_lock_irqsave(&pa->lock, flags);
- pmic_arb_base_write(pa, offset + PMIC_ARB_CMD, cmd);
- rc = pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, 0);
- raw_spin_unlock_irqrestore(&pa->lock, flags);
+ raw_spin_lock_irqsave(&pmic_arb->lock, flags);
+ pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
+ rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
+ PMIC_ARB_CHANNEL_RW);
+ raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
return rc;
}
@@ -320,7 +330,7 @@ pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
/* Non-data command */
static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
{
- struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
@@ -328,38 +338,27 @@ static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
return -EINVAL;
- return pa->ver_ops->non_data_cmd(ctrl, opc, sid);
+ return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
}
static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
u16 addr, u8 *buf, size_t len)
{
- struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
unsigned long flags;
u8 bc = len - 1;
u32 cmd;
int rc;
u32 offset;
- mode_t mode;
-
- rc = pa->ver_ops->offset(pa, sid, addr, &offset);
- if (rc)
- return rc;
- rc = pa->ver_ops->mode(pa, sid, addr, &mode);
- if (rc)
+ rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
+ PMIC_ARB_CHANNEL_OBS);
+ if (rc < 0)
return rc;
- if (!(mode & S_IRUSR)) {
- dev_err(&pa->spmic->dev,
- "error: impermissible read from peripheral sid:%d addr:0x%x\n",
- sid, addr);
- return -EPERM;
- }
-
+ offset = rc;
if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
- dev_err(&ctrl->dev,
- "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
+ dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
PMIC_ARB_MAX_TRANS_BYTES, len);
return -EINVAL;
}
@@ -374,54 +373,45 @@ static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
else
return -EINVAL;
- cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc);
+ cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
- raw_spin_lock_irqsave(&pa->lock, flags);
- pmic_arb_set_rd_cmd(pa, offset + PMIC_ARB_CMD, cmd);
- rc = pmic_arb_wait_for_done(ctrl, pa->rd_base, sid, addr);
+ raw_spin_lock_irqsave(&pmic_arb->lock, flags);
+ pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
+ rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
+ PMIC_ARB_CHANNEL_OBS);
if (rc)
goto done;
- pa_read_data(pa, buf, offset + PMIC_ARB_RDATA0,
+ pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
min_t(u8, bc, 3));
if (bc > 3)
- pa_read_data(pa, buf + 4, offset + PMIC_ARB_RDATA1, bc - 4);
+ pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
+ bc - 4);
done:
- raw_spin_unlock_irqrestore(&pa->lock, flags);
+ raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
return rc;
}
static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
- u16 addr, const u8 *buf, size_t len)
+ u16 addr, const u8 *buf, size_t len)
{
- struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
unsigned long flags;
u8 bc = len - 1;
u32 cmd;
int rc;
u32 offset;
- mode_t mode;
-
- rc = pa->ver_ops->offset(pa, sid, addr, &offset);
- if (rc)
- return rc;
- rc = pa->ver_ops->mode(pa, sid, addr, &mode);
- if (rc)
+ rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
+ PMIC_ARB_CHANNEL_RW);
+ if (rc < 0)
return rc;
- if (!(mode & S_IWUSR)) {
- dev_err(&pa->spmic->dev,
- "error: impermissible write to peripheral sid:%d addr:0x%x\n",
- sid, addr);
- return -EPERM;
- }
-
+ offset = rc;
if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
- dev_err(&ctrl->dev,
- "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
+ dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
PMIC_ARB_MAX_TRANS_BYTES, len);
return -EINVAL;
}
@@ -429,7 +419,7 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
/* Check the opcode */
if (opc >= 0x40 && opc <= 0x5F)
opc = PMIC_ARB_OP_WRITE;
- else if (opc >= 0x00 && opc <= 0x0F)
+ else if (opc <= 0x0F)
opc = PMIC_ARB_OP_EXT_WRITE;
else if (opc >= 0x30 && opc <= 0x37)
opc = PMIC_ARB_OP_EXT_WRITEL;
@@ -438,18 +428,21 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
else
return -EINVAL;
- cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc);
+ cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
/* Write data to FIFOs */
- raw_spin_lock_irqsave(&pa->lock, flags);
- pa_write_data(pa, buf, offset + PMIC_ARB_WDATA0, min_t(u8, bc, 3));
+ raw_spin_lock_irqsave(&pmic_arb->lock, flags);
+ pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
+ min_t(u8, bc, 3));
if (bc > 3)
- pa_write_data(pa, buf + 4, offset + PMIC_ARB_WDATA1, bc - 4);
+ pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
+ bc - 4);
/* Start the transaction */
- pmic_arb_base_write(pa, offset + PMIC_ARB_CMD, cmd);
- rc = pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, addr);
- raw_spin_unlock_irqrestore(&pa->lock, flags);
+ pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
+ rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
+ PMIC_ARB_CHANNEL_RW);
+ raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
return rc;
}
@@ -475,67 +468,64 @@ struct spmi_pmic_arb_qpnpint_type {
static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
size_t len)
{
- struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
- u8 sid = HWIRQ_SID(d->hwirq);
- u8 per = HWIRQ_PER(d->hwirq);
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ u8 sid = hwirq_to_sid(d->hwirq);
+ u8 per = hwirq_to_per(d->hwirq);
- if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
+ if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
(per << 8) + reg, buf, len))
- dev_err_ratelimited(&pa->spmic->dev,
- "failed irqchip transaction on %x\n",
+ dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
d->irq);
}
static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
{
- struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
- u8 sid = HWIRQ_SID(d->hwirq);
- u8 per = HWIRQ_PER(d->hwirq);
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ u8 sid = hwirq_to_sid(d->hwirq);
+ u8 per = hwirq_to_per(d->hwirq);
- if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid,
+ if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
(per << 8) + reg, buf, len))
- dev_err_ratelimited(&pa->spmic->dev,
- "failed irqchip transaction on %x\n",
+ dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
d->irq);
}
-static void cleanup_irq(struct spmi_pmic_arb *pa, u16 apid, int id)
+static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
{
- u16 ppid = pa->apid_data[apid].ppid;
+ u16 ppid = pmic_arb->apid_data[apid].ppid;
u8 sid = ppid >> 8;
u8 per = ppid & 0xFF;
u8 irq_mask = BIT(id);
- writel_relaxed(irq_mask, pa->intr + pa->ver_ops->irq_clear(apid));
+ writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
- if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
+ if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
(per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
- dev_err_ratelimited(&pa->spmic->dev,
- "failed to ack irq_mask = 0x%x for ppid = %x\n",
+ dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
irq_mask, ppid);
- if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
+ if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
(per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
- dev_err_ratelimited(&pa->spmic->dev,
- "failed to ack irq_mask = 0x%x for ppid = %x\n",
+ dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
irq_mask, ppid);
}
-static void periph_interrupt(struct spmi_pmic_arb *pa, u16 apid)
+static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
{
unsigned int irq;
u32 status;
int id;
- u8 sid = (pa->apid_data[apid].ppid >> 8) & 0xF;
- u8 per = pa->apid_data[apid].ppid & 0xFF;
+ u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
+ u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
- status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid));
+ status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
while (status) {
id = ffs(status) - 1;
status &= ~BIT(id);
- irq = irq_find_mapping(pa->domain, HWIRQ(sid, per, id, apid));
+ irq = irq_find_mapping(pmic_arb->domain,
+ spec_to_hwirq(sid, per, id, apid));
if (irq == 0) {
- cleanup_irq(pa, apid, id);
+ cleanup_irq(pmic_arb, apid, id);
continue;
}
generic_handle_irq(irq);
@@ -544,27 +534,28 @@ static void periph_interrupt(struct spmi_pmic_arb *pa, u16 apid)
static void pmic_arb_chained_irq(struct irq_desc *desc)
{
- struct spmi_pmic_arb *pa = irq_desc_get_handler_data(desc);
+ struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
+ const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
struct irq_chip *chip = irq_desc_get_chip(desc);
- void __iomem *intr = pa->intr;
- int first = pa->min_apid >> 5;
- int last = pa->max_apid >> 5;
+ int first = pmic_arb->min_apid >> 5;
+ int last = pmic_arb->max_apid >> 5;
+ u8 ee = pmic_arb->ee;
u32 status, enable;
int i, id, apid;
chained_irq_enter(chip, desc);
for (i = first; i <= last; ++i) {
- status = readl_relaxed(intr +
- pa->ver_ops->owner_acc_status(pa->ee, i));
+ status = readl_relaxed(
+ ver_ops->owner_acc_status(pmic_arb, ee, i));
while (status) {
id = ffs(status) - 1;
status &= ~BIT(id);
apid = id + i * 32;
- enable = readl_relaxed(intr +
- pa->ver_ops->acc_enable(apid));
+ enable = readl_relaxed(
+ ver_ops->acc_enable(pmic_arb, apid));
if (enable & SPMI_PIC_ACC_ENABLE_BIT)
- periph_interrupt(pa, apid);
+ periph_interrupt(pmic_arb, apid);
}
}
@@ -573,12 +564,12 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
static void qpnpint_irq_ack(struct irq_data *d)
{
- struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
- u8 irq = HWIRQ_IRQ(d->hwirq);
- u16 apid = HWIRQ_APID(d->hwirq);
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ u8 irq = hwirq_to_irq(d->hwirq);
+ u16 apid = hwirq_to_apid(d->hwirq);
u8 data;
- writel_relaxed(BIT(irq), pa->intr + pa->ver_ops->irq_clear(apid));
+ writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
data = BIT(irq);
qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
@@ -586,7 +577,7 @@ static void qpnpint_irq_ack(struct irq_data *d)
static void qpnpint_irq_mask(struct irq_data *d)
{
- u8 irq = HWIRQ_IRQ(d->hwirq);
+ u8 irq = hwirq_to_irq(d->hwirq);
u8 data = BIT(irq);
qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
@@ -594,13 +585,14 @@ static void qpnpint_irq_mask(struct irq_data *d)
static void qpnpint_irq_unmask(struct irq_data *d)
{
- struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
- u8 irq = HWIRQ_IRQ(d->hwirq);
- u16 apid = HWIRQ_APID(d->hwirq);
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
+ u8 irq = hwirq_to_irq(d->hwirq);
+ u16 apid = hwirq_to_apid(d->hwirq);
u8 buf[2];
writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
- pa->intr + pa->ver_ops->acc_enable(apid));
+ ver_ops->acc_enable(pmic_arb, apid));
qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
if (!(buf[0] & BIT(irq))) {
@@ -618,44 +610,51 @@ static void qpnpint_irq_unmask(struct irq_data *d)
static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct spmi_pmic_arb_qpnpint_type type;
- u8 irq = HWIRQ_IRQ(d->hwirq);
- u8 bit_mask_irq = BIT(irq);
+ irq_flow_handler_t flow_handler;
+ u8 irq = hwirq_to_irq(d->hwirq);
qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
- type.type |= bit_mask_irq;
+ type.type |= BIT(irq);
if (flow_type & IRQF_TRIGGER_RISING)
- type.polarity_high |= bit_mask_irq;
+ type.polarity_high |= BIT(irq);
if (flow_type & IRQF_TRIGGER_FALLING)
- type.polarity_low |= bit_mask_irq;
+ type.polarity_low |= BIT(irq);
+
+ flow_handler = handle_edge_irq;
} else {
if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
(flow_type & (IRQF_TRIGGER_LOW)))
return -EINVAL;
- type.type &= ~bit_mask_irq; /* level trig */
+ type.type &= ~BIT(irq); /* level trig */
if (flow_type & IRQF_TRIGGER_HIGH)
- type.polarity_high |= bit_mask_irq;
+ type.polarity_high |= BIT(irq);
else
- type.polarity_low |= bit_mask_irq;
+ type.polarity_low |= BIT(irq);
+
+ flow_handler = handle_level_irq;
}
qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
-
- if (flow_type & IRQ_TYPE_EDGE_BOTH)
- irq_set_handler_locked(d, handle_edge_irq);
- else
- irq_set_handler_locked(d, handle_level_irq);
+ irq_set_handler_locked(d, flow_handler);
return 0;
}
+static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+
+ return irq_set_irq_wake(pmic_arb->irq, on);
+}
+
static int qpnpint_get_irqchip_state(struct irq_data *d,
enum irqchip_irq_state which,
bool *state)
{
- u8 irq = HWIRQ_IRQ(d->hwirq);
+ u8 irq = hwirq_to_irq(d->hwirq);
u8 status = 0;
if (which != IRQCHIP_STATE_LINE_LEVEL)
@@ -667,15 +666,34 @@ static int qpnpint_get_irqchip_state(struct irq_data *d,
return 0;
}
+static int qpnpint_irq_request_resources(struct irq_data *d)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ u16 periph = hwirq_to_per(d->hwirq);
+ u16 apid = hwirq_to_apid(d->hwirq);
+ u16 sid = hwirq_to_sid(d->hwirq);
+ u16 irq = hwirq_to_irq(d->hwirq);
+
+ if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
+ dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
+ sid, periph, irq, pmic_arb->ee,
+ pmic_arb->apid_data[apid].irq_ee);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
static struct irq_chip pmic_arb_irqchip = {
.name = "pmic_arb",
.irq_ack = qpnpint_irq_ack,
.irq_mask = qpnpint_irq_mask,
.irq_unmask = qpnpint_irq_unmask,
.irq_set_type = qpnpint_irq_set_type,
+ .irq_set_wake = qpnpint_irq_set_wake,
.irq_get_irqchip_state = qpnpint_get_irqchip_state,
- .flags = IRQCHIP_MASK_ON_SUSPEND
- | IRQCHIP_SKIP_SET_WAKE,
+ .irq_request_resources = qpnpint_irq_request_resources,
+ .flags = IRQCHIP_MASK_ON_SUSPEND,
};
static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
@@ -685,12 +703,11 @@ static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
unsigned long *out_hwirq,
unsigned int *out_type)
{
- struct spmi_pmic_arb *pa = d->host_data;
+ struct spmi_pmic_arb *pmic_arb = d->host_data;
+ u16 apid, ppid;
int rc;
- u16 apid;
- dev_dbg(&pa->spmic->dev,
- "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
+ dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
intspec[0], intspec[1], intspec[2]);
if (irq_domain_get_of_node(d) != controller)
@@ -700,25 +717,25 @@ static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
return -EINVAL;
- rc = pa->ver_ops->ppid_to_apid(pa, intspec[0],
- (intspec[1] << 8), &apid);
+ ppid = intspec[0] << 8 | intspec[1];
+ rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
if (rc < 0) {
- dev_err(&pa->spmic->dev,
- "failed to xlate sid = 0x%x, periph = 0x%x, irq = %x rc = %d\n",
+ dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
intspec[0], intspec[1], intspec[2], rc);
return rc;
}
+ apid = rc;
/* Keep track of {max,min}_apid for bounding search during interrupt */
- if (apid > pa->max_apid)
- pa->max_apid = apid;
- if (apid < pa->min_apid)
- pa->min_apid = apid;
+ if (apid > pmic_arb->max_apid)
+ pmic_arb->max_apid = apid;
+ if (apid < pmic_arb->min_apid)
+ pmic_arb->min_apid = apid;
- *out_hwirq = HWIRQ(intspec[0], intspec[1], intspec[2], apid);
+ *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
*out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
- dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
+ dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
return 0;
}
@@ -727,9 +744,9 @@ static int qpnpint_irq_domain_map(struct irq_domain *d,
unsigned int virq,
irq_hw_number_t hwirq)
{
- struct spmi_pmic_arb *pa = d->host_data;
+ struct spmi_pmic_arb *pmic_arb = d->host_data;
- dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
+ dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq);
irq_set_chip_data(virq, d->host_data);
@@ -737,24 +754,23 @@ static int qpnpint_irq_domain_map(struct irq_domain *d,
return 0;
}
-static int
-pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid)
+static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
{
- u16 ppid = sid << 8 | ((addr >> 8) & 0xFF);
- u32 *mapping_table = pa->mapping_table;
+ u32 *mapping_table = pmic_arb->mapping_table;
int index = 0, i;
u16 apid_valid;
+ u16 apid;
u32 data;
- apid_valid = pa->ppid_to_apid[ppid];
- if (apid_valid & PMIC_ARB_CHAN_VALID) {
- *apid = (apid_valid & ~PMIC_ARB_CHAN_VALID);
- return 0;
+ apid_valid = pmic_arb->ppid_to_apid[ppid];
+ if (apid_valid & PMIC_ARB_APID_VALID) {
+ apid = apid_valid & ~PMIC_ARB_APID_VALID;
+ return apid;
}
for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
- if (!test_and_set_bit(index, pa->mapping_table_valid))
- mapping_table[index] = readl_relaxed(pa->cnfg +
+ if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
+ mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
SPMI_MAPPING_TABLE_REG(index));
data = mapping_table[index];
@@ -763,21 +779,21 @@ pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid)
if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
} else {
- *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
- pa->ppid_to_apid[ppid]
- = *apid | PMIC_ARB_CHAN_VALID;
- pa->apid_data[*apid].ppid = ppid;
- return 0;
+ apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
+ pmic_arb->ppid_to_apid[ppid]
+ = apid | PMIC_ARB_APID_VALID;
+ pmic_arb->apid_data[apid].ppid = ppid;
+ return apid;
}
} else {
if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
} else {
- *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
- pa->ppid_to_apid[ppid]
- = *apid | PMIC_ARB_CHAN_VALID;
- pa->apid_data[*apid].ppid = ppid;
- return 0;
+ apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
+ pmic_arb->ppid_to_apid[ppid]
+ = apid | PMIC_ARB_APID_VALID;
+ pmic_arb->apid_data[apid].ppid = ppid;
+ return apid;
}
}
}
@@ -785,105 +801,178 @@ pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid)
return -ENODEV;
}
-static int
-pmic_arb_mode_v1_v3(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode)
-{
- *mode = S_IRUSR | S_IWUSR;
- return 0;
-}
-
/* v1 offset per ee */
-static int
-pmic_arb_offset_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u32 *offset)
+static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
{
- *offset = 0x800 + 0x80 * pa->channel;
- return 0;
+ return 0x800 + 0x80 * pmic_arb->channel;
}
-static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pa, u16 ppid)
+static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
{
+ struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
u32 regval, offset;
- u16 apid;
- u16 id;
-
- /*
- * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid.
- * ppid_to_apid is an in-memory invert of that table.
- */
- for (apid = pa->last_apid; apid < pa->max_periph; apid++) {
- regval = readl_relaxed(pa->cnfg +
- SPMI_OWNERSHIP_TABLE_REG(apid));
- pa->apid_data[apid].owner = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
+ u16 id, apid;
- offset = PMIC_ARB_REG_CHNL(apid);
- if (offset >= pa->core_size)
+ for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
+ offset = pmic_arb->ver_ops->apid_map_offset(apid);
+ if (offset >= pmic_arb->core_size)
break;
- regval = readl_relaxed(pa->core + offset);
+ regval = readl_relaxed(pmic_arb->cnfg +
+ SPMI_OWNERSHIP_TABLE_REG(apid));
+ apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
+ apidd->write_ee = apidd->irq_ee;
+
+ regval = readl_relaxed(pmic_arb->core + offset);
if (!regval)
continue;
id = (regval >> 8) & PMIC_ARB_PPID_MASK;
- pa->ppid_to_apid[id] = apid | PMIC_ARB_CHAN_VALID;
- pa->apid_data[apid].ppid = id;
+ pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
+ apidd->ppid = id;
if (id == ppid) {
- apid |= PMIC_ARB_CHAN_VALID;
+ apid |= PMIC_ARB_APID_VALID;
break;
}
}
- pa->last_apid = apid & ~PMIC_ARB_CHAN_VALID;
+ pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
return apid;
}
-
-static int
-pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid)
+static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
{
- u16 ppid = (sid << 8) | (addr >> 8);
u16 apid_valid;
- apid_valid = pa->ppid_to_apid[ppid];
- if (!(apid_valid & PMIC_ARB_CHAN_VALID))
- apid_valid = pmic_arb_find_apid(pa, ppid);
- if (!(apid_valid & PMIC_ARB_CHAN_VALID))
+ apid_valid = pmic_arb->ppid_to_apid[ppid];
+ if (!(apid_valid & PMIC_ARB_APID_VALID))
+ apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
+ if (!(apid_valid & PMIC_ARB_APID_VALID))
return -ENODEV;
- *apid = (apid_valid & ~PMIC_ARB_CHAN_VALID);
+ return apid_valid & ~PMIC_ARB_APID_VALID;
+}
+
+static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
+{
+ struct apid_data *apidd = pmic_arb->apid_data;
+ struct apid_data *prev_apidd;
+ u16 i, apid, ppid;
+ bool valid, is_irq_ee;
+ u32 regval, offset;
+
+ /*
+ * In order to allow multiple EEs to write to a single PPID in arbiter
+ * version 5, there is more than one APID mapped to each PPID.
+ * The owner field for each of these mappings specifies the EE which is
+ * allowed to write to the APID. The owner of the last (highest) APID
+ * for a given PPID will receive interrupts from the PPID.
+ */
+ for (i = 0; ; i++, apidd++) {
+ offset = pmic_arb->ver_ops->apid_map_offset(i);
+ if (offset >= pmic_arb->core_size)
+ break;
+
+ regval = readl_relaxed(pmic_arb->core + offset);
+ if (!regval)
+ continue;
+ ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
+ is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
+
+ regval = readl_relaxed(pmic_arb->cnfg +
+ SPMI_OWNERSHIP_TABLE_REG(i));
+ apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
+
+ apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
+
+ valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
+ apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
+ prev_apidd = &pmic_arb->apid_data[apid];
+
+ if (valid && is_irq_ee &&
+ prev_apidd->write_ee == pmic_arb->ee) {
+ /*
+ * Duplicate PPID mapping after the one for this EE;
+ * override the irq owner
+ */
+ prev_apidd->irq_ee = apidd->irq_ee;
+ } else if (!valid || is_irq_ee) {
+ /* First PPID mapping or duplicate for another EE */
+ pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
+ }
+
+ apidd->ppid = ppid;
+ pmic_arb->last_apid = i;
+ }
+
+ /* Dump the mapping table for debug purposes. */
+ dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
+ for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
+ apid = pmic_arb->ppid_to_apid[ppid];
+ if (apid & PMIC_ARB_APID_VALID) {
+ apid &= ~PMIC_ARB_APID_VALID;
+ apidd = &pmic_arb->apid_data[apid];
+ dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
+ ppid, apid, apidd->write_ee, apidd->irq_ee);
+ }
+ }
+
return 0;
}
-static int
-pmic_arb_mode_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode)
+static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+{
+ if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
+ return -ENODEV;
+
+ return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
+}
+
+/* v2 offset per ppid and per ee */
+static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
{
u16 apid;
+ u16 ppid;
int rc;
- rc = pmic_arb_ppid_to_apid_v2(pa, sid, addr, &apid);
+ ppid = sid << 8 | ((addr >> 8) & 0xFF);
+ rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
if (rc < 0)
return rc;
- *mode = 0;
- *mode |= S_IRUSR;
-
- if (pa->ee == pa->apid_data[apid].owner)
- *mode |= S_IWUSR;
- return 0;
+ apid = rc;
+ return 0x1000 * pmic_arb->ee + 0x8000 * apid;
}
-/* v2 offset per ppid and per ee */
-static int
-pmic_arb_offset_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u32 *offset)
+/*
+ * v5 offset per ee and per apid for observer channels and per apid for
+ * read/write channels.
+ */
+static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
{
u16 apid;
int rc;
+ u32 offset = 0;
+ u16 ppid = (sid << 8) | (addr >> 8);
- rc = pmic_arb_ppid_to_apid_v2(pa, sid, addr, &apid);
+ rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
if (rc < 0)
return rc;
- *offset = 0x1000 * pa->ee + 0x8000 * apid;
- return 0;
+ apid = rc;
+ switch (ch_type) {
+ case PMIC_ARB_CHANNEL_OBS:
+ offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
+ break;
+ case PMIC_ARB_CHANNEL_RW:
+ offset = 0x10000 * apid;
+ break;
+ }
+
+ return offset;
}
static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
@@ -896,55 +985,97 @@ static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
}
-static u32 pmic_arb_owner_acc_status_v1(u8 m, u16 n)
+static void __iomem *
+pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+{
+ return pmic_arb->intr + 0x20 * m + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+{
+ return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+{
+ return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+{
+ return pmic_arb->intr + 0x10000 * m + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->intr + 0x200 + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->intr + 0x1000 * n;
+}
+
+static void __iomem *
+pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
{
- return 0x20 * m + 0x4 * n;
+ return pmic_arb->wr_base + 0x100 + 0x10000 * n;
}
-static u32 pmic_arb_owner_acc_status_v2(u8 m, u16 n)
+static void __iomem *
+pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
{
- return 0x100000 + 0x1000 * m + 0x4 * n;
+ return pmic_arb->intr + 0x600 + 0x4 * n;
}
-static u32 pmic_arb_owner_acc_status_v3(u8 m, u16 n)
+static void __iomem *
+pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
{
- return 0x200000 + 0x1000 * m + 0x4 * n;
+ return pmic_arb->intr + 0x4 + 0x1000 * n;
}
-static u32 pmic_arb_acc_enable_v1(u16 n)
+static void __iomem *
+pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
{
- return 0x200 + 0x4 * n;
+ return pmic_arb->wr_base + 0x104 + 0x10000 * n;
}
-static u32 pmic_arb_acc_enable_v2(u16 n)
+static void __iomem *
+pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
{
- return 0x1000 * n;
+ return pmic_arb->intr + 0xA00 + 0x4 * n;
}
-static u32 pmic_arb_irq_status_v1(u16 n)
+static void __iomem *
+pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
{
- return 0x600 + 0x4 * n;
+ return pmic_arb->intr + 0x8 + 0x1000 * n;
}
-static u32 pmic_arb_irq_status_v2(u16 n)
+static void __iomem *
+pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
{
- return 0x4 + 0x1000 * n;
+ return pmic_arb->wr_base + 0x108 + 0x10000 * n;
}
-static u32 pmic_arb_irq_clear_v1(u16 n)
+static u32 pmic_arb_apid_map_offset_v2(u16 n)
{
- return 0xA00 + 0x4 * n;
+ return 0x800 + 0x4 * n;
}
-static u32 pmic_arb_irq_clear_v2(u16 n)
+static u32 pmic_arb_apid_map_offset_v5(u16 n)
{
- return 0x8 + 0x1000 * n;
+ return 0x900 + 0x4 * n;
}
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
.ver_str = "v1",
.ppid_to_apid = pmic_arb_ppid_to_apid_v1,
- .mode = pmic_arb_mode_v1_v3,
.non_data_cmd = pmic_arb_non_data_cmd_v1,
.offset = pmic_arb_offset_v1,
.fmt_cmd = pmic_arb_fmt_cmd_v1,
@@ -952,12 +1083,12 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 = {
.acc_enable = pmic_arb_acc_enable_v1,
.irq_status = pmic_arb_irq_status_v1,
.irq_clear = pmic_arb_irq_clear_v1,
+ .apid_map_offset = pmic_arb_apid_map_offset_v2,
};
static const struct pmic_arb_ver_ops pmic_arb_v2 = {
.ver_str = "v2",
.ppid_to_apid = pmic_arb_ppid_to_apid_v2,
- .mode = pmic_arb_mode_v2,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
.offset = pmic_arb_offset_v2,
.fmt_cmd = pmic_arb_fmt_cmd_v2,
@@ -965,12 +1096,12 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 = {
.acc_enable = pmic_arb_acc_enable_v2,
.irq_status = pmic_arb_irq_status_v2,
.irq_clear = pmic_arb_irq_clear_v2,
+ .apid_map_offset = pmic_arb_apid_map_offset_v2,
};
static const struct pmic_arb_ver_ops pmic_arb_v3 = {
.ver_str = "v3",
.ppid_to_apid = pmic_arb_ppid_to_apid_v2,
- .mode = pmic_arb_mode_v1_v3,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
.offset = pmic_arb_offset_v2,
.fmt_cmd = pmic_arb_fmt_cmd_v2,
@@ -978,6 +1109,20 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 = {
.acc_enable = pmic_arb_acc_enable_v2,
.irq_status = pmic_arb_irq_status_v2,
.irq_clear = pmic_arb_irq_clear_v2,
+ .apid_map_offset = pmic_arb_apid_map_offset_v2,
+};
+
+static const struct pmic_arb_ver_ops pmic_arb_v5 = {
+ .ver_str = "v5",
+ .ppid_to_apid = pmic_arb_ppid_to_apid_v5,
+ .non_data_cmd = pmic_arb_non_data_cmd_v2,
+ .offset = pmic_arb_offset_v5,
+ .fmt_cmd = pmic_arb_fmt_cmd_v2,
+ .owner_acc_status = pmic_arb_owner_acc_status_v5,
+ .acc_enable = pmic_arb_acc_enable_v5,
+ .irq_status = pmic_arb_irq_status_v5,
+ .irq_clear = pmic_arb_irq_clear_v5,
+ .apid_map_offset = pmic_arb_apid_map_offset_v5,
};
static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
@@ -987,37 +1132,34 @@ static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
static int spmi_pmic_arb_probe(struct platform_device *pdev)
{
- struct spmi_pmic_arb *pa;
+ struct spmi_pmic_arb *pmic_arb;
struct spmi_controller *ctrl;
struct resource *res;
void __iomem *core;
+ u32 *mapping_table;
u32 channel, ee, hw_ver;
int err;
- ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa));
+ ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
if (!ctrl)
return -ENOMEM;
- pa = spmi_controller_get_drvdata(ctrl);
- pa->spmic = ctrl;
+ pmic_arb = spmi_controller_get_drvdata(ctrl);
+ pmic_arb->spmic = ctrl;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
- pa->core_size = resource_size(res);
- if (pa->core_size <= 0x800) {
- dev_err(&pdev->dev, "core_size is smaller than 0x800. Failing Probe\n");
- err = -EINVAL;
- goto err_put_ctrl;
- }
-
core = devm_ioremap_resource(&ctrl->dev, res);
if (IS_ERR(core)) {
err = PTR_ERR(core);
goto err_put_ctrl;
}
- pa->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
- sizeof(*pa->ppid_to_apid), GFP_KERNEL);
- if (!pa->ppid_to_apid) {
+ pmic_arb->core_size = resource_size(res);
+
+ pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
+ sizeof(*pmic_arb->ppid_to_apid),
+ GFP_KERNEL);
+ if (!pmic_arb->ppid_to_apid) {
err = -ENOMEM;
goto err_put_ctrl;
}
@@ -1025,57 +1167,56 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
- pa->ver_ops = &pmic_arb_v1;
- pa->wr_base = core;
- pa->rd_base = core;
+ pmic_arb->ver_ops = &pmic_arb_v1;
+ pmic_arb->wr_base = core;
+ pmic_arb->rd_base = core;
} else {
- pa->core = core;
+ pmic_arb->core = core;
if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
- pa->ver_ops = &pmic_arb_v2;
+ pmic_arb->ver_ops = &pmic_arb_v2;
+ else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
+ pmic_arb->ver_ops = &pmic_arb_v3;
else
- pa->ver_ops = &pmic_arb_v3;
-
- /* the apid to ppid table starts at PMIC_ARB_REG_CHNL(0) */
- pa->max_periph = (pa->core_size - PMIC_ARB_REG_CHNL(0)) / 4;
+ pmic_arb->ver_ops = &pmic_arb_v5;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"obsrvr");
- pa->rd_base = devm_ioremap_resource(&ctrl->dev, res);
- if (IS_ERR(pa->rd_base)) {
- err = PTR_ERR(pa->rd_base);
+ pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(pmic_arb->rd_base)) {
+ err = PTR_ERR(pmic_arb->rd_base);
goto err_put_ctrl;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"chnls");
- pa->wr_base = devm_ioremap_resource(&ctrl->dev, res);
- if (IS_ERR(pa->wr_base)) {
- err = PTR_ERR(pa->wr_base);
+ pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(pmic_arb->wr_base)) {
+ err = PTR_ERR(pmic_arb->wr_base);
goto err_put_ctrl;
}
}
dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
- pa->ver_ops->ver_str, hw_ver);
+ pmic_arb->ver_ops->ver_str, hw_ver);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
- pa->intr = devm_ioremap_resource(&ctrl->dev, res);
- if (IS_ERR(pa->intr)) {
- err = PTR_ERR(pa->intr);
+ pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(pmic_arb->intr)) {
+ err = PTR_ERR(pmic_arb->intr);
goto err_put_ctrl;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
- pa->cnfg = devm_ioremap_resource(&ctrl->dev, res);
- if (IS_ERR(pa->cnfg)) {
- err = PTR_ERR(pa->cnfg);
+ pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(pmic_arb->cnfg)) {
+ err = PTR_ERR(pmic_arb->cnfg);
goto err_put_ctrl;
}
- pa->irq = platform_get_irq_byname(pdev, "periph_irq");
- if (pa->irq < 0) {
- err = pa->irq;
+ pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
+ if (pmic_arb->irq < 0) {
+ err = pmic_arb->irq;
goto err_put_ctrl;
}
@@ -1092,7 +1233,7 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
goto err_put_ctrl;
}
- pa->channel = channel;
+ pmic_arb->channel = channel;
err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
if (err) {
@@ -1106,39 +1247,47 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
goto err_put_ctrl;
}
- pa->ee = ee;
-
- pa->mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS - 1,
- sizeof(*pa->mapping_table), GFP_KERNEL);
- if (!pa->mapping_table) {
+ pmic_arb->ee = ee;
+ mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
+ sizeof(*mapping_table), GFP_KERNEL);
+ if (!mapping_table) {
err = -ENOMEM;
goto err_put_ctrl;
}
+ pmic_arb->mapping_table = mapping_table;
/* Initialize max_apid/min_apid to the opposite bounds, during
* the irq domain translation, we are sure to update these */
- pa->max_apid = 0;
- pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
+ pmic_arb->max_apid = 0;
+ pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
platform_set_drvdata(pdev, ctrl);
- raw_spin_lock_init(&pa->lock);
+ raw_spin_lock_init(&pmic_arb->lock);
ctrl->cmd = pmic_arb_cmd;
ctrl->read_cmd = pmic_arb_read_cmd;
ctrl->write_cmd = pmic_arb_write_cmd;
+ if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
+ err = pmic_arb_read_apid_map_v5(pmic_arb);
+ if (err) {
+ dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
+ err);
+ goto err_put_ctrl;
+ }
+ }
+
dev_dbg(&pdev->dev, "adding irq domain\n");
- pa->domain = irq_domain_add_tree(pdev->dev.of_node,
- &pmic_arb_irq_domain_ops, pa);
- if (!pa->domain) {
+ pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
+ &pmic_arb_irq_domain_ops, pmic_arb);
+ if (!pmic_arb->domain) {
dev_err(&pdev->dev, "unable to create irq_domain\n");
err = -ENOMEM;
goto err_put_ctrl;
}
- irq_set_chained_handler_and_data(pa->irq, pmic_arb_chained_irq, pa);
- enable_irq_wake(pa->irq);
-
+ irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
+ pmic_arb);
err = spmi_controller_add(ctrl);
if (err)
goto err_domain_remove;
@@ -1146,8 +1295,8 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
return 0;
err_domain_remove:
- irq_set_chained_handler_and_data(pa->irq, NULL, NULL);
- irq_domain_remove(pa->domain);
+ irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
+ irq_domain_remove(pmic_arb->domain);
err_put_ctrl:
spmi_controller_put(ctrl);
return err;
@@ -1156,10 +1305,10 @@ err_put_ctrl:
static int spmi_pmic_arb_remove(struct platform_device *pdev)
{
struct spmi_controller *ctrl = platform_get_drvdata(pdev);
- struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
spmi_controller_remove(ctrl);
- irq_set_chained_handler_and_data(pa->irq, NULL, NULL);
- irq_domain_remove(pa->domain);
+ irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
+ irq_domain_remove(pmic_arb->domain);
spmi_controller_put(ctrl);
return 0;
}