diff options
Diffstat (limited to 'drivers/staging/iio/accel')
| -rw-r--r-- | drivers/staging/iio/accel/Kconfig | 27 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/Makefile | 11 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/accel.h | 167 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/kxsd9.c | 395 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/lis3l02dq.h | 232 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/lis3l02dq_core.c | 926 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/lis3l02dq_ring.c | 600 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/sca3000.h | 298 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/sca3000_core.c | 1509 | ||||
| -rw-r--r-- | drivers/staging/iio/accel/sca3000_ring.c | 331 |
10 files changed, 4496 insertions, 0 deletions
diff --git a/drivers/staging/iio/accel/Kconfig b/drivers/staging/iio/accel/Kconfig new file mode 100644 index 000000000000..fef3da48276c --- /dev/null +++ b/drivers/staging/iio/accel/Kconfig @@ -0,0 +1,27 @@ +# +# Accelerometer drivers +# +comment "Accelerometers" + +config KXSD9 + tristate "Kionix KXSD9 Accelerometer Driver" + depends on SPI + help + Say yes here to build support for the Kionix KXSD9 accelerometer. + Currently this only supports the device via an SPI interface. + +config LIS3L02DQ + tristate "ST Microelectronics LIS3L02DQ Accelerometer Driver" + depends on SPI + help + Say yes here to build SPI support for the ST microelectronics + accelerometer. The driver supplies direct access via sysfs files + and an event interface via a character device. + +config SCA3000 + depends on IIO_RING_BUFFER + depends on SPI + tristate "VTI SCA3000 series accelerometers" + help + Say yes here to build support for the VTI SCA3000 series of SPI + accelerometers. These devices use a hardware ring buffer.
\ No newline at end of file diff --git a/drivers/staging/iio/accel/Makefile b/drivers/staging/iio/accel/Makefile new file mode 100644 index 000000000000..d5335f9094ad --- /dev/null +++ b/drivers/staging/iio/accel/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for industrial I/O accelerometer drivers +# +obj-$(CONFIG_KXSD9) += kxsd9.o + +lis3l02dq-y := lis3l02dq_core.o +lis3l02dq-$(CONFIG_IIO_RING_BUFFER) += lis3l02dq_ring.o +obj-$(CONFIG_LIS3L02DQ) += lis3l02dq.o + +sca3000-y := sca3000_core.o sca3000_ring.o +obj-$(CONFIG_SCA3000) += sca3000.o
\ No newline at end of file diff --git a/drivers/staging/iio/accel/accel.h b/drivers/staging/iio/accel/accel.h new file mode 100644 index 000000000000..811fa0527a43 --- /dev/null +++ b/drivers/staging/iio/accel/accel.h @@ -0,0 +1,167 @@ + +#include "../sysfs.h" + +/* Accelerometer types of attribute */ + +#define IIO_DEV_ATTR_ACCEL_X_OFFSET(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(accel_x_offset, _mode, _show, _store, _addr) + +#define IIO_DEV_ATTR_ACCEL_Y_OFFSET(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(accel_y_offset, _mode, _show, _store, _addr) + +#define IIO_DEV_ATTR_ACCEL_Z_OFFSET(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(accel_z_offset, _mode, _show, _store, _addr) + +#define IIO_DEV_ATTR_ACCEL_X_GAIN(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(accel_x_gain, _mode, _show, _store, _addr) + +#define IIO_DEV_ATTR_ACCEL_Y_GAIN(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(accel_y_gain, _mode, _show, _store, _addr) + +#define IIO_DEV_ATTR_ACCEL_Z_GAIN(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(accel_z_gain, _mode, _show, _store, _addr) + +#define IIO_DEV_ATTR_ACCEL_X(_show, _addr) \ + IIO_DEVICE_ATTR(accel_x, S_IRUGO, _show, NULL, _addr) + +#define IIO_DEV_ATTR_ACCEL_Y(_show, _addr) \ + IIO_DEVICE_ATTR(accel_y, S_IRUGO, _show, NULL, _addr) + +#define IIO_DEV_ATTR_ACCEL_Z(_show, _addr) \ + IIO_DEVICE_ATTR(accel_z, S_IRUGO, _show, NULL, _addr) + +/* Thresholds are somewhat chip dependent - may need quite a few defs here */ +/* For unified thesholds (shared across all directions */ + +/** + * IIO_DEV_ATTR_ACCEL_THRESH: unified threshold + * @_mode: read/write + * @_show: read detector threshold value + * @_store: write detector theshold value + * @_addr: driver specific data, typically a register address + * + * This one is for cases where as single threshold covers all directions + **/ +#define IIO_DEV_ATTR_ACCEL_THRESH(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(thresh, _mode, _show, _store, _addr) + +/** + * IIO_DEV_ATTR_ACCEL_THRESH_X: independant direction threshold, x axis + * @_mode: readable / writable + * @_show: read x axis detector theshold value + * @_store: write x axis detector threshold value + * @_addr: device driver dependant, typically a register address + **/ +#define IIO_DEV_ATTR_ACCEL_THRESH_X(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(thresh_accel_x, _mode, _show, _store, _addr) + +#define IIO_DEV_ATTR_ACCEL_THRESH_Y(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(thresh_accel_y, _mode, _show, _store, _addr) + +#define IIO_DEV_ATTR_ACCEL_THRESH_Z(_mode, _show, _store, _addr) \ + IIO_DEVICE_ATTR(thresh_accel_z, _mode, _show, _store, _addr) + + +/** + * IIO_EVENT_ATTR_ACCEL_X_HIGH: threshold event, x acceleration + * @_show: read x acceleration high threshold + * @_store: write x acceleration high threshold + * @_mask: device dependant, typically a bit mask + * @_handler: the iio_handler associated with this attribute + **/ +#define IIO_EVENT_ATTR_ACCEL_X_HIGH(_show, _store, _mask, _handler) \ + IIO_EVENT_ATTR(accel_x_high, _show, _store, _mask, _handler) + +/** + * IIO_EVENT_ATTR_ACCEL_X_HIGH_SH: threshold event, x accel high, shared handler + * @_evlist: event list used to share the handler + * @_show: attribute read + * @_store: attribute write + * @_mask: driver specific data, typically a bit mask + **/ +#define IIO_EVENT_ATTR_ACCEL_X_HIGH_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_x_high, _evlist, _show, _store, _mask) + +/** + * IIO_EVENT_CODE_ACCEL_X_HIGH - event code for x axis high accel threshold + **/ +#define IIO_EVENT_CODE_ACCEL_X_HIGH IIO_EVENT_CODE_ACCEL_BASE + +#define IIO_EVENT_ATTR_ACCEL_Y_HIGH(_show, _store, _mask, _handler) \ + IIO_EVENT_ATTR(accel_y_high, _show, _store, _mask, _handler) + +#define IIO_EVENT_ATTR_ACCEL_Y_HIGH_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_y_high, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_Y_HIGH (IIO_EVENT_CODE_ACCEL_BASE + 1) + +#define IIO_EVENT_ATTR_ACCEL_Z_HIGH(_show, _store, _mask, _handler) \ + IIO_EVENT_ATTR(accel_z_high, _show, _store, _mask, _handler) + +#define IIO_EVENT_ATTR_ACCEL_Z_HIGH_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_z_high, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_Z_HIGH (IIO_EVENT_CODE_ACCEL_BASE + 2) + +#define IIO_EVENT_ATTR_ACCEL_X_LOW(_show, _store, _mask, _handler) \ + IIO_EVENT_ATTR(accel_x_low, _show, _store, _mask, _handler) + +#define IIO_EVENT_ATTR_ACCEL_X_LOW_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_x_low, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_X_LOW (IIO_EVENT_CODE_ACCEL_BASE + 3) + +#define IIO_EVENT_ATTR_ACCEL_Y_LOW(_show, _store, _mask, _handler) \ + IIO_EVENT_ATTR(accel_y_low, _show, _store, _mask, _handler) + +#define IIO_EVENT_ATTR_ACCEL_Y_LOW_SH(_evlist, _show, _store, _mask)\ + IIO_EVENT_ATTR_SH(accel_y_low, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_Y_LOW (IIO_EVENT_CODE_ACCEL_BASE + 4) + +#define IIO_EVENT_ATTR_ACCEL_Z_LOW(_show, _store, _mask, _handler) \ + IIO_EVENT_ATTR(accel_z_low, _show, _store, _mask, _handler) + +#define IIO_EVENT_ATTR_ACCEL_Z_LOW_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_z_low, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_Z_LOW (IIO_EVENT_CODE_ACCEL_BASE + 5) + +#define IIO_EVENT_ATTR_FREE_FALL_DETECT(_show, _store, _mask, _handler) \ + IIO_EVENT_ATTR(free_fall, _show, _store, _mask, _handler) + +#define IIO_EVENT_ATTR_FREE_FALL_DETECT_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(free_fall, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_FREE_FALL (IIO_EVENT_CODE_ACCEL_BASE + 6) + + +#define IIO_EVENT_ATTR_ACCEL_X_ROC_HIGH_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_x_roc_high, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_X_ROC_HIGH (IIO_EVENT_CODE_ACCEL_BASE + 10) + +#define IIO_EVENT_ATTR_ACCEL_X_ROC_LOW_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_x_roc_low, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_X_ROC_LOW (IIO_EVENT_CODE_ACCEL_BASE + 11) + +#define IIO_EVENT_ATTR_ACCEL_Y_ROC_HIGH_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_y_roc_high, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_Y_ROC_HIGH (IIO_EVENT_CODE_ACCEL_BASE + 12) + +#define IIO_EVENT_ATTR_ACCEL_Y_ROC_LOW_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_y_roc_low, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_Y_ROC_LOW (IIO_EVENT_CODE_ACCEL_BASE + 13) + +#define IIO_EVENT_ATTR_ACCEL_Z_ROC_HIGH_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_z_roc_high, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_Z_ROC_HIGH (IIO_EVENT_CODE_ACCEL_BASE + 14) + +#define IIO_EVENT_ATTR_ACCEL_Z_ROC_LOW_SH(_evlist, _show, _store, _mask) \ + IIO_EVENT_ATTR_SH(accel_z_roc_low, _evlist, _show, _store, _mask) + +#define IIO_EVENT_CODE_ACCEL_Z_ROC_LOW (IIO_EVENT_CODE_ACCEL_BASE + 15) diff --git a/drivers/staging/iio/accel/kxsd9.c b/drivers/staging/iio/accel/kxsd9.c new file mode 100644 index 000000000000..33d16b6f7b50 --- /dev/null +++ b/drivers/staging/iio/accel/kxsd9.c @@ -0,0 +1,395 @@ +/* + * kxsd9.c simple support for the Kionix KXSD9 3D + * accelerometer. + * + * Copyright (c) 2008-2009 Jonathan Cameron <jic23@cam.ac.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The i2c interface is very similar, so shouldn't be a problem once + * I have a suitable wire made up. + * + * TODO: Support the motion detector + * Uses register address incrementing so could have a + * heavily optimized ring buffer access function. + */ + +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/fs.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/spi/spi.h> +#include <linux/sysfs.h> +#include <linux/rtc.h> +#include <linux/delay.h> + +#include "../iio.h" +#include "../sysfs.h" +#include "../adc/adc.h" +#include "accel.h" + +#define KXSD9_REG_X 0x00 +#define KXSD9_REG_Y 0x02 +#define KXSD9_REG_Z 0x04 +#define KXSD9_REG_AUX 0x06 +#define KXSD9_REG_RESET 0x0a +#define KXSD9_REG_CTRL_C 0x0c + +#define KXSD9_FS_8 0x00 +#define KXSD9_FS_6 0x01 +#define KXSD9_FS_4 0x02 +#define KXSD9_FS_2 0x03 +#define KXSD9_FS_MASK 0x03 + +#define KXSD9_REG_CTRL_B 0x0d +#define KXSD9_REG_CTRL_A 0x0e + +#define KXSD9_READ(a) (0x80 | (a)) +#define KXSD9_WRITE(a) (a) + +#define IIO_DEV_ATTR_ACCEL_SET_RANGE(_mode, _show, _store) \ + IIO_DEVICE_ATTR(accel_range, _mode, _show, _store, 0) + +#define KXSD9_STATE_RX_SIZE 2 +#define KXSD9_STATE_TX_SIZE 4 +/** + * struct kxsd9_state - device related storage + * @buf_lock: protect the rx and tx buffers. + * @indio_dev: associated industrial IO device + * @us: spi device + * @rx: single rx buffer storage + * @tx: single tx buffer storage + **/ +struct kxsd9_state { + struct mutex buf_lock; + struct iio_dev *indio_dev; + struct spi_device *us; + u8 *rx; + u8 *tx; +}; + +/* This may want to move to mili g to allow for non integer ranges */ +static ssize_t kxsd9_read_accel_range(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret; + ssize_t len = 0; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct kxsd9_state *st = indio_dev->dev_data; + struct spi_transfer xfer = { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + .tx_buf = st->tx, + .rx_buf = st->rx, + }; + struct spi_message msg; + + mutex_lock(&st->buf_lock); + st->tx[0] = KXSD9_READ(KXSD9_REG_CTRL_C); + st->tx[1] = 0; + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + ret = spi_sync(st->us, &msg); + if (ret) + goto error_ret; + + switch (st->rx[1] & KXSD9_FS_MASK) { + case KXSD9_FS_8: + len += sprintf(buf, "8\n"); + break; + case KXSD9_FS_6: + len += sprintf(buf, "6\n"); + break; + case KXSD9_FS_4: + len += sprintf(buf, "4\n"); + break; + case KXSD9_FS_2: + len += sprintf(buf, "2\n"); + break; + } + +error_ret: + mutex_unlock(&st->buf_lock); + + return ret ? ret : len; +} +static ssize_t kxsd9_write_accel_range(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + long readin; + struct spi_message msg; + int ret; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct kxsd9_state *st = indio_dev->dev_data; + u8 val; + struct spi_transfer xfers[] = { + { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + .tx_buf = st->tx, + .rx_buf = st->rx, + }, { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + .tx_buf = st->tx, + }, + }; + + ret = strict_strtol(buf, 10, &readin); + if (ret) + return ret; + switch (readin) { + case 8: + val = KXSD9_FS_8; + break; + case 6: + val = KXSD9_FS_6; + break; + case 4: + val = KXSD9_FS_4; + break; + case 2: + val = KXSD9_FS_2; + break; + default: + return -EINVAL; + } + mutex_lock(&st->buf_lock); + st->tx[0] = KXSD9_READ(KXSD9_REG_CTRL_C); + st->tx[1] = 0; + spi_message_init(&msg); + spi_message_add_tail(&xfers[0], &msg); + ret = spi_sync(st->us, &msg); + if (ret) + goto error_ret; + st->tx[0] = KXSD9_WRITE(KXSD9_REG_CTRL_C); + st->tx[1] = (st->rx[1] & ~KXSD9_FS_MASK) | val; + + spi_message_init(&msg); + spi_message_add_tail(&xfers[1], &msg); + ret = spi_sync(st->us, &msg); +error_ret: + mutex_unlock(&st->buf_lock); + return ret ? ret : len; +} +static ssize_t kxsd9_read_accel(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct spi_message msg; + int ret; + ssize_t len = 0; + u16 val; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct kxsd9_state *st = indio_dev->dev_data; + struct spi_transfer xfers[] = { + { + .bits_per_word = 8, + .len = 1, + .cs_change = 0, + .delay_usecs = 200, + .tx_buf = st->tx, + }, { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + .rx_buf = st->rx, + }, + }; + + mutex_lock(&st->buf_lock); + st->tx[0] = KXSD9_READ(this_attr->address); + spi_message_init(&msg); + spi_message_add_tail(&xfers[0], &msg); + spi_message_add_tail(&xfers[1], &msg); + ret = spi_sync(st->us, &msg); + if (ret) + goto error_ret; + val = (((u16)(st->rx[0])) << 8) | (st->rx[1] & 0xF0); + len = sprintf(buf, "%d\n", val); +error_ret: + mutex_unlock(&st->buf_lock); + + return ret ? ret : len; +} + +static IIO_DEV_ATTR_ACCEL_X(kxsd9_read_accel, KXSD9_REG_X); +static IIO_DEV_ATTR_ACCEL_Y(kxsd9_read_accel, KXSD9_REG_Y); +static IIO_DEV_ATTR_ACCEL_Z(kxsd9_read_accel, KXSD9_REG_Z); +static IIO_DEV_ATTR_ADC(0, kxsd9_read_accel, KXSD9_REG_AUX); +static IIO_DEV_ATTR_ACCEL_SET_RANGE(S_IRUGO | S_IWUSR, + kxsd9_read_accel_range, + kxsd9_write_accel_range); + +static struct attribute *kxsd9_attributes[] = { + &iio_dev_attr_accel_x.dev_attr.attr, + &iio_dev_attr_accel_y.dev_attr.attr, + &iio_dev_attr_accel_z.dev_attr.attr, + &iio_dev_attr_adc_0.dev_attr.attr, + &iio_dev_attr_accel_range.dev_attr.attr, + NULL, +}; + +static const struct attribute_group kxsd9_attribute_group = { + .attrs = kxsd9_attributes, +}; + +static int __devinit kxsd9_power_up(struct spi_device *spi) +{ + int ret; + struct spi_transfer xfers[2] = { + { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + }, { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + }, + }; + struct spi_message msg; + u8 *tx2; + u8 *tx = kmalloc(2, GFP_KERNEL); + + if (tx == NULL) { + ret = -ENOMEM; + goto error_ret; + } + tx2 = kmalloc(2, GFP_KERNEL); + if (tx2 == NULL) { + ret = -ENOMEM; + goto error_free_tx; + } + tx[0] = 0x0d; + tx[1] = 0x40; + + tx2[0] = 0x0c; + tx2[1] = 0x9b; + + xfers[0].tx_buf = tx; + xfers[1].tx_buf = tx2; + spi_message_init(&msg); + spi_message_add_tail(&xfers[0], &msg); + spi_message_add_tail(&xfers[1], &msg); + ret = spi_sync(spi, &msg); + + kfree(tx2); +error_free_tx: + kfree(tx); +error_ret: + return ret; + +}; + +static int __devinit kxsd9_probe(struct spi_device *spi) +{ + + struct kxsd9_state *st; + int ret = 0; + + st = kzalloc(sizeof(*st), GFP_KERNEL); + if (st == NULL) { + ret = -ENOMEM; + goto error_ret; + } + spi_set_drvdata(spi, st); + + st->rx = kmalloc(sizeof(*st->rx)*KXSD9_STATE_RX_SIZE, + GFP_KERNEL); + if (st->rx == NULL) { + ret = -ENOMEM; + goto error_free_st; + } + st->tx = kmalloc(sizeof(*st->tx)*KXSD9_STATE_TX_SIZE, + GFP_KERNEL); + if (st->tx == NULL) { + ret = -ENOMEM; + goto error_free_rx; + } + + st->us = spi; + mutex_init(&st->buf_lock); + st->indio_dev = iio_allocate_device(); + if (st->indio_dev == NULL) { + ret = -ENOMEM; + goto error_free_tx; + } + st->indio_dev->dev.parent = &spi->dev; + /* for now */ + st->indio_dev->num_interrupt_lines = 0; + st->indio_dev->event_attrs = NULL; + + st->indio_dev->attrs = &kxsd9_attribute_group; + st->indio_dev->dev_data = (void *)(st); + st->indio_dev->driver_module = THIS_MODULE; + st->indio_dev->modes = INDIO_DIRECT_MODE; + + ret = iio_device_register(st->indio_dev); + if (ret) + goto error_free_dev; + + spi->mode = SPI_MODE_0; + spi_setup(spi); + kxsd9_power_up(spi); + + return 0; + +error_free_dev: + iio_free_device(st->indio_dev); +error_free_tx: + kfree(st->tx); +error_free_rx: + kfree(st->rx); +error_free_st: + kfree(st); +error_ret: + return ret; +} + +static int __devexit kxsd9_remove(struct spi_device *spi) +{ + struct kxsd9_state *st = spi_get_drvdata(spi); + + iio_device_unregister(st->indio_dev); + kfree(st->tx); + kfree(st->rx); + kfree(st); + + return 0; +} + +static struct spi_driver kxsd9_driver = { + .driver = { + .name = "kxsd9", + .owner = THIS_MODULE, + }, + .probe = kxsd9_probe, + .remove = __devexit_p(kxsd9_remove), +}; + +static __init int kxsd9_spi_init(void) +{ + return spi_register_driver(&kxsd9_driver); +} +module_init(kxsd9_spi_init); + +static __exit void kxsd9_spi_exit(void) +{ + spi_unregister_driver(&kxsd9_driver); +} +module_exit(kxsd9_spi_exit); + +MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>"); +MODULE_DESCRIPTION("Kionix KXSD9 SPI driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/iio/accel/lis3l02dq.h b/drivers/staging/iio/accel/lis3l02dq.h new file mode 100644 index 000000000000..91a5375408c2 --- /dev/null +++ b/drivers/staging/iio/accel/lis3l02dq.h @@ -0,0 +1,232 @@ +/* + * LISL02DQ.h -- support STMicroelectronics LISD02DQ + * 3d 2g Linear Accelerometers via SPI + * + * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk> + * + * Loosely based upon tle62x0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef SPI_LIS3L02DQ_H_ +#define SPI_LIS3L02DQ_H_ +#define LIS3L02DQ_READ_REG(a) ((a) | 0x80) +#define LIS3L02DQ_WRITE_REG(a) a + +/* Calibration parameters */ +#define LIS3L02DQ_REG_OFFSET_X_ADDR 0x16 +#define LIS3L02DQ_REG_OFFSET_Y_ADDR 0x17 +#define LIS3L02DQ_REG_OFFSET_Z_ADDR 0x18 + +#define LIS3L02DQ_REG_GAIN_X_ADDR 0x19 +#define LIS3L02DQ_REG_GAIN_Y_ADDR 0x1A +#define LIS3L02DQ_REG_GAIN_Z_ADDR 0x1B + +/* Control Register (1 of 2) */ +#define LIS3L02DQ_REG_CTRL_1_ADDR 0x20 +/* Power ctrl - either bit set corresponds to on*/ +#define LIS3L02DQ_REG_CTRL_1_PD_ON 0xC0 + +/* Decimation Factor */ +#define LIS3L02DQ_DEC_MASK 0x30 +#define LIS3L02DQ_REG_CTRL_1_DF_128 0x00 +#define LIS3L02DQ_REG_CTRL_1_DF_64 0x10 +#define LIS3L02DQ_REG_CTRL_1_DF_32 0x20 +#define LIS3L02DQ_REG_CTRL_1_DF_8 (0x10 | 0x20) + +/* Self Test Enable */ +#define LIS3L02DQ_REG_CTRL_1_SELF_TEST_ON 0x08 + +/* Axes enable ctrls */ +#define LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE 0x04 +#define LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE 0x02 +#define LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE 0x01 + +/* Control Register (2 of 2) */ +#define LIS3L02DQ_REG_CTRL_2_ADDR 0x21 + +/* Block Data Update only after MSB and LSB read */ +#define LIS3L02DQ_REG_CTRL_2_BLOCK_UPDATE 0x40 + +/* Set to big endian output */ +#define LIS3L02DQ_REG_CTRL_2_BIG_ENDIAN 0x20 + +/* Reboot memory content */ +#define LIS3L02DQ_REG_CTRL_2_REBOOT_MEMORY 0x10 + +/* Interupt Enable - applies data ready to the RDY pad */ +#define LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT 0x08 + +/* Enable Data Ready Generation - relationship with previous unclear in docs */ +#define LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION 0x04 + +/* SPI 3 wire mode */ +#define LIS3L02DQ_REG_CTRL_2_THREE_WIRE_SPI_MODE 0x02 + +/* Data alignment, default is 12 bit right justified + * - option for 16 bit left justified */ +#define LIS3L02DQ_REG_CTRL_2_DATA_ALIGNMENT_16_BIT_LEFT_JUSTIFIED 0x01 + +/* Interupt related stuff */ +#define LIS3L02DQ_REG_WAKE_UP_CFG_ADDR 0x23 + +/* Switch from or combination fo conditions to and */ +#define LIS3L02DQ_REG_WAKE_UP_CFG_BOOLEAN_AND 0x80 + +/* Latch interupt request, + * if on ack must be given by reading the ack register */ +#define LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC 0x40 + +/* Z Interupt on High (above threshold)*/ +#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH 0x20 +/* Z Interupt on Low */ +#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW 0x10 +/* Y Interupt on High */ +#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_HIGH 0x08 +/* Y Interupt on Low */ +#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_LOW 0x04 +/* X Interupt on High */ +#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_HIGH 0x02 +/* X Interupt on Low */ +#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_LOW 0x01 + +/* Register that gives description of what caused interupt + * - latched if set in CFG_ADDRES */ +#define LIS3L02DQ_REG_WAKE_UP_SRC_ADDR 0x24 +/* top bit ignored */ +/* Interupt Active */ +#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_ACTIVATED 0x40 +/* Interupts that have been triggered */ +#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH 0x20 +#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW 0x10 +#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH 0x08 +#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW 0x04 +#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH 0x02 +#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW 0x01 + +#define LIS3L02DQ_REG_WAKE_UP_ACK_ADDR 0x25 + +/* Status register */ +#define LIS3L02DQ_REG_STATUS_ADDR 0x27 +/* XYZ axis data overrun - first is all overrun? */ +#define LIS3L02DQ_REG_STATUS_XYZ_OVERRUN 0x80 +#define LIS3L02DQ_REG_STATUS_Z_OVERRUN 0x40 +#define LIS3L02DQ_REG_STATUS_Y_OVERRUN 0x20 +#define LIS3L02DQ_REG_STATUS_X_OVERRUN 0x10 +/* XYZ new data available - first is all 3 available? */ +#define LIS3L02DQ_REG_STATUS_XYZ_NEW_DATA 0x08 +#define LIS3L02DQ_REG_STATUS_Z_NEW_DATA 0x04 +#define LIS3L02DQ_REG_STATUS_Y_NEW_DATA 0x02 +#define LIS3L02DQ_REG_STATUS_X_NEW_DATA 0x01 + +/* The accelerometer readings - low and high bytes. +Form of high byte dependant on justification set in ctrl reg */ +#define LIS3L02DQ_REG_OUT_X_L_ADDR 0x28 +#define LIS3L02DQ_REG_OUT_X_H_ADDR 0x29 +#define LIS3L02DQ_REG_OUT_Y_L_ADDR 0x2A +#define LIS3L02DQ_REG_OUT_Y_H_ADDR 0x2B +#define LIS3L02DQ_REG_OUT_Z_L_ADDR 0x2C +#define LIS3L02DQ_REG_OUT_Z_H_ADDR 0x2D + +/* Threshold values for all axes and both above and below thresholds + * - i.e. there is only one value */ +#define LIS3L02DQ_REG_THS_L_ADDR 0x2E +#define LIS3L02DQ_REG_THS_H_ADDR 0x2F + +#define LIS3L02DQ_DEFAULT_CTRL1 (LIS3L02DQ_REG_CTRL_1_PD_ON \ + | LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE \ + | LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE \ + | LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE \ + | LIS3L02DQ_REG_CTRL_1_DF_128) + +#define LIS3L02DQ_DEFAULT_CTRL2 0 + +#define LIS3L02DQ_MAX_TX 12 +#define LIS3L02DQ_MAX_RX 12 +/** + * struct lis3l02dq_state - device instance specific data + * @us: actual spi_device + * @work_trigger_to_ring: bh for triggered event handling + * @work_cont_thresh: CLEAN + * @inter: used to check if new interrupt has been triggered + * @last_timestamp: passing timestamp from th to bh of interrupt handler + * @indio_dev: industrial I/O device structure + * @trig: data ready trigger registered with iio + * @tx: transmit buffer + * @rx: recieve buffer + * @buf_lock: mutex to protect tx and rx + **/ +struct lis3l02dq_state { + struct spi_device *us; + struct work_struct work_trigger_to_ring; + struct iio_work_cont work_cont_thresh; + bool inter; + s64 last_timestamp; + struct iio_dev *indio_dev; + struct iio_trigger *trig; + u8 *tx; + u8 *rx; + struct mutex buf_lock; +}; + +int lis3l02dq_spi_read_reg_8(struct device *dev, + u8 reg_address, + u8 *val); + +int lis3l02dq_spi_write_reg_8(struct device *dev, + u8 reg_address, + u8 *val); +#define LIS3L02DQ_SCAN_ACC_X 0 +#define LIS3L02DQ_SCAN_ACC_Y 1 +#define LIS3L02DQ_SCAN_ACC_Z 2 + + +#ifdef CONFIG_IIO_RING_BUFFER +/* At the moment triggers are only used for ring buffer + * filling. This may change! + */ +void lis3l02dq_remove_trigger(struct iio_dev *indio_dev); +int lis3l02dq_probe_trigger(struct iio_dev *indio_dev); + +ssize_t lis3l02dq_read_accel_from_ring(struct device *dev, + struct device_attribute *attr, + char *buf); + + +int lis3l02dq_configure_ring(struct iio_dev *indio_dev); +void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev); + +int lis3l02dq_initialize_ring(struct iio_ring_buffer *ring); +void lis3l02dq_uninitialize_ring(struct iio_ring_buffer *ring); +#else /* CONFIG_IIO_RING_BUFFER */ + +static inline void lis3l02dq_remove_trigger(struct iio_dev *indio_dev) {}; +static inline int lis3l02dq_probe_trigger(struct iio_dev *indio_dev) +{ + return 0; +}; + +static inline ssize_t +lis3l02dq_read_accel_from_ring(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return 0; +}; + +static int lis3l02dq_configure_ring(struct iio_dev *indio_dev) +{ + return 0; +}; +static inline void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev) +{}; +static inline int lis3l02dq_initialize_ring(struct iio_ring_buffer *ring) +{ + return 0; +}; +static inline void lis3l02dq_uninitialize_ring(struct iio_ring_buffer *ring) {}; +#endif /* CONFIG_IIO_RING_BUFFER */ +#endif /* SPI_LIS3L02DQ_H_ */ diff --git a/drivers/staging/iio/accel/lis3l02dq_core.c b/drivers/staging/iio/accel/lis3l02dq_core.c new file mode 100644 index 000000000000..f008837e5a14 --- /dev/null +++ b/drivers/staging/iio/accel/lis3l02dq_core.c @@ -0,0 +1,926 @@ +/* + * lis3l02dq.c support STMicroelectronics LISD02DQ + * 3d 2g Linear Accelerometers via SPI + * + * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Settings: + * 16 bit left justified mode used. + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/workqueue.h> +#include <linux/mutex.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/spi/spi.h> + +#include <linux/sysfs.h> +#include <linux/list.h> + +#include "../iio.h" +#include "../sysfs.h" +#include "accel.h" + +#include "lis3l02dq.h" + +/* At the moment the spi framework doesn't allow global setting of cs_change. + * It's in the likely to be added comment at the top of spi.h. + * This means that use cannot be made of spi_write etc. + */ + +/** + * lis3l02dq_spi_read_reg_8() - read single byte from a single register + * @dev: device asosciated with child of actual device (iio_dev or iio_trig) + * @reg_address: the address of the register to be read + * @val: pass back the resulting value + **/ +int lis3l02dq_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val) +{ + int ret; + struct spi_message msg; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev); + struct spi_transfer xfer = { + .tx_buf = st->tx, + .rx_buf = st->rx, + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + }; + + mutex_lock(&st->buf_lock); + st->tx[0] = LIS3L02DQ_READ_REG(reg_address); + st->tx[1] = 0; + + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + ret = spi_sync(st->us, &msg); + *val = st->rx[1]; + mutex_unlock(&st->buf_lock); + + return ret; +} + +/** + * lis3l02dq_spi_write_reg_8() - write single byte to a register + * @dev: device associated with child of actual device (iio_dev or iio_trig) + * @reg_address: the address of the register to be writen + * @val: the value to write + **/ +int lis3l02dq_spi_write_reg_8(struct device *dev, + u8 reg_address, + u8 *val) +{ + int ret; + struct spi_message msg; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev); + struct spi_transfer xfer = { + .tx_buf = st->tx, + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + }; + + mutex_lock(&st->buf_lock); + st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address); + st->tx[1] = *val; + + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + ret = spi_sync(st->us, &msg); + mutex_unlock(&st->buf_lock); + + return ret; +} + +/** + * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers + * @dev: device associated with child of actual device (iio_dev or iio_trig) + * @reg_address: the address of the lower of the two registers. Second register + * is assumed to have address one greater. + * @val: value to be written + **/ +static int lis3l02dq_spi_write_reg_s16(struct device *dev, + u8 lower_reg_address, + s16 value) +{ + int ret; + struct spi_message msg; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev); + struct spi_transfer xfers[] = { { + .tx_buf = st->tx, + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + }, { + .tx_buf = st->tx + 2, + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + }, + }; + + mutex_lock(&st->buf_lock); + st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address); + st->tx[1] = value & 0xFF; + st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1); + st->tx[3] = (value >> 8) & 0xFF; + + spi_message_init(&msg); + spi_message_add_tail(&xfers[0], &msg); + spi_message_add_tail(&xfers[1], &msg); + ret = spi_sync(st->us, &msg); + mutex_unlock(&st->buf_lock); + + return ret; +} + +/** + * lisl302dq_spi_read_reg_s16() - write 2 bytes to a pair of registers + * @dev: device associated with child of actual device (iio_dev or iio_trig) + * @reg_address: the address of the lower of the two registers. Second register + * is assumed to have address one greater. + * @val: somewhere to pass back the value read + **/ +static int lis3l02dq_spi_read_reg_s16(struct device *dev, + u8 lower_reg_address, + s16 *val) +{ + struct spi_message msg; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev); + int ret; + struct spi_transfer xfers[] = { { + .tx_buf = st->tx, + .rx_buf = st->rx, + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + }, { + .tx_buf = st->tx + 2, + .rx_buf = st->rx + 2, + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + + }, + }; + + mutex_lock(&st->buf_lock); + st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address); + st->tx[1] = 0; + st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address+1); + st->tx[3] = 0; + + spi_message_init(&msg); + spi_message_add_tail(&xfers[0], &msg); + spi_message_add_tail(&xfers[1], &msg); + ret = spi_sync(st->us, &msg); + if (ret) { + dev_err(&st->us->dev, "problem when reading 16 bit register"); + goto error_ret; + } + *val = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8); + +error_ret: + mutex_unlock(&st->buf_lock); + return ret; +} + +/** + * lis3l02dq_read_signed() - attribute function used for 8 bit signed values + * @dev: the child device associated with the iio_dev or iio_trigger + * @attr: the attribute being processed + * @buf: buffer into which put the output string + **/ +static ssize_t lis3l02dq_read_signed(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret; + s8 val; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + + ret = lis3l02dq_spi_read_reg_8(dev, this_attr->address, (u8 *)&val); + + return ret ? ret : sprintf(buf, "%d\n", val); +} + +static ssize_t lis3l02dq_read_unsigned(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret; + u8 val; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + + ret = lis3l02dq_spi_read_reg_8(dev, this_attr->address, &val); + + return ret ? ret : sprintf(buf, "%d\n", val); +} + +static ssize_t lis3l02dq_write_signed(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + long valin; + s8 val; + int ret; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + + ret = strict_strtol(buf, 10, &valin); + if (ret) + goto error_ret; + val = valin; + ret = lis3l02dq_spi_write_reg_8(dev, this_attr->address, (u8 *)&val); + +error_ret: + return ret ? ret : len; +} + +static ssize_t lis3l02dq_write_unsigned(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + int ret; + ulong valin; + u8 val; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + + ret = strict_strtoul(buf, 10, &valin); + if (ret) + goto err_ret; + val = valin; + ret = lis3l02dq_spi_write_reg_8(dev, this_attr->address, &val); + +err_ret: + return ret ? ret : len; +} + +static ssize_t lis3l02dq_read_16bit_signed(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret; + s16 val = 0; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + + ret = lis3l02dq_spi_read_reg_s16(dev, this_attr->address, &val); + + if (ret) + return ret; + + return sprintf(buf, "%d\n", val); +} + +static ssize_t lis3l02dq_read_accel(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + ssize_t ret; + + /* Take the iio_dev status lock */ + mutex_lock(&indio_dev->mlock); + if (indio_dev->currentmode == INDIO_RING_TRIGGERED) + ret = lis3l02dq_read_accel_from_ring(dev, attr, buf); + else + ret = lis3l02dq_read_16bit_signed(dev, attr, buf); + mutex_unlock(&indio_dev->mlock); + + return ret; +} + +static ssize_t lis3l02dq_write_16bit_signed(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + int ret; + long val; + + ret = strict_strtol(buf, 10, &val); + if (ret) + goto error_ret; + ret = lis3l02dq_spi_write_reg_s16(dev, this_attr->address, val); + +error_ret: + return ret ? ret : len; +} + +static ssize_t lis3l02dq_read_frequency(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret, len = 0; + s8 t; + ret = lis3l02dq_spi_read_reg_8(dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + (u8 *)&t); + if (ret) + return ret; + t &= LIS3L02DQ_DEC_MASK; + switch (t) { + case LIS3L02DQ_REG_CTRL_1_DF_128: + len = sprintf(buf, "280\n"); + break; + case LIS3L02DQ_REG_CTRL_1_DF_64: + len = sprintf(buf, "560\n"); + break; + case LIS3L02DQ_REG_CTRL_1_DF_32: + len = sprintf(buf, "1120\n"); + break; + case LIS3L02DQ_REG_CTRL_1_DF_8: + len = sprintf(buf, "4480\n"); + break; + } + return len; +} + +static ssize_t lis3l02dq_write_frequency(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + long val; + int ret; + u8 t; + + ret = strict_strtol(buf, 10, &val); + if (ret) + return ret; + + mutex_lock(&indio_dev->mlock); + ret = lis3l02dq_spi_read_reg_8(dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + &t); + if (ret) + goto error_ret_mutex; + /* Wipe the bits clean */ + t &= ~LIS3L02DQ_DEC_MASK; + switch (val) { + case 280: + t |= LIS3L02DQ_REG_CTRL_1_DF_128; + break; + case 560: + t |= LIS3L02DQ_REG_CTRL_1_DF_64; + break; + case 1120: + t |= LIS3L02DQ_REG_CTRL_1_DF_32; + break; + case 4480: + t |= LIS3L02DQ_REG_CTRL_1_DF_8; + break; + default: + ret = -EINVAL; + goto error_ret_mutex; + }; + + ret = lis3l02dq_spi_write_reg_8(dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + &t); + +error_ret_mutex: + mutex_unlock(&indio_dev->mlock); + + return ret ? ret : len; +} + +static int lis3l02dq_initial_setup(struct lis3l02dq_state *st) +{ + int ret; + u8 val, valtest; + + st->us->mode = SPI_MODE_3; + + spi_setup(st->us); + + val = LIS3L02DQ_DEFAULT_CTRL1; + /* Write suitable defaults to ctrl1 */ + ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + &val); + if (ret) { + dev_err(&st->us->dev, "problem with setup control register 1"); + goto err_ret; + } + /* Repeat as sometimes doesn't work first time?*/ + ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + &val); + if (ret) { + dev_err(&st->us->dev, "problem with setup control register 1"); + goto err_ret; + } + + /* Read back to check this has worked acts as loose test of correct + * chip */ + ret = lis3l02dq_spi_read_reg_8(&st->indio_dev->dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + &valtest); + if (ret || (valtest != val)) { + dev_err(&st->indio_dev->dev, "device not playing ball"); + ret = -EINVAL; + goto err_ret; + } + + val = LIS3L02DQ_DEFAULT_CTRL2; + ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev, + LIS3L02DQ_REG_CTRL_2_ADDR, + &val); + if (ret) { + dev_err(&st->us->dev, "problem with setup control register 2"); + goto err_ret; + } + + val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC; + ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev, + LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, + &val); + if (ret) + dev_err(&st->us->dev, "problem with interrupt cfg register"); +err_ret: + + return ret; +} + +static IIO_DEV_ATTR_ACCEL_X_OFFSET(S_IWUSR | S_IRUGO, + lis3l02dq_read_signed, + lis3l02dq_write_signed, + LIS3L02DQ_REG_OFFSET_X_ADDR); + +static IIO_DEV_ATTR_ACCEL_Y_OFFSET(S_IWUSR | S_IRUGO, + lis3l02dq_read_signed, + lis3l02dq_write_signed, + LIS3L02DQ_REG_OFFSET_Y_ADDR); + +static IIO_DEV_ATTR_ACCEL_Z_OFFSET(S_IWUSR | S_IRUGO, + lis3l02dq_read_signed, + lis3l02dq_write_signed, + LIS3L02DQ_REG_OFFSET_Z_ADDR); + +static IIO_DEV_ATTR_ACCEL_X_GAIN(S_IWUSR | S_IRUGO, + lis3l02dq_read_unsigned, + lis3l02dq_write_unsigned, + LIS3L02DQ_REG_GAIN_X_ADDR); + +static IIO_DEV_ATTR_ACCEL_Y_GAIN(S_IWUSR | S_IRUGO, + lis3l02dq_read_unsigned, + lis3l02dq_write_unsigned, + LIS3L02DQ_REG_GAIN_Y_ADDR); + +static IIO_DEV_ATTR_ACCEL_Z_GAIN(S_IWUSR | S_IRUGO, + lis3l02dq_read_unsigned, + lis3l02dq_write_unsigned, + LIS3L02DQ_REG_GAIN_Z_ADDR); + +static IIO_DEV_ATTR_ACCEL_THRESH(S_IWUSR | S_IRUGO, + lis3l02dq_read_16bit_signed, + lis3l02dq_write_16bit_signed, + LIS3L02DQ_REG_THS_L_ADDR); + +/* RFC The reading method for these will change depending on whether + * ring buffer capture is in use. Is it worth making these take two + * functions and let the core handle which to call, or leave as in this + * driver where it is the drivers problem to manage this? + */ + +static IIO_DEV_ATTR_ACCEL_X(lis3l02dq_read_accel, + LIS3L02DQ_REG_OUT_X_L_ADDR); + +static IIO_DEV_ATTR_ACCEL_Y(lis3l02dq_read_accel, + LIS3L02DQ_REG_OUT_Y_L_ADDR); + +static IIO_DEV_ATTR_ACCEL_Z(lis3l02dq_read_accel, + LIS3L02DQ_REG_OUT_Z_L_ADDR); + +static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, + lis3l02dq_read_frequency, + lis3l02dq_write_frequency); + +static IIO_CONST_ATTR_AVAIL_SAMP_FREQ("280 560 1120 4480"); + +static ssize_t lis3l02dq_read_interrupt_config(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret; + s8 val; + struct iio_event_attr *this_attr = to_iio_event_attr(attr); + + ret = lis3l02dq_spi_read_reg_8(dev, + LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, + (u8 *)&val); + + return ret ? ret : sprintf(buf, "%d\n", + (val & this_attr->mask) ? 1 : 0);; +} + +static ssize_t lis3l02dq_write_interrupt_config(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_event_attr *this_attr = to_iio_event_attr(attr); + struct iio_dev *indio_dev = dev_get_drvdata(dev); + int ret, currentlyset, changed = 0; + u8 valold, controlold; + bool val; + + val = !(buf[0] == '0'); + + mutex_lock(&indio_dev->mlock); + /* read current value */ + ret = lis3l02dq_spi_read_reg_8(dev, + LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, + &valold); + if (ret) + goto error_mutex_unlock; + + /* read current control */ + ret = lis3l02dq_spi_read_reg_8(dev, + LIS3L02DQ_REG_CTRL_2_ADDR, + &controlold); + if (ret) + goto error_mutex_unlock; + currentlyset = !!(valold & this_attr->mask); + if (val == false && currentlyset) { + valold &= ~this_attr->mask; + changed = 1; + iio_remove_event_from_list(this_attr->listel, + &indio_dev->interrupts[0] + ->ev_list); + } else if (val == true && !currentlyset) { + changed = 1; + valold |= this_attr->mask; + iio_add_event_to_list(this_attr->listel, + &indio_dev->interrupts[0]->ev_list); + } + + if (changed) { + ret = lis3l02dq_spi_write_reg_8(dev, + LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, + &valold); + if (ret) + goto error_mutex_unlock; + /* This always enables the interrupt, even if we've remove the + * last thing using it. For this device we can use the reference + * count on the handler to tell us if anyone wants the interrupt + */ + controlold = this_attr->listel->refcount ? + (controlold | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) : + (controlold & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT); + ret = lis3l02dq_spi_write_reg_8(dev, + LIS3L02DQ_REG_CTRL_2_ADDR, + &controlold); + if (ret) + goto error_mutex_unlock; + } +error_mutex_unlock: + mutex_unlock(&indio_dev->mlock); + + return ret ? ret : len; +} + + +static int lis3l02dq_thresh_handler_th(struct iio_dev *dev_info, + int index, + s64 timestamp, + int no_test) +{ + struct lis3l02dq_state *st = dev_info->dev_data; + + /* Stash the timestamp somewhere convenient for the bh */ + st->last_timestamp = timestamp; + schedule_work(&st->work_cont_thresh.ws); + + return 0; +} + + +/* Unforunately it appears the interrupt won't clear unless you read from the + * src register. + */ +static void lis3l02dq_thresh_handler_bh_no_check(struct work_struct *work_s) +{ + struct iio_work_cont *wc + = container_of(work_s, struct iio_work_cont, ws_nocheck); + struct lis3l02dq_state *st = wc->st; + u8 t; + + lis3l02dq_spi_read_reg_8(&st->indio_dev->dev, + LIS3L02DQ_REG_WAKE_UP_SRC_ADDR, + &t); + + if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_Z_HIGH, + st->last_timestamp); + + if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_Z_LOW, + st->last_timestamp); + + if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_Y_HIGH, + st->last_timestamp); + + if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_Y_LOW, + st->last_timestamp); + + if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_X_HIGH, + st->last_timestamp); + + if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_X_LOW, + st->last_timestamp); + /* reenable the irq */ + enable_irq(st->us->irq); + /* Ack and allow for new interrupts */ + lis3l02dq_spi_read_reg_8(&st->indio_dev->dev, + LIS3L02DQ_REG_WAKE_UP_ACK_ADDR, + &t); + + return; +} + +/* A shared handler for a number of threshold types */ +IIO_EVENT_SH(threshold, &lis3l02dq_thresh_handler_th); + +IIO_EVENT_ATTR_ACCEL_X_HIGH_SH(iio_event_threshold, + lis3l02dq_read_interrupt_config, + lis3l02dq_write_interrupt_config, + LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_HIGH); + +IIO_EVENT_ATTR_ACCEL_Y_HIGH_SH(iio_event_threshold, + lis3l02dq_read_interrupt_config, + lis3l02dq_write_interrupt_config, + LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_HIGH); + +IIO_EVENT_ATTR_ACCEL_Z_HIGH_SH(iio_event_threshold, + lis3l02dq_read_interrupt_config, + lis3l02dq_write_interrupt_config, + LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH); + +IIO_EVENT_ATTR_ACCEL_X_LOW_SH(iio_event_threshold, + lis3l02dq_read_interrupt_config, + lis3l02dq_write_interrupt_config, + LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_LOW); + +IIO_EVENT_ATTR_ACCEL_Y_LOW_SH(iio_event_threshold, + lis3l02dq_read_interrupt_config, + lis3l02dq_write_interrupt_config, + LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_LOW); + +IIO_EVENT_ATTR_ACCEL_Z_LOW_SH(iio_event_threshold, + lis3l02dq_read_interrupt_config, + lis3l02dq_write_interrupt_config, + LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW); + +static struct attribute *lis3l02dq_event_attributes[] = { + &iio_event_attr_accel_x_high.dev_attr.attr, + &iio_event_attr_accel_y_high.dev_attr.attr, + &iio_event_attr_accel_z_high.dev_attr.attr, + &iio_event_attr_accel_x_low.dev_attr.attr, + &iio_event_attr_accel_y_low.dev_attr.attr, + &iio_event_attr_accel_z_low.dev_attr.attr, + NULL +}; + +static struct attribute_group lis3l02dq_event_attribute_group = { + .attrs = lis3l02dq_event_attributes, +}; + +static IIO_CONST_ATTR(name, "lis3l02dq"); + +static struct attribute *lis3l02dq_attributes[] = { + &iio_dev_attr_accel_x_offset.dev_attr.attr, + &iio_dev_attr_accel_y_offset.dev_attr.attr, + &iio_dev_attr_accel_z_offset.dev_attr.attr, + &iio_dev_attr_accel_x_gain.dev_attr.attr, + &iio_dev_attr_accel_y_gain.dev_attr.attr, + &iio_dev_attr_accel_z_gain.dev_attr.attr, + &iio_dev_attr_thresh.dev_attr.attr, + &iio_dev_attr_accel_x.dev_attr.attr, + &iio_dev_attr_accel_y.dev_attr.attr, + &iio_dev_attr_accel_z.dev_attr.attr, + &iio_dev_attr_sampling_frequency.dev_attr.attr, + &iio_const_attr_available_sampling_frequency.dev_attr.attr, + &iio_const_attr_name.dev_attr.attr, + NULL +}; + +static const struct attribute_group lis3l02dq_attribute_group = { + .attrs = lis3l02dq_attributes, +}; + +static int __devinit lis3l02dq_probe(struct spi_device *spi) +{ + int ret, regdone = 0; + struct lis3l02dq_state *st = kzalloc(sizeof *st, GFP_KERNEL); + if (!st) { + ret = -ENOMEM; + goto error_ret; + } + /* this is only used tor removal purposes */ + spi_set_drvdata(spi, st); + + /* Allocate the comms buffers */ + st->rx = kzalloc(sizeof(*st->rx)*LIS3L02DQ_MAX_RX, GFP_KERNEL); + if (st->rx == NULL) { + ret = -ENOMEM; + goto error_free_st; + } + st->tx = kzalloc(sizeof(*st->tx)*LIS3L02DQ_MAX_TX, GFP_KERNEL); + if (st->tx == NULL) { + ret = -ENOMEM; + goto error_free_rx; + } + st->us = spi; + mutex_init(&st->buf_lock); + /* setup the industrialio driver allocated elements */ + st->indio_dev = iio_allocate_device(); + if (st->indio_dev == NULL) { + ret = -ENOMEM; + goto error_free_tx; + } + + st->indio_dev->dev.parent = &spi->dev; + st->indio_dev->num_interrupt_lines = 1; + st->indio_dev->event_attrs = &lis3l02dq_event_attribute_group; + st->indio_dev->attrs = &lis3l02dq_attribute_group; + st->indio_dev->dev_data = (void *)(st); + st->indio_dev->driver_module = THIS_MODULE; + st->indio_dev->modes = INDIO_DIRECT_MODE; + + ret = lis3l02dq_configure_ring(st->indio_dev); + if (ret) + goto error_free_dev; + + ret = iio_device_register(st->indio_dev); + if (ret) + goto error_unreg_ring_funcs; + regdone = 1; + + ret = lis3l02dq_initialize_ring(st->indio_dev->ring); + if (ret) { + printk(KERN_ERR "failed to initialize the ring\n"); + goto error_unreg_ring_funcs; + } + + if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) { + /* This is a little unusual, in that the device seems + to need a full read of the interrupt source reg before + the interrupt will reset. + Hence the two handlers are the same */ + iio_init_work_cont(&st->work_cont_thresh, + lis3l02dq_thresh_handler_bh_no_check, + lis3l02dq_thresh_handler_bh_no_check, + LIS3L02DQ_REG_WAKE_UP_SRC_ADDR, + 0, + st); + st->inter = 0; + ret = iio_register_interrupt_line(spi->irq, + st->indio_dev, + 0, + IRQF_TRIGGER_RISING, + "lis3l02dq"); + if (ret) + goto error_uninitialize_ring; + + ret = lis3l02dq_probe_trigger(st->indio_dev); + if (ret) + goto error_unregister_line; + } + + /* Get the device into a sane initial state */ + ret = lis3l02dq_initial_setup(st); + if (ret) + goto error_remove_trigger; + return 0; + +error_remove_trigger: + if (st->indio_dev->modes & INDIO_RING_TRIGGERED) + lis3l02dq_remove_trigger(st->indio_dev); +error_unregister_line: + if (st->indio_dev->modes & INDIO_RING_TRIGGERED) + iio_unregister_interrupt_line(st->indio_dev, 0); +error_uninitialize_ring: + lis3l02dq_uninitialize_ring(st->indio_dev->ring); +error_unreg_ring_funcs: + lis3l02dq_unconfigure_ring(st->indio_dev); +error_free_dev: + if (regdone) + iio_device_unregister(st->indio_dev); + else + iio_free_device(st->indio_dev); +error_free_tx: + kfree(st->tx); +error_free_rx: + kfree(st->rx); +error_free_st: + kfree(st); +error_ret: + return ret; +} + +/* Power down the device */ +static int lis3l02dq_stop_device(struct iio_dev *indio_dev) +{ + int ret; + struct lis3l02dq_state *st = indio_dev->dev_data; + u8 val = 0; + + mutex_lock(&indio_dev->mlock); + ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + &val); + if (ret) { + dev_err(&st->us->dev, "problem with turning device off: ctrl1"); + goto err_ret; + } + + ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, + LIS3L02DQ_REG_CTRL_2_ADDR, + &val); + if (ret) + dev_err(&st->us->dev, "problem with turning device off: ctrl2"); +err_ret: + mutex_unlock(&indio_dev->mlock); + return ret; +} + +/* fixme, confirm ordering in this function */ +static int lis3l02dq_remove(struct spi_device *spi) +{ + int ret; + struct lis3l02dq_state *st = spi_get_drvdata(spi); + struct iio_dev *indio_dev = st->indio_dev; + + ret = lis3l02dq_stop_device(indio_dev); + if (ret) + goto err_ret; + + flush_scheduled_work(); + + lis3l02dq_remove_trigger(indio_dev); + if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) + iio_unregister_interrupt_line(indio_dev, 0); + + lis3l02dq_uninitialize_ring(indio_dev->ring); + lis3l02dq_unconfigure_ring(indio_dev); + iio_device_unregister(indio_dev); + kfree(st->tx); + kfree(st->rx); + kfree(st); + + return 0; + +err_ret: + return ret; +} + +static struct spi_driver lis3l02dq_driver = { + .driver = { + .name = "lis3l02dq", + .owner = THIS_MODULE, + }, + .probe = lis3l02dq_probe, + .remove = __devexit_p(lis3l02dq_remove), +}; + +static __init int lis3l02dq_init(void) +{ + return spi_register_driver(&lis3l02dq_driver); +} +module_init(lis3l02dq_init); + +static __exit void lis3l02dq_exit(void) +{ + spi_unregister_driver(&lis3l02dq_driver); +} +module_exit(lis3l02dq_exit); + +MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>"); +MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/iio/accel/lis3l02dq_ring.c b/drivers/staging/iio/accel/lis3l02dq_ring.c new file mode 100644 index 000000000000..a6b7c72a86f4 --- /dev/null +++ b/drivers/staging/iio/accel/lis3l02dq_ring.c @@ -0,0 +1,600 @@ +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/workqueue.h> +#include <linux/mutex.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/spi/spi.h> +#include <linux/sysfs.h> +#include <linux/list.h> + +#include "../iio.h" +#include "../sysfs.h" +#include "../ring_sw.h" +#include "accel.h" +#include "../trigger.h" +#include "lis3l02dq.h" + +/** + * combine_8_to_16() utility function to munge to u8s into u16 + **/ +static inline u16 combine_8_to_16(u8 lower, u8 upper) +{ + u16 _lower = lower; + u16 _upper = upper; + return _lower | (_upper << 8); +} + +/** + * lis3l02dq_scan_el_set_state() set whether a scan contains a given channel + * @scan_el: associtate iio scan element attribute + * @indio_dev: the device structure + * @bool: desired state + * + * mlock already held when this is called. + **/ +static int lis3l02dq_scan_el_set_state(struct iio_scan_el *scan_el, + struct iio_dev *indio_dev, + bool state) +{ + u8 t, mask; + int ret; + + ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + &t); + if (ret) + goto error_ret; + switch (scan_el->label) { + case LIS3L02DQ_REG_OUT_X_L_ADDR: + mask = LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE; + break; + case LIS3L02DQ_REG_OUT_Y_L_ADDR: + mask = LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE; + break; + case LIS3L02DQ_REG_OUT_Z_L_ADDR: + mask = LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE; + break; + default: + ret = -EINVAL; + goto error_ret; + } + + if (!(mask & t) == state) { + if (state) + t |= mask; + else + t &= ~mask; + ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, + LIS3L02DQ_REG_CTRL_1_ADDR, + &t); + } +error_ret: + return ret; + +} +static IIO_SCAN_EL_C(accel_x, LIS3L02DQ_SCAN_ACC_X, IIO_SIGNED(16), + LIS3L02DQ_REG_OUT_X_L_ADDR, + &lis3l02dq_scan_el_set_state); +static IIO_SCAN_EL_C(accel_y, LIS3L02DQ_SCAN_ACC_Y, IIO_SIGNED(16), + LIS3L02DQ_REG_OUT_Y_L_ADDR, + &lis3l02dq_scan_el_set_state); +static IIO_SCAN_EL_C(accel_z, LIS3L02DQ_SCAN_ACC_Z, IIO_SIGNED(16), + LIS3L02DQ_REG_OUT_Z_L_ADDR, + &lis3l02dq_scan_el_set_state); +static IIO_SCAN_EL_TIMESTAMP; + +static struct attribute *lis3l02dq_scan_el_attrs[] = { + &iio_scan_el_accel_x.dev_attr.attr, + &iio_scan_el_accel_y.dev_attr.attr, + &iio_scan_el_accel_z.dev_attr.attr, + &iio_scan_el_timestamp.dev_attr.attr, + NULL, +}; + +static struct attribute_group lis3l02dq_scan_el_group = { + .attrs = lis3l02dq_scan_el_attrs, + .name = "scan_elements", +}; + +/** + * lis3l02dq_poll_func_th() top half interrupt handler called by trigger + * @private_data: iio_dev + **/ +static void lis3l02dq_poll_func_th(struct iio_dev *indio_dev) +{ + struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev); + st->last_timestamp = indio_dev->trig->timestamp; + schedule_work(&st->work_trigger_to_ring); + /* Indicate that this interrupt is being handled */ + + /* Technically this is trigger related, but without this + * handler running there is currently now way for the interrupt + * to clear. + */ + st->inter = 1; +} + +/** + * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig + **/ +static int lis3l02dq_data_rdy_trig_poll(struct iio_dev *dev_info, + int index, + s64 timestamp, + int no_test) +{ + struct lis3l02dq_state *st = iio_dev_get_devdata(dev_info); + struct iio_trigger *trig = st->trig; + + trig->timestamp = timestamp; + iio_trigger_poll(trig); + + return IRQ_HANDLED; +} + +/* This is an event as it is a response to a physical interrupt */ +IIO_EVENT_SH(data_rdy_trig, &lis3l02dq_data_rdy_trig_poll); + +/** + * lis3l02dq_read_accel_from_ring() individual acceleration read from ring + **/ +ssize_t lis3l02dq_read_accel_from_ring(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_scan_el *el = NULL; + int ret, len = 0, i = 0; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + struct iio_dev *dev_info = dev_get_drvdata(dev); + s16 *data; + + while (dev_info->scan_el_attrs->attrs[i]) { + el = to_iio_scan_el((struct device_attribute *) + (dev_info->scan_el_attrs->attrs[i])); + /* label is in fact the address */ + if (el->label == this_attr->address) + break; + i++; + } + if (!dev_info->scan_el_attrs->attrs[i]) { + ret = -EINVAL; + goto error_ret; + } + /* If this element is in the scan mask */ + ret = iio_scan_mask_query(dev_info, el->number); + if (ret < 0) + goto error_ret; + if (ret) { + data = kmalloc(dev_info->ring->access.get_bpd(dev_info->ring), + GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + ret = dev_info->ring->access.read_last(dev_info->ring, + (u8 *)data); + if (ret) + goto error_free_data; + } else { + ret = -EINVAL; + goto error_ret; + } + len = iio_scan_mask_count_to_right(dev_info, el->number); + if (len < 0) { + ret = len; + goto error_free_data; + } + len = sprintf(buf, "ring %d\n", data[len]); +error_free_data: + kfree(data); +error_ret: + return ret ? ret : len; + +} + +static const u8 read_all_tx_array[] = +{ + LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0, + LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0, + LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0, + LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0, + LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0, + LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0, +}; + +/** + * lis3l02dq_read_all() Reads all channels currently selected + * @st: device specific state + * @rx_array: (dma capable) recieve array, must be at least + * 4*number of channels + **/ +int lis3l02dq_read_all(struct lis3l02dq_state *st, u8 *rx_array) +{ + struct spi_transfer *xfers; + struct spi_message msg; + int ret, i, j = 0; + + xfers = kzalloc((st->indio_dev->scan_count) * 2 + * sizeof(*xfers), GFP_KERNEL); + if (!xfers) + return -ENOMEM; + + mutex_lock(&st->buf_lock); + + for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++) { + if (st->indio_dev->scan_mask & (1 << i)) { + /* lower byte */ + xfers[j].tx_buf = st->tx + 2*j; + st->tx[2*j] = read_all_tx_array[i*4]; + st->tx[2*j + 1] = 0; + if (rx_array) + xfers[j].rx_buf = rx_array + j*2; + xfers[j].bits_per_word = 8; + xfers[j].len = 2; + xfers[j].cs_change = 1; + j++; + + /* upper byte */ + xfers[j].tx_buf = st->tx + 2*j; + st->tx[2*j] = read_all_tx_array[i*4 + 2]; + st->tx[2*j + 1] = 0; + if (rx_array) + xfers[j].rx_buf = rx_array + j*2; + xfers[j].bits_per_word = 8; + xfers[j].len = 2; + xfers[j].cs_change = 1; + j++; + } + } + /* After these are transmitted, the rx_buff should have + * values in alternate bytes + */ + spi_message_init(&msg); + for (j = 0; j < st->indio_dev->scan_count * 2; j++) + spi_message_add_tail(&xfers[j], &msg); + + ret = spi_sync(st->us, &msg); + mutex_unlock(&st->buf_lock); + kfree(xfers); + + return ret; +} + + +/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device + * specific to be rolled into the core. + */ +static void lis3l02dq_trigger_bh_to_ring(struct work_struct *work_s) +{ + struct lis3l02dq_state *st + = container_of(work_s, struct lis3l02dq_state, + work_trigger_to_ring); + + u8 *rx_array; + int i = 0; + u16 *data; + size_t datasize = st->indio_dev + ->ring->access.get_bpd(st->indio_dev->ring); + + data = kmalloc(datasize , GFP_KERNEL); + if (data == NULL) { + dev_err(&st->us->dev, "memory alloc failed in ring bh"); + return; + } + /* Due to interleaved nature of transmission this buffer must be + * twice the number of bytes, or 4 times the number of channels + */ + rx_array = kmalloc(4 * (st->indio_dev->scan_count), GFP_KERNEL); + if (rx_array == NULL) { + dev_err(&st->us->dev, "memory alloc failed in ring bh"); + kfree(data); + return; + } + + /* whilst trigger specific, if this read does nto occur the data + ready interrupt will not be cleared. Need to add a mechanism + to provide a dummy read function if this is not triggering on + the data ready function but something else is. + */ + st->inter = 0; + + if (st->indio_dev->scan_count) + if (lis3l02dq_read_all(st, rx_array) >= 0) + for (; i < st->indio_dev->scan_count; i++) + data[i] = combine_8_to_16(rx_array[i*4+1], + rx_array[i*4+3]); + /* Guaranteed to be aligned with 8 byte boundary */ + if (st->indio_dev->scan_timestamp) + *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp; + + st->indio_dev->ring->access.store_to(st->indio_dev->ring, + (u8 *)data, + st->last_timestamp); + + iio_trigger_notify_done(st->indio_dev->trig); + kfree(rx_array); + kfree(data); + + return; +} +/* in these circumstances is it better to go with unaligned packing and + * deal with the cost?*/ +static int lis3l02dq_data_rdy_ring_preenable(struct iio_dev *indio_dev) +{ + size_t size; + /* Check if there are any scan elements enabled, if not fail*/ + if (!(indio_dev->scan_count || indio_dev->scan_timestamp)) + return -EINVAL; + + if (indio_dev->ring->access.set_bpd) { + if (indio_dev->scan_timestamp) + if (indio_dev->scan_count) /* Timestamp and data */ + size = 2*sizeof(s64); + else /* Timestamp only */ + size = sizeof(s64); + else /* Data only */ + size = indio_dev->scan_count*sizeof(s16); + indio_dev->ring->access.set_bpd(indio_dev->ring, size); + } + + return 0; +} + +static int lis3l02dq_data_rdy_ring_postenable(struct iio_dev *indio_dev) +{ + return indio_dev->trig + ? iio_trigger_attach_poll_func(indio_dev->trig, + indio_dev->pollfunc) + : 0; +} + +static int lis3l02dq_data_rdy_ring_predisable(struct iio_dev *indio_dev) +{ + return indio_dev->trig + ? iio_trigger_dettach_poll_func(indio_dev->trig, + indio_dev->pollfunc) + : 0; +} + + +/* Caller responsible for locking as necessary. */ +static int __lis3l02dq_write_data_ready_config(struct device *dev, + struct + iio_event_handler_list *list, + bool state) +{ + int ret; + u8 valold; + bool currentlyset; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + +/* Get the current event mask register */ + ret = lis3l02dq_spi_read_reg_8(dev, + LIS3L02DQ_REG_CTRL_2_ADDR, + &valold); + if (ret) + goto error_ret; +/* Find out if data ready is already on */ + currentlyset + = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION; + +/* Disable requested */ + if (!state && currentlyset) { + + valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION; + /* The double write is to overcome a hardware bug?*/ + ret = lis3l02dq_spi_write_reg_8(dev, + LIS3L02DQ_REG_CTRL_2_ADDR, + &valold); + if (ret) + goto error_ret; + ret = lis3l02dq_spi_write_reg_8(dev, + LIS3L02DQ_REG_CTRL_2_ADDR, + &valold); + if (ret) + goto error_ret; + + iio_remove_event_from_list(list, + &indio_dev->interrupts[0] + ->ev_list); + +/* Enable requested */ + } else if (state && !currentlyset) { + /* if not set, enable requested */ + valold |= LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION; + iio_add_event_to_list(list, &indio_dev->interrupts[0]->ev_list); + ret = lis3l02dq_spi_write_reg_8(dev, + LIS3L02DQ_REG_CTRL_2_ADDR, + &valold); + if (ret) + goto error_ret; + } + + return 0; +error_ret: + return ret; +} + +/** + * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state + * + * If disabling the interrupt also does a final read to ensure it is clear. + * This is only important in some cases where the scan enable elements are + * switched before the ring is reenabled. + **/ +static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig, + bool state) +{ + struct lis3l02dq_state *st = trig->private_data; + int ret = 0; + u8 t; + __lis3l02dq_write_data_ready_config(&st->indio_dev->dev, + &iio_event_data_rdy_trig, + state); + if (state == false) { + /* possible quirk with handler currently worked around + by ensuring the work queue is empty */ + flush_scheduled_work(); + /* Clear any outstanding ready events */ + ret = lis3l02dq_read_all(st, NULL); + } + lis3l02dq_spi_read_reg_8(&st->indio_dev->dev, + LIS3L02DQ_REG_WAKE_UP_SRC_ADDR, + &t); + return ret; +} +static DEVICE_ATTR(name, S_IRUGO, iio_trigger_read_name, NULL); + +static struct attribute *lis3l02dq_trigger_attrs[] = { + &dev_attr_name.attr, + NULL, +}; + +static const struct attribute_group lis3l02dq_trigger_attr_group = { + .attrs = lis3l02dq_trigger_attrs, +}; + +/** + * lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger + * @trig: the datardy trigger + * + * As the trigger may occur on any data element being updated it is + * really rather likely to occur during the read from the previous + * trigger event. The only way to discover if this has occured on + * boards not supporting level interrupts is to take a look at the line. + * If it is indicating another interrupt and we don't seem to have a + * handler looking at it, then we need to notify the core that we need + * to tell the triggering core to try reading all these again. + **/ +static int lis3l02dq_trig_try_reen(struct iio_trigger *trig) +{ + struct lis3l02dq_state *st = trig->private_data; + enable_irq(st->us->irq); + /* If gpio still high (or high again) */ + if (gpio_get_value(irq_to_gpio(st->us->irq))) + if (st->inter == 0) { + /* already interrupt handler dealing with it */ + disable_irq_nosync(st->us->irq); + if (st->inter == 1) { + /* interrupt handler snuck in between test + * and disable */ + enable_irq(st->us->irq); + return 0; + } + return -EAGAIN; + } + /* irq reenabled so success! */ + return 0; +} + +int lis3l02dq_probe_trigger(struct iio_dev *indio_dev) +{ + int ret; + struct lis3l02dq_state *state = indio_dev->dev_data; + + state->trig = iio_allocate_trigger(); + state->trig->name = kmalloc(IIO_TRIGGER_NAME_LENGTH, GFP_KERNEL); + if (!state->trig->name) { + ret = -ENOMEM; + goto error_free_trig; + } + snprintf((char *)state->trig->name, + IIO_TRIGGER_NAME_LENGTH, + "lis3l02dq-dev%d", indio_dev->id); + state->trig->dev.parent = &state->us->dev; + state->trig->owner = THIS_MODULE; + state->trig->private_data = state; + state->trig->set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state; + state->trig->try_reenable = &lis3l02dq_trig_try_reen; + state->trig->control_attrs = &lis3l02dq_trigger_attr_group; + ret = iio_trigger_register(state->trig); + if (ret) + goto error_free_trig_name; + + return 0; + +error_free_trig_name: + kfree(state->trig->name); +error_free_trig: + iio_free_trigger(state->trig); + + return ret; +} + +void lis3l02dq_remove_trigger(struct iio_dev *indio_dev) +{ + struct lis3l02dq_state *state = indio_dev->dev_data; + + iio_trigger_unregister(state->trig); + kfree(state->trig->name); + iio_free_trigger(state->trig); +} + +void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev) +{ + kfree(indio_dev->pollfunc); + iio_sw_rb_free(indio_dev->ring); +} + +int lis3l02dq_configure_ring(struct iio_dev *indio_dev) +{ + int ret = 0; + struct lis3l02dq_state *st = indio_dev->dev_data; + struct iio_ring_buffer *ring; + INIT_WORK(&st->work_trigger_to_ring, lis3l02dq_trigger_bh_to_ring); + /* Set default scan mode */ + + iio_scan_mask_set(indio_dev, iio_scan_el_accel_x.number); + iio_scan_mask_set(indio_dev, iio_scan_el_accel_y.number); + iio_scan_mask_set(indio_dev, iio_scan_el_accel_z.number); + indio_dev->scan_timestamp = true; + + indio_dev->scan_el_attrs = &lis3l02dq_scan_el_group; + + ring = iio_sw_rb_allocate(indio_dev); + if (!ring) { + ret = -ENOMEM; + return ret; + } + indio_dev->ring = ring; + /* Effectively select the ring buffer implementation */ + iio_ring_sw_register_funcs(&ring->access); + ring->preenable = &lis3l02dq_data_rdy_ring_preenable; + ring->postenable = &lis3l02dq_data_rdy_ring_postenable; + ring->predisable = &lis3l02dq_data_rdy_ring_predisable; + ring->owner = THIS_MODULE; + + indio_dev->pollfunc = kzalloc(sizeof(*indio_dev->pollfunc), GFP_KERNEL); + if (indio_dev->pollfunc == NULL) { + ret = -ENOMEM; + goto error_iio_sw_rb_free;; + } + indio_dev->pollfunc->poll_func_main = &lis3l02dq_poll_func_th; + indio_dev->pollfunc->private_data = indio_dev; + indio_dev->modes |= INDIO_RING_TRIGGERED; + return 0; + +error_iio_sw_rb_free: + iio_sw_rb_free(indio_dev->ring); + return ret; +} + +int lis3l02dq_initialize_ring(struct iio_ring_buffer *ring) +{ + return iio_ring_buffer_register(ring); +} + +void lis3l02dq_uninitialize_ring(struct iio_ring_buffer *ring) +{ + iio_ring_buffer_unregister(ring); +} + + +int lis3l02dq_set_ring_length(struct iio_dev *indio_dev, int length) +{ + /* Set sensible defaults for the ring buffer */ + if (indio_dev->ring->access.set_length) + return indio_dev->ring->access.set_length(indio_dev->ring, 500); + return 0; +} + + diff --git a/drivers/staging/iio/accel/sca3000.h b/drivers/staging/iio/accel/sca3000.h new file mode 100644 index 000000000000..29e11da09572 --- /dev/null +++ b/drivers/staging/iio/accel/sca3000.h @@ -0,0 +1,298 @@ +/* + * sca3000.c -- support VTI sca3000 series accelerometers + * via SPI + * + * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk> + * + * Partly based upon tle62x0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Initial mode is direct measurement. + * + * Untested things + * + * Temperature reading (the e05 I'm testing with doesn't have a sensor) + * + * Free fall detection mode - supported but untested as I'm not droping my + * dubious wire rig far enough to test it. + * + * Unsupported as yet + * + * Time stamping of data from ring. Various ideas on how to do this but none + * are remotely simple. Suggestions welcome. + * + * Individual enabling disabling of channels going into ring buffer + * + * Overflow handling (this is signaled for all but 8 bit ring buffer mode.) + * + * Motion detector using AND combinations of signals. + * + * Note: Be very careful about not touching an register bytes marked + * as reserved on the data sheet. They really mean it as changing convents of + * some will cause the device to lock up. + * + * Known issues - on rare occasions the interrupts lock up. Not sure why as yet. + * Can probably alleviate this by reading the interrupt register on start, but + * that is really just brushing the problem under the carpet. + */ +#define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02) +#define SCA3000_READ_REG(a) ((a) << 2) + +#define SCA3000_REG_ADDR_REVID 0x00 +#define SCA3000_REVID_MAJOR_MASK 0xf0 +#define SCA3000_REVID_MINOR_MASK 0x0f + +#define SCA3000_REG_ADDR_STATUS 0x02 +#define SCA3000_LOCKED 0x20 +#define SCA3000_EEPROM_CS_ERROR 0x02 +#define SCA3000_SPI_FRAME_ERROR 0x01 + +/* All reads done using register decrement so no need to directly access LSBs */ +#define SCA3000_REG_ADDR_X_MSB 0x05 +#define SCA3000_REG_ADDR_Y_MSB 0x07 +#define SCA3000_REG_ADDR_Z_MSB 0x09 + +#define SCA3000_REG_ADDR_RING_OUT 0x0f + +/* Temp read untested - the e05 doesn't have the sensor */ +#define SCA3000_REG_ADDR_TEMP_MSB 0x13 + +#define SCA3000_REG_ADDR_MODE 0x14 +#define SCA3000_MODE_PROT_MASK 0x28 + +#define SCA3000_RING_BUF_ENABLE 0x80 +#define SCA3000_RING_BUF_8BIT 0x40 +/* Free fall detection triggers an interrupt if the acceleration + * is below a threshold for equivalent of 25cm drop + */ +#define SCA3000_FREE_FALL_DETECT 0x10 +#define SCA3000_MEAS_MODE_NORMAL 0x00 +#define SCA3000_MEAS_MODE_OP_1 0x01 +#define SCA3000_MEAS_MODE_OP_2 0x02 + +/* In motion detection mode the accelerations are band pass filtered + * (aprox 1 - 25Hz) and then a programmable theshold used to trigger + * and interrupt. + */ +#define SCA3000_MEAS_MODE_MOT_DET 0x03 + +#define SCA3000_REG_ADDR_BUF_COUNT 0x15 + +#define SCA3000_REG_ADDR_INT_STATUS 0x16 + +#define SCA3000_INT_STATUS_THREE_QUARTERS 0x80 +#define SCA3000_INT_STATUS_HALF 0x40 + +#define SCA3000_INT_STATUS_FREE_FALL 0x08 +#define SCA3000_INT_STATUS_Y_TRIGGER 0x04 +#define SCA3000_INT_STATUS_X_TRIGGER 0x02 +#define SCA3000_INT_STATUS_Z_TRIGGER 0x01 + +/* Used to allow accesss to multiplexed registers */ +#define SCA3000_REG_ADDR_CTRL_SEL 0x18 +/* Only available for SCA3000-D03 and SCA3000-D01 */ +#define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01 +#define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02 +#define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03 +#define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04 +#define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05 +/* BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device + will not function */ +#define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B +#define SCA3000_OUT_CTRL_PROT_MASK 0xE0 +#define SCA3000_OUT_CTRL_BUF_X_EN 0x10 +#define SCA3000_OUT_CTRL_BUF_Y_EN 0x08 +#define SCA3000_OUT_CTRL_BUF_Z_EN 0x04 +#define SCA3000_OUT_CTRL_BUF_DIV_4 0x02 +#define SCA3000_OUT_CTRL_BUF_DIV_2 0x01 + +/* Control which motion detector interrupts are on. + * For now only OR combinations are supported.x + */ +#define SCA3000_MD_CTRL_PROT_MASK 0xC0 +#define SCA3000_MD_CTRL_OR_Y 0x01 +#define SCA3000_MD_CTRL_OR_X 0x02 +#define SCA3000_MD_CTRL_OR_Z 0x04 +/* Currently unsupported */ +#define SCA3000_MD_CTRL_AND_Y 0x08 +#define SCA3000_MD_CTRL_AND_X 0x10 +#define SAC3000_MD_CTRL_AND_Z 0x20 + +/* Some control registers of complex access methods requiring this register to + * be used to remove a lock. + */ +#define SCA3000_REG_ADDR_UNLOCK 0x1e + +#define SCA3000_REG_ADDR_INT_MASK 0x21 +#define SCA3000_INT_MASK_PROT_MASK 0x1C + +#define SCA3000_INT_MASK_RING_THREE_QUARTER 0x80 +#define SCA3000_INT_MASK_RING_HALF 0x40 + +#define SCA3000_INT_MASK_ALL_INTS 0x02 +#define SCA3000_INT_MASK_ACTIVE_HIGH 0x01 +#define SCA3000_INT_MASK_ACTIVE_LOW 0x00 + +/* Values of mulipexed registers (write to ctrl_data after select) */ +#define SCA3000_REG_ADDR_CTRL_DATA 0x22 + +/* Measurment modes available on some sca3000 series chips. Code assumes others + * may become available in the future. + * + * Bypass - Bypass the low-pass filter in the signal channel so as to increase + * signal bandwidth. + * + * Narrow - Narrow low-pass filtering of the signal channel and half output + * data rate by decimation. + * + * Wide - Widen low-pass filtering of signal channel to increase bandwidth + */ +#define SCA3000_OP_MODE_BYPASS 0x01 +#define SCA3000_OP_MODE_NARROW 0x02 +#define SCA3000_OP_MODE_WIDE 0x04 +#define SCA3000_MAX_TX 6 +#define SCA3000_MAX_RX 2 + +/** + * struct sca3000_state - device instance state information + * @us: the associated spi device + * @info: chip variant information + * @indio_dev: device information used by the IIO core + * @interrupt_handler_ws: event interrupt handler for all events + * @last_timestamp: the timestamp of the last event + * @mo_det_use_count: reference counter for the motion detection unit + * @lock: lock used to protect elements of sca3000_state + * and the underlying device state. + * @bpse: number of bits per scan element + * @tx: dma-able transmit buffer + * @rx: dma-able receive buffer + **/ +struct sca3000_state { + struct spi_device *us; + const struct sca3000_chip_info *info; + struct iio_dev *indio_dev; + struct work_struct interrupt_handler_ws; + s64 last_timestamp; + int mo_det_use_count; + struct mutex lock; + int bpse; + u8 *tx; + /* not used during a ring buffer read */ + u8 *rx; +}; + +/** + * struct sca3000_chip_info - model dependant parameters + * @name: model identification + * @temp_output: some devices have temperature sensors. + * @measurement_mode_freq: normal mode sampling frequency + * @option_mode_1: first optional mode. Not all models have one + * @option_mode_1_freq: option mode 1 sampling frequency + * @option_mode_2: second optional mode. Not all chips have one + * @option_mode_2_freq: option mode 2 sampling frequency + * + * This structure is used to hold information about the functionality of a given + * sca3000 variant. + **/ +struct sca3000_chip_info { + const char *name; + bool temp_output; + int measurement_mode_freq; + int option_mode_1; + int option_mode_1_freq; + int option_mode_2; + int option_mode_2_freq; +}; + +/** + * sca3000_read_data() read a series of values from the device + * @dev: device + * @reg_address_high: start address (decremented read) + * @rx: pointer where recieved data is placed. Callee + * responsible for freeing this. + * @len: number of bytes to read + * + * The main lock must be held. + **/ +int sca3000_read_data(struct sca3000_state *st, + u8 reg_address_high, + u8 **rx_p, + int len); + +/** + * sca3000_write_reg() write a single register + * @address: address of register on chip + * @val: value to be written to register + * + * The main lock must be held. + **/ +int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val); + +/* Conversion function for use with the ring buffer when in 11bit mode */ +static inline int sca3000_11bit_convert(uint8_t msb, uint8_t lsb) +{ + int16_t val; + + val = ((lsb >> 3) & 0x1C) | (msb << 5); + val |= (val & (1 << 12)) ? 0xE000 : 0; + + return val; +}; + +static inline int sca3000_13bit_convert(uint8_t msb, uint8_t lsb) +{ + s16 val; + + val = ((lsb >> 3) & 0x1F) | (msb << 5); + /* sign fill */ + val |= (val & (1 << 12)) ? 0xE000 : 0; + + return val; +}; + + +#ifdef CONFIG_IIO_RING_BUFFER +/** + * sca3000_register_ring_funcs() setup the ring state change functions + **/ +void sca3000_register_ring_funcs(struct iio_dev *indio_dev); + +/** + * sca3000_configure_ring() - allocate and configure ring buffer + * @indio_dev: iio-core device whose ring is to be configured + * + * The hardware ring buffer needs far fewer ring buffer functions than + * a software one as a lot of things are handled automatically. + * This function also tells the iio core that our device supports a + * hardware ring buffer mode. + **/ +int sca3000_configure_ring(struct iio_dev *indio_dev); + +/** + * sca3000_unconfigure_ring() - deallocate the ring buffer + * @indio_dev: iio-core device whose ring we are freeing + **/ +void sca3000_unconfigure_ring(struct iio_dev *indio_dev); + +/** + * sca3000_ring_int_process() handles ring related event pushing and escalation + * @val: the event code + **/ +void sca3000_ring_int_process(u8 val, struct iio_ring_buffer *ring); + +#else +static inline void sca3000_register_ring_funcs(struct iio_dev *indio_dev) {}; + +static inline +int sca3000_register_ring_access_and_init(struct iio_dev *indio_dev) +{ + return 0; +}; + +static inline void sca3000_ring_int_process(u8 val, void *ring) {}; + +#endif + diff --git a/drivers/staging/iio/accel/sca3000_core.c b/drivers/staging/iio/accel/sca3000_core.c new file mode 100644 index 000000000000..e27e3b7d1003 --- /dev/null +++ b/drivers/staging/iio/accel/sca3000_core.c @@ -0,0 +1,1509 @@ +/* + * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * Copyright (c) 2009 Jonathan Cameron <jic23@cam.ac.uk> + * + * See industrialio/accels/sca3000.h for comments. + */ + +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/fs.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/spi/spi.h> +#include <linux/sysfs.h> +#include "../iio.h" +#include "../sysfs.h" +#include "../ring_generic.h" + +#include "accel.h" +#include "sca3000.h" + +enum sca3000_variant { + d01, + d03, + e02, + e04, + e05, + l01, +}; + +/* Note where option modes are not defined, the chip simply does not + * support any. + * Other chips in the sca3000 series use i2c and are not included here. + * + * Some of these devices are only listed in the family data sheet and + * do not actually appear to be available. + */ +static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = { + { + .name = "sca3000-d01", + .temp_output = true, + .measurement_mode_freq = 250, + .option_mode_1 = SCA3000_OP_MODE_BYPASS, + .option_mode_1_freq = 250, + }, { + /* No data sheet available - may be the same as the 3100-d03?*/ + .name = "sca3000-d03", + .temp_output = true, + }, { + .name = "sca3000-e02", + .measurement_mode_freq = 125, + .option_mode_1 = SCA3000_OP_MODE_NARROW, + .option_mode_1_freq = 63, + }, { + .name = "sca3000-e04", + .measurement_mode_freq = 100, + .option_mode_1 = SCA3000_OP_MODE_NARROW, + .option_mode_1_freq = 50, + .option_mode_2 = SCA3000_OP_MODE_WIDE, + .option_mode_2_freq = 400, + }, { + .name = "sca3000-e05", + .measurement_mode_freq = 200, + .option_mode_1 = SCA3000_OP_MODE_NARROW, + .option_mode_1_freq = 50, + .option_mode_2 = SCA3000_OP_MODE_WIDE, + .option_mode_2_freq = 400, + }, { + /* No data sheet available. + * Frequencies are unknown. + */ + .name = "sca3000-l01", + .temp_output = true, + .option_mode_1 = SCA3000_OP_MODE_BYPASS, + }, +}; + + +int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val) +{ + struct spi_transfer xfer = { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + .tx_buf = st->tx, + }; + struct spi_message msg; + + st->tx[0] = SCA3000_WRITE_REG(address); + st->tx[1] = val; + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + + return spi_sync(st->us, &msg); +} + +int sca3000_read_data(struct sca3000_state *st, + uint8_t reg_address_high, + u8 **rx_p, + int len) +{ + int ret; + struct spi_message msg; + struct spi_transfer xfer = { + .bits_per_word = 8, + .len = len + 1, + .cs_change = 1, + .tx_buf = st->tx, + }; + + *rx_p = kmalloc(len + 1, GFP_KERNEL); + if (*rx_p == NULL) { + ret = -ENOMEM; + goto error_ret; + } + xfer.rx_buf = *rx_p; + st->tx[0] = SCA3000_READ_REG(reg_address_high); + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + + ret = spi_sync(st->us, &msg); + + if (ret) { + dev_err(get_device(&st->us->dev), "problem reading register"); + goto error_free_rx; + } + + return 0; +error_free_rx: + kfree(*rx_p); +error_ret: + return ret; + +} +/** + * sca3000_reg_lock_on() test if the ctrl register lock is on + * + * Lock must be held. + **/ +static int sca3000_reg_lock_on(struct sca3000_state *st) +{ + u8 *rx; + int ret; + + ret = sca3000_read_data(st, SCA3000_REG_ADDR_STATUS, &rx, 1); + + if (ret < 0) + return ret; + ret = !(rx[1] & SCA3000_LOCKED); + kfree(rx); + + return ret; +} + +/** + * __sca3000_unlock_reg_lock() unlock the control registers + * + * Note the device does not appear to support doing this in a single transfer. + * This should only ever be used as part of ctrl reg read. + * Lock must be held before calling this + **/ +static int __sca3000_unlock_reg_lock(struct sca3000_state *st) +{ + struct spi_message msg; + struct spi_transfer xfer[3] = { + { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + .tx_buf = st->tx, + }, { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + .tx_buf = st->tx + 2, + }, { + .bits_per_word = 8, + .len = 2, + .cs_change = 1, + .tx_buf = st->tx + 4, + }, + }; + st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_ADDR_UNLOCK); + st->tx[1] = 0x00; + st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_ADDR_UNLOCK); + st->tx[3] = 0x50; + st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_ADDR_UNLOCK); + st->tx[5] = 0xA0; + spi_message_init(&msg); + spi_message_add_tail(&xfer[0], &msg); + spi_message_add_tail(&xfer[1], &msg); + spi_message_add_tail(&xfer[2], &msg); + + return spi_sync(st->us, &msg); +} + +/** + * sca3000_write_ctrl_reg() write to a lock protect ctrl register + * @sel: selects which registers we wish to write to + * @val: the value to be written + * + * Certain control registers are protected against overwriting by the lock + * register and use a shared write address. This function allows writing of + * these registers. + * Lock must be held. + **/ +static int sca3000_write_ctrl_reg(struct sca3000_state *st, + uint8_t sel, + uint8_t val) +{ + + int ret; + + ret = sca3000_reg_lock_on(st); + if (ret < 0) + goto error_ret; + if (ret) { + ret = __sca3000_unlock_reg_lock(st); + if (ret) + goto error_ret; + } + + /* Set the control select register */ + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_CTRL_SEL, sel); + if (ret) + goto error_ret; + + /* Write the actual value into the register */ + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_CTRL_DATA, val); + +error_ret: + return ret; +} + +/* Crucial that lock is called before calling this */ +/** + * sca3000_read_ctrl_reg() read from lock protected control register. + * + * Lock must be held. + **/ +static int sca3000_read_ctrl_reg(struct sca3000_state *st, + u8 ctrl_reg, + u8 **rx_p) +{ + int ret; + + ret = sca3000_reg_lock_on(st); + if (ret < 0) + goto error_ret; + if (ret) { + ret = __sca3000_unlock_reg_lock(st); + if (ret) + goto error_ret; + } + /* Set the control select register */ + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_CTRL_SEL, ctrl_reg); + if (ret) + goto error_ret; + ret = sca3000_read_data(st, SCA3000_REG_ADDR_CTRL_DATA, rx_p, 1); + +error_ret: + return ret; +} + +#ifdef SCA3000_DEBUG +/** + * sca3000_check_status() check the status register + * + * Only used for debugging purposes + **/ +static int sca3000_check_status(struct device *dev) +{ + u8 *rx; + int ret; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_STATUS, &rx, 1); + if (ret < 0) + goto error_ret; + if (rx[1] & SCA3000_EEPROM_CS_ERROR) + dev_err(dev, "eeprom error \n"); + if (rx[1] & SCA3000_SPI_FRAME_ERROR) + dev_err(dev, "Previous SPI Frame was corrupt\n"); + kfree(rx); + +error_ret: + mutex_unlock(&st->lock); + return ret; +} +#endif /* SCA3000_DEBUG */ + +/** + * sca3000_read_13bit_signed() sysfs interface to read 13 bit signed registers + * + * These are described as signed 12 bit on the data sheet, which appears + * to be a conventional 2's complement 13 bit. + **/ +static ssize_t sca3000_read_13bit_signed(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int len = 0, ret; + int val; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + u8 *rx; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + + mutex_lock(&st->lock); + ret = sca3000_read_data(st, this_attr->address, &rx, 2); + if (ret < 0) + goto error_ret; + val = sca3000_13bit_convert(rx[1], rx[2]); + len += sprintf(buf + len, "%d\n", val); + kfree(rx); +error_ret: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + + +static ssize_t sca3000_show_name(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *dev_info = dev_get_drvdata(dev); + struct sca3000_state *st = dev_info->dev_data; + return sprintf(buf, "%s\n", st->info->name); +} +/** + * sca3000_show_reg() - sysfs interface to read the chip revision number + **/ +static ssize_t sca3000_show_rev(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int len = 0, ret; + struct iio_dev *dev_info = dev_get_drvdata(dev); + struct sca3000_state *st = dev_info->dev_data; + + u8 *rx; + + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_REVID, &rx, 1); + if (ret < 0) + goto error_ret; + len += sprintf(buf + len, + "major=%d, minor=%d\n", + rx[1] & SCA3000_REVID_MAJOR_MASK, + rx[1] & SCA3000_REVID_MINOR_MASK); + kfree(rx); + +error_ret: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +/** + * sca3000_show_available_measurement_modes() display available modes + * + * This is all read from chip specific data in the driver. Not all + * of the sca3000 series support modes other than normal. + **/ +static ssize_t +sca3000_show_available_measurement_modes(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *dev_info = dev_get_drvdata(dev); + struct sca3000_state *st = dev_info->dev_data; + int len = 0; + + len += sprintf(buf + len, "0 - normal mode"); + switch (st->info->option_mode_1) { + case SCA3000_OP_MODE_NARROW: + len += sprintf(buf + len, ", 1 - narrow mode"); + break; + case SCA3000_OP_MODE_BYPASS: + len += sprintf(buf + len, ", 1 - bypass mode"); + break; + }; + switch (st->info->option_mode_2) { + case SCA3000_OP_MODE_WIDE: + len += sprintf(buf + len, ", 2 - wide mode"); + break; + } + /* always supported */ + len += sprintf(buf + len, " 3 - motion detection \n"); + + return len; +} + +/** + * sca3000_show_measurmenet_mode() sysfs read of current mode + **/ +static ssize_t +sca3000_show_measurement_mode(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *dev_info = dev_get_drvdata(dev); + struct sca3000_state *st = dev_info->dev_data; + int len = 0, ret; + u8 *rx; + + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (ret) + goto error_ret; + /* mask bottom 2 bits - only ones that are relevant */ + rx[1] &= 0x03; + switch (rx[1]) { + case SCA3000_MEAS_MODE_NORMAL: + len += sprintf(buf + len, "0 - normal mode\n"); + break; + case SCA3000_MEAS_MODE_MOT_DET: + len += sprintf(buf + len, "3 - motion detection\n"); + break; + case SCA3000_MEAS_MODE_OP_1: + switch (st->info->option_mode_1) { + case SCA3000_OP_MODE_NARROW: + len += sprintf(buf + len, "1 - narrow mode\n"); + break; + case SCA3000_OP_MODE_BYPASS: + len += sprintf(buf + len, "1 - bypass mode\n"); + break; + }; + break; + case SCA3000_MEAS_MODE_OP_2: + switch (st->info->option_mode_2) { + case SCA3000_OP_MODE_WIDE: + len += sprintf(buf + len, "2 - wide mode\n"); + break; + } + break; + }; + +error_ret: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +/** + * sca3000_store_measurement_mode() set the current mode + **/ +static ssize_t +sca3000_store_measurement_mode(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev *dev_info = dev_get_drvdata(dev); + struct sca3000_state *st = dev_info->dev_data; + int ret; + u8 *rx; + int mask = 0x03; + long val; + + mutex_lock(&st->lock); + ret = strict_strtol(buf, 10, &val); + if (ret) + goto error_ret; + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (ret) + goto error_ret; + rx[1] &= ~mask; + rx[1] |= (val & mask); + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, rx[1]); + if (ret) + goto error_free_rx; + mutex_unlock(&st->lock); + + return len; + +error_free_rx: + kfree(rx); +error_ret: + mutex_unlock(&st->lock); + + return ret; +} + + +/* Not even vaguely standard attributes so defined here rather than + * in the relevant IIO core headers + */ +static IIO_DEVICE_ATTR(available_measurement_modes, S_IRUGO, + sca3000_show_available_measurement_modes, + NULL, 0); + +static IIO_DEVICE_ATTR(measurement_mode, S_IRUGO | S_IWUSR, + sca3000_show_measurement_mode, + sca3000_store_measurement_mode, + 0); + +/* More standard attributes */ + +static IIO_DEV_ATTR_NAME(sca3000_show_name); +static IIO_DEV_ATTR_REV(sca3000_show_rev); + +static IIO_DEV_ATTR_ACCEL_X(sca3000_read_13bit_signed, + SCA3000_REG_ADDR_X_MSB); +static IIO_DEV_ATTR_ACCEL_Y(sca3000_read_13bit_signed, + SCA3000_REG_ADDR_Y_MSB); +static IIO_DEV_ATTR_ACCEL_Z(sca3000_read_13bit_signed, + SCA3000_REG_ADDR_Z_MSB); + + +/** + * sca3000_read_av_freq() sysfs function to get available frequencies + * + * The later modes are only relevant to the ring buffer - and depend on current + * mode. Note that data sheet gives rather wide tolerances for these so integer + * division will give good enough answer and not all chips have them specified + * at all. + **/ +static ssize_t sca3000_read_av_freq(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + int len = 0, ret; + u8 *rx; + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + mutex_unlock(&st->lock); + if (ret) + goto error_ret; + rx[1] &= 0x03; + switch (rx[1]) { + case SCA3000_MEAS_MODE_NORMAL: + len += sprintf(buf + len, "%d %d %d\n", + st->info->measurement_mode_freq, + st->info->measurement_mode_freq/2, + st->info->measurement_mode_freq/4); + break; + case SCA3000_MEAS_MODE_OP_1: + len += sprintf(buf + len, "%d %d %d\n", + st->info->option_mode_1_freq, + st->info->option_mode_1_freq/2, + st->info->option_mode_1_freq/4); + break; + case SCA3000_MEAS_MODE_OP_2: + len += sprintf(buf + len, "%d %d %d\n", + st->info->option_mode_2_freq, + st->info->option_mode_2_freq/2, + st->info->option_mode_2_freq/4); + break; + }; + kfree(rx); + return len; +error_ret: + return ret; +} +/** + * __sca3000_get_base_frequency() obtain mode specific base frequency + * + * lock must be held + **/ +static inline int __sca3000_get_base_freq(struct sca3000_state *st, + const struct sca3000_chip_info *info, + int *base_freq) +{ + int ret; + u8 *rx; + + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (ret) + goto error_ret; + switch (0x03 & rx[1]) { + case SCA3000_MEAS_MODE_NORMAL: + *base_freq = info->measurement_mode_freq; + break; + case SCA3000_MEAS_MODE_OP_1: + *base_freq = info->option_mode_1_freq; + break; + case SCA3000_MEAS_MODE_OP_2: + *base_freq = info->option_mode_2_freq; + break; + }; + kfree(rx); +error_ret: + return ret; +} + +/** + * sca3000_read_frequency() sysfs interface to get the current frequency + **/ +static ssize_t sca3000_read_frequency(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + int ret, len = 0, base_freq = 0; + u8 *rx; + mutex_lock(&st->lock); + ret = __sca3000_get_base_freq(st, st->info, &base_freq); + if (ret) + goto error_ret_mut; + ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL, &rx); + mutex_unlock(&st->lock); + if (ret) + goto error_ret; + if (base_freq > 0) + switch (rx[1]&0x03) { + case 0x00: + case 0x03: + len = sprintf(buf, "%d\n", base_freq); + break; + case 0x01: + len = sprintf(buf, "%d\n", base_freq/2); + break; + case 0x02: + len = sprintf(buf, "%d\n", base_freq/4); + break; + }; + kfree(rx); + return len; +error_ret_mut: + mutex_unlock(&st->lock); +error_ret: + return ret; +} + +/** + * sca3000_set_frequency() sysfs interface to set the current frequency + **/ +static ssize_t sca3000_set_frequency(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + int ret, base_freq = 0; + u8 *rx; + long val; + + ret = strict_strtol(buf, 10, &val); + if (ret) + return ret; + + mutex_lock(&st->lock); + /* What mode are we in? */ + ret = __sca3000_get_base_freq(st, st->info, &base_freq); + if (ret) + goto error_free_lock; + + ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL, &rx); + if (ret) + goto error_free_lock; + /* clear the bits */ + rx[1] &= ~0x03; + + if (val == base_freq/2) { + rx[1] |= SCA3000_OUT_CTRL_BUF_DIV_2; + } else if (val == base_freq/4) { + rx[1] |= SCA3000_OUT_CTRL_BUF_DIV_4; + } else if (val != base_freq) { + ret = -EINVAL; + goto error_free_lock; + } + ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL, rx[1]); +error_free_lock: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +/* Should only really be registered if ring buffer support is compiled in. + * Does no harm however and doing it right would add a fair bit of complexity + */ +static IIO_DEV_ATTR_AVAIL_SAMP_FREQ(sca3000_read_av_freq); + +static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, + sca3000_read_frequency, + sca3000_set_frequency); + + +/** + * sca3000_read_temp() sysfs interface to get the temperature when available + * +* The alignment of data in here is downright odd. See data sheet. +* Converting this into a meaningful value is left to inline functions in +* userspace part of header. +**/ +static ssize_t sca3000_read_temp(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + int len = 0, ret; + int val; + u8 *rx; + ret = sca3000_read_data(st, SCA3000_REG_ADDR_TEMP_MSB, &rx, 2); + if (ret < 0) + goto error_ret; + val = ((rx[1]&0x3F) << 3) | ((rx[2] & 0xE0) >> 5); + len += sprintf(buf + len, "%d\n", val); + kfree(rx); + + return len; + +error_ret: + return ret; +} +static IIO_DEV_ATTR_TEMP(sca3000_read_temp); + +/** + * sca3000_show_thresh() sysfs query of a theshold + **/ +static ssize_t sca3000_show_thresh(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + int len = 0, ret; + u8 *rx; + + mutex_lock(&st->lock); + ret = sca3000_read_ctrl_reg(st, + this_attr->address, + &rx); + mutex_unlock(&st->lock); + if (ret) + return ret; + len += sprintf(buf + len, "%d\n", rx[1]); + kfree(rx); + + return len; +} + +/** + * sca3000_write_thresh() sysfs control of threshold + **/ +static ssize_t sca3000_write_thresh(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + int ret; + long val; + + ret = strict_strtol(buf, 10, &val); + if (ret) + return ret; + mutex_lock(&st->lock); + ret = sca3000_write_ctrl_reg(st, this_attr->address, val); + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +static IIO_DEV_ATTR_ACCEL_THRESH_X(S_IRUGO | S_IWUSR, + sca3000_show_thresh, + sca3000_write_thresh, + SCA3000_REG_CTRL_SEL_MD_X_TH); +static IIO_DEV_ATTR_ACCEL_THRESH_Y(S_IRUGO | S_IWUSR, + sca3000_show_thresh, + sca3000_write_thresh, + SCA3000_REG_CTRL_SEL_MD_Y_TH); +static IIO_DEV_ATTR_ACCEL_THRESH_Z(S_IRUGO | S_IWUSR, + sca3000_show_thresh, + sca3000_write_thresh, + SCA3000_REG_CTRL_SEL_MD_Z_TH); + +static struct attribute *sca3000_attributes[] = { + &iio_dev_attr_name.dev_attr.attr, + &iio_dev_attr_revision.dev_attr.attr, + &iio_dev_attr_accel_x.dev_attr.attr, + &iio_dev_attr_accel_y.dev_attr.attr, + &iio_dev_attr_accel_z.dev_attr.attr, + &iio_dev_attr_thresh_accel_x.dev_attr.attr, + &iio_dev_attr_thresh_accel_y.dev_attr.attr, + &iio_dev_attr_thresh_accel_z.dev_attr.attr, + &iio_dev_attr_available_measurement_modes.dev_attr.attr, + &iio_dev_attr_measurement_mode.dev_attr.attr, + &iio_dev_attr_available_sampling_frequency.dev_attr.attr, + &iio_dev_attr_sampling_frequency.dev_attr.attr, + NULL, +}; + +static struct attribute *sca3000_attributes_with_temp[] = { + &iio_dev_attr_name.dev_attr.attr, + &iio_dev_attr_revision.dev_attr.attr, + &iio_dev_attr_accel_x.dev_attr.attr, + &iio_dev_attr_accel_y.dev_attr.attr, + &iio_dev_attr_accel_z.dev_attr.attr, + &iio_dev_attr_thresh_accel_x.dev_attr.attr, + &iio_dev_attr_thresh_accel_y.dev_attr.attr, + &iio_dev_attr_thresh_accel_z.dev_attr.attr, + &iio_dev_attr_available_measurement_modes.dev_attr.attr, + &iio_dev_attr_measurement_mode.dev_attr.attr, + &iio_dev_attr_available_sampling_frequency.dev_attr.attr, + &iio_dev_attr_sampling_frequency.dev_attr.attr, + /* Only present if temp sensor is */ + &iio_dev_attr_temp.dev_attr.attr, + NULL, +}; + +static const struct attribute_group sca3000_attribute_group = { + .attrs = sca3000_attributes, +}; + +static const struct attribute_group sca3000_attribute_group_with_temp = { + .attrs = sca3000_attributes_with_temp, +}; + +/* RING RELATED interrupt handler */ +/* depending on event, push to the ring buffer event chrdev or the event one */ + +/** + * sca3000_interrupt_handler_bh() - handling ring and non ring events + * + * This function is complicated by the fact that the devices can signify ring + * and non ring events via the same interrupt line and they can only + * be distinguished via a read of the relevant status register. + **/ +static void sca3000_interrupt_handler_bh(struct work_struct *work_s) +{ + struct sca3000_state *st + = container_of(work_s, struct sca3000_state, + interrupt_handler_ws); + u8 *rx; + int ret; + + /* Could lead if badly timed to an extra read of status reg, + * but ensures no interrupt is missed. + */ + enable_irq(st->us->irq); + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_STATUS, + &rx, 1); + mutex_unlock(&st->lock); + if (ret) + goto done; + + sca3000_ring_int_process(rx[1], st->indio_dev->ring); + + if (rx[1] & SCA3000_INT_STATUS_FREE_FALL) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_FREE_FALL, + st->last_timestamp); + + if (rx[1] & SCA3000_INT_STATUS_Y_TRIGGER) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_Y_HIGH, + st->last_timestamp); + + if (rx[1] & SCA3000_INT_STATUS_X_TRIGGER) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_X_HIGH, + st->last_timestamp); + + if (rx[1] & SCA3000_INT_STATUS_Z_TRIGGER) + iio_push_event(st->indio_dev, 0, + IIO_EVENT_CODE_ACCEL_Z_HIGH, + st->last_timestamp); + +done: + kfree(rx); + return; +} + +/** + * sca3000_handler_th() handles all interrupt events from device + * + * These devices deploy unified interrupt status registers meaning + * all interrupts must be handled together + **/ +static int sca3000_handler_th(struct iio_dev *dev_info, + int index, + s64 timestamp, + int no_test) +{ + struct sca3000_state *st = dev_info->dev_data; + + st->last_timestamp = timestamp; + schedule_work(&st->interrupt_handler_ws); + + return 0; +} + +/** + * sca3000_query_mo_det() is motion detection enabled for this axis + * + * First queries if motion detection is enabled and then if this axis is + * on. + **/ +static ssize_t sca3000_query_mo_det(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + struct iio_event_attr *this_attr = to_iio_event_attr(attr); + int ret, len = 0; + u8 *rx; + u8 protect_mask = 0x03; + + /* read current value of mode register */ + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (ret) + goto error_ret; + + if ((rx[1]&protect_mask) != SCA3000_MEAS_MODE_MOT_DET) + len += sprintf(buf + len, "0\n"); + else { + kfree(rx); + ret = sca3000_read_ctrl_reg(st, + SCA3000_REG_CTRL_SEL_MD_CTRL, + &rx); + if (ret) + goto error_ret; + /* only supporting logical or's for now */ + len += sprintf(buf + len, "%d\n", + (rx[1] & this_attr->mask) ? 1 : 0); + } + kfree(rx); +error_ret: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} +/** + * sca3000_query_free_fall_mode() is free fall mode enabled + **/ +static ssize_t sca3000_query_free_fall_mode(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret, len; + u8 *rx; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + mutex_unlock(&st->lock); + if (ret) + return ret; + len = sprintf(buf, "%d\n", + !!(rx[1] & SCA3000_FREE_FALL_DETECT)); + kfree(rx); + + return len; +} +/** + * sca3000_query_ring_int() is the hardware ring status interrupt enabled + **/ +static ssize_t sca3000_query_ring_int(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_event_attr *this_attr = to_iio_event_attr(attr); + int ret, len; + u8 *rx; + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_MASK, &rx, 1); + mutex_unlock(&st->lock); + if (ret) + return ret; + len = sprintf(buf, "%d\n", (rx[1] & this_attr->mask) ? 1 : 0); + kfree(rx); + + return len; +} +/** + * sca3000_set_ring_int() set state of ring status interrupt + **/ +static ssize_t sca3000_set_ring_int(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + struct iio_event_attr *this_attr = to_iio_event_attr(attr); + + long val; + int ret; + u8 *rx; + + mutex_lock(&st->lock); + ret = strict_strtol(buf, 10, &val); + if (ret) + goto error_ret; + ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_MASK, &rx, 1); + if (ret) + goto error_ret; + if (val) + ret = sca3000_write_reg(st, + SCA3000_REG_ADDR_INT_MASK, + rx[1] | this_attr->mask); + else + ret = sca3000_write_reg(st, + SCA3000_REG_ADDR_INT_MASK, + rx[1] & ~this_attr->mask); + kfree(rx); +error_ret: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +/** + * sca3000_set_free_fall_mode() simple on off control for free fall int + * + * In these chips the free fall detector should send an interrupt if + * the device falls more than 25cm. This has not been tested due + * to fragile wiring. + **/ + +static ssize_t sca3000_set_free_fall_mode(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + long val; + int ret; + u8 *rx; + u8 protect_mask = SCA3000_FREE_FALL_DETECT; + + mutex_lock(&st->lock); + ret = strict_strtol(buf, 10, &val); + if (ret) + goto error_ret; + + /* read current value of mode register */ + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (ret) + goto error_ret; + + /*if off and should be on*/ + if (val && !(rx[1] & protect_mask)) + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, + (rx[1] | SCA3000_FREE_FALL_DETECT)); + /* if on and should be off */ + else if (!val && (rx[1]&protect_mask)) + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, + (rx[1] & ~protect_mask)); + + kfree(rx); +error_ret: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +/** + * sca3000_set_mo_det() simple on off control for motion detector + * + * This is a per axis control, but enabling any will result in the + * motion detector unit being enabled. + * N.B. enabling motion detector stops normal data acquisition. + * There is a complexity in knowing which mode to return to when + * this mode is disabled. Currently normal mode is assumed. + **/ +static ssize_t sca3000_set_mo_det(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct sca3000_state *st = indio_dev->dev_data; + struct iio_event_attr *this_attr = to_iio_event_attr(attr); + long val; + int ret; + u8 *rx; + u8 protect_mask = 0x03; + ret = strict_strtol(buf, 10, &val); + if (ret) + return ret; + + mutex_lock(&st->lock); + /* First read the motion detector config to find out if + * this axis is on*/ + ret = sca3000_read_ctrl_reg(st, + SCA3000_REG_CTRL_SEL_MD_CTRL, + &rx); + if (ret) + goto exit_point; + /* Off and should be on */ + if (val && !(rx[1] & this_attr->mask)) { + ret = sca3000_write_ctrl_reg(st, + SCA3000_REG_CTRL_SEL_MD_CTRL, + rx[1] | this_attr->mask); + if (ret) + goto exit_point_free_rx; + st->mo_det_use_count++; + } else if (!val && (rx[1]&this_attr->mask)) { + ret = sca3000_write_ctrl_reg(st, + SCA3000_REG_CTRL_SEL_MD_CTRL, + rx[1] & ~(this_attr->mask)); + if (ret) + goto exit_point_free_rx; + st->mo_det_use_count--; + } else /* relies on clean state for device on boot */ + goto exit_point_free_rx; + kfree(rx); + /* read current value of mode register */ + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (ret) + goto exit_point; + /*if off and should be on*/ + if ((st->mo_det_use_count) + && ((rx[1]&protect_mask) != SCA3000_MEAS_MODE_MOT_DET)) + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, + (rx[1] & ~protect_mask) + | SCA3000_MEAS_MODE_MOT_DET); + /* if on and should be off */ + else if (!(st->mo_det_use_count) + && ((rx[1]&protect_mask) == SCA3000_MEAS_MODE_MOT_DET)) + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, + (rx[1] & ~protect_mask)); +exit_point_free_rx: + kfree(rx); +exit_point: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +/* Shared event handler for all events as single event status register */ +IIO_EVENT_SH(all, &sca3000_handler_th); + +/* Free fall detector related event attribute */ +IIO_EVENT_ATTR_FREE_FALL_DETECT_SH(iio_event_all, + sca3000_query_free_fall_mode, + sca3000_set_free_fall_mode, + 0) + +/* Motion detector related event attributes */ +IIO_EVENT_ATTR_ACCEL_X_HIGH_SH(iio_event_all, + sca3000_query_mo_det, + sca3000_set_mo_det, + SCA3000_MD_CTRL_OR_X); + +IIO_EVENT_ATTR_ACCEL_Y_HIGH_SH(iio_event_all, + sca3000_query_mo_det, + sca3000_set_mo_det, + SCA3000_MD_CTRL_OR_Y); + +IIO_EVENT_ATTR_ACCEL_Z_HIGH_SH(iio_event_all, + sca3000_query_mo_det, + sca3000_set_mo_det, + SCA3000_MD_CTRL_OR_Z); + +/* Hardware ring buffer related event attributes */ +IIO_EVENT_ATTR_RING_50_FULL_SH(iio_event_all, + sca3000_query_ring_int, + sca3000_set_ring_int, + SCA3000_INT_MASK_RING_HALF); + +IIO_EVENT_ATTR_RING_75_FULL_SH(iio_event_all, + sca3000_query_ring_int, + sca3000_set_ring_int, + SCA3000_INT_MASK_RING_THREE_QUARTER); + +static struct attribute *sca3000_event_attributes[] = { + &iio_event_attr_free_fall.dev_attr.attr, + &iio_event_attr_accel_x_high.dev_attr.attr, + &iio_event_attr_accel_y_high.dev_attr.attr, + &iio_event_attr_accel_z_high.dev_attr.attr, + &iio_event_attr_ring_50_full.dev_attr.attr, + &iio_event_attr_ring_75_full.dev_attr.attr, + NULL, +}; + +static struct attribute_group sca3000_event_attribute_group = { + .attrs = sca3000_event_attributes, +}; + +/** + * sca3000_clean_setup() get the device into a predictable state + * + * Devices use flash memory to store many of the register values + * and hence can come up in somewhat unpredictable states. + * Hence reset everything on driver load. + **/ +static int sca3000_clean_setup(struct sca3000_state *st) +{ + int ret; + u8 *rx; + + mutex_lock(&st->lock); + /* Ensure all interrupts have been acknowledged */ + ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_STATUS, &rx, 1); + if (ret) + goto error_ret; + kfree(rx); + + /* Turn off all motion detection channels */ + ret = sca3000_read_ctrl_reg(st, + SCA3000_REG_CTRL_SEL_MD_CTRL, + &rx); + if (ret) + goto error_ret; + ret = sca3000_write_ctrl_reg(st, + SCA3000_REG_CTRL_SEL_MD_CTRL, + rx[1] & SCA3000_MD_CTRL_PROT_MASK); + kfree(rx); + if (ret) + goto error_ret; + + /* Disable ring buffer */ + sca3000_read_ctrl_reg(st, + SCA3000_REG_CTRL_SEL_OUT_CTRL, + &rx); + /* Frequency of ring buffer sampling deliberately restricted to make + * debugging easier - add control of this later */ + ret = sca3000_write_ctrl_reg(st, + SCA3000_REG_CTRL_SEL_OUT_CTRL, + (rx[1] & SCA3000_OUT_CTRL_PROT_MASK) + | SCA3000_OUT_CTRL_BUF_X_EN + | SCA3000_OUT_CTRL_BUF_Y_EN + | SCA3000_OUT_CTRL_BUF_Z_EN + | SCA3000_OUT_CTRL_BUF_DIV_4); + kfree(rx); + + if (ret) + goto error_ret; + /* Enable interrupts, relevant to mode and set up as active low */ + ret = sca3000_read_data(st, + SCA3000_REG_ADDR_INT_MASK, + &rx, 1); + if (ret) + goto error_ret; + ret = sca3000_write_reg(st, + SCA3000_REG_ADDR_INT_MASK, + (rx[1] & SCA3000_INT_MASK_PROT_MASK) + | SCA3000_INT_MASK_ACTIVE_LOW); + kfree(rx); + if (ret) + goto error_ret; + /* Select normal measurement mode, free fall off, ring off */ + /* Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5 + * as that occurs in one of the example on the datasheet */ + ret = sca3000_read_data(st, + SCA3000_REG_ADDR_MODE, + &rx, 1); + if (ret) + goto error_ret; + ret = sca3000_write_reg(st, + SCA3000_REG_ADDR_MODE, + (rx[1] & SCA3000_MODE_PROT_MASK)); + kfree(rx); + st->bpse = 11; + +error_ret: + mutex_unlock(&st->lock); + return ret; +} + +static int __devinit __sca3000_probe(struct spi_device *spi, + enum sca3000_variant variant) +{ + int ret, regdone = 0; + struct sca3000_state *st; + + st = kzalloc(sizeof(struct sca3000_state), GFP_KERNEL); + if (st == NULL) { + ret = -ENOMEM; + goto error_ret; + } + spi_set_drvdata(spi, st); + + st->tx = kmalloc(sizeof(*st->tx)*6, GFP_KERNEL); + if (st->tx == NULL) { + ret = -ENOMEM; + goto error_clear_st; + } + st->rx = kmalloc(sizeof(*st->rx)*3, GFP_KERNEL); + if (st->rx == NULL) { + ret = -ENOMEM; + goto error_free_tx; + } + st->us = spi; + mutex_init(&st->lock); + st->info = &sca3000_spi_chip_info_tbl[variant]; + + st->indio_dev = iio_allocate_device(); + if (st->indio_dev == NULL) { + ret = -ENOMEM; + goto error_free_rx; + } + + st->indio_dev->dev.parent = &spi->dev; + st->indio_dev->num_interrupt_lines = 1; + st->indio_dev->event_attrs = &sca3000_event_attribute_group; + if (st->info->temp_output) + st->indio_dev->attrs = &sca3000_attribute_group_with_temp; + else + st->indio_dev->attrs = &sca3000_attribute_group; + st->indio_dev->dev_data = (void *)(st); + st->indio_dev->modes = INDIO_DIRECT_MODE; + + sca3000_configure_ring(st->indio_dev); + + ret = iio_device_register(st->indio_dev); + if (ret < 0) + goto error_free_dev; + regdone = 1; + ret = iio_ring_buffer_register(st->indio_dev->ring); + if (ret < 0) + goto error_unregister_dev; + if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) { + INIT_WORK(&st->interrupt_handler_ws, + sca3000_interrupt_handler_bh); + ret = iio_register_interrupt_line(spi->irq, + st->indio_dev, + 0, + IRQF_TRIGGER_FALLING, + "sca3000"); + if (ret) + goto error_unregister_ring; + /* RFC + * Probably a common situation. All interrupts need an ack + * and there is only one handler so the complicated list system + * is overkill. At very least a simpler registration method + * might be worthwhile. + */ + iio_add_event_to_list(iio_event_attr_accel_z_high.listel, + &st->indio_dev + ->interrupts[0]->ev_list); + } + sca3000_register_ring_funcs(st->indio_dev); + ret = sca3000_clean_setup(st); + if (ret) + goto error_unregister_interrupt_line; + return 0; + +error_unregister_interrupt_line: + if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) + iio_unregister_interrupt_line(st->indio_dev, 0); +error_unregister_ring: + iio_ring_buffer_unregister(st->indio_dev->ring); +error_unregister_dev: +error_free_dev: + if (regdone) + iio_device_unregister(st->indio_dev); + else + iio_free_device(st->indio_dev); +error_free_rx: + kfree(st->rx); +error_free_tx: + kfree(st->tx); +error_clear_st: + kfree(st); +error_ret: + return ret; +} + +static int sca3000_stop_all_interrupts(struct sca3000_state *st) +{ + int ret; + u8 *rx; + + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_MASK, &rx, 1); + if (ret) + goto error_ret; + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_INT_MASK, + (rx[1] & ~(SCA3000_INT_MASK_RING_THREE_QUARTER + | SCA3000_INT_MASK_RING_HALF + | SCA3000_INT_MASK_ALL_INTS))); +error_ret: + kfree(rx); + return ret; + +} + +static int sca3000_remove(struct spi_device *spi) +{ + struct sca3000_state *st = spi_get_drvdata(spi); + struct iio_dev *indio_dev = st->indio_dev; + int ret; + /* Must ensure no interrupts can be generated after this!*/ + ret = sca3000_stop_all_interrupts(st); + if (ret) + return ret; + if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) + iio_unregister_interrupt_line(indio_dev, 0); + iio_ring_buffer_unregister(indio_dev->ring); + sca3000_unconfigure_ring(indio_dev); + iio_device_unregister(indio_dev); + + kfree(st->tx); + kfree(st->rx); + kfree(st); + + return 0; +} + +/* These macros save on an awful lot of repeated code */ +#define SCA3000_VARIANT_PROBE(_name) \ + static int __devinit \ + sca3000_##_name##_probe(struct spi_device *spi) \ + { \ + return __sca3000_probe(spi, _name); \ + } + +#define SCA3000_VARIANT_SPI_DRIVER(_name) \ + struct spi_driver sca3000_##_name##_driver = { \ + .driver = { \ + .name = "sca3000_" #_name, \ + .owner = THIS_MODULE, \ + }, \ + .probe = sca3000_##_name##_probe, \ + .remove = __devexit_p(sca3000_remove), \ + } + +SCA3000_VARIANT_PROBE(d01); +static SCA3000_VARIANT_SPI_DRIVER(d01); + +SCA3000_VARIANT_PROBE(d03); +static SCA3000_VARIANT_SPI_DRIVER(d03); + +SCA3000_VARIANT_PROBE(e02); +static SCA3000_VARIANT_SPI_DRIVER(e02); + +SCA3000_VARIANT_PROBE(e04); +static SCA3000_VARIANT_SPI_DRIVER(e04); + +SCA3000_VARIANT_PROBE(e05); +static SCA3000_VARIANT_SPI_DRIVER(e05); + +SCA3000_VARIANT_PROBE(l01); +static SCA3000_VARIANT_SPI_DRIVER(l01); + +static __init int sca3000_init(void) +{ + int ret; + + ret = spi_register_driver(&sca3000_d01_driver); + if (ret) + goto error_ret; + ret = spi_register_driver(&sca3000_d03_driver); + if (ret) + goto error_unreg_d01; + ret = spi_register_driver(&sca3000_e02_driver); + if (ret) + goto error_unreg_d03; + ret = spi_register_driver(&sca3000_e04_driver); + if (ret) + goto error_unreg_e02; + ret = spi_register_driver(&sca3000_e05_driver); + if (ret) + goto error_unreg_e04; + ret = spi_register_driver(&sca3000_l01_driver); + if (ret) + goto error_unreg_e05; + + return 0; + +error_unreg_e05: + spi_unregister_driver(&sca3000_e05_driver); +error_unreg_e04: + spi_unregister_driver(&sca3000_e04_driver); +error_unreg_e02: + spi_unregister_driver(&sca3000_e02_driver); +error_unreg_d03: + spi_unregister_driver(&sca3000_d03_driver); +error_unreg_d01: + spi_unregister_driver(&sca3000_d01_driver); +error_ret: + + return ret; +} + +static __exit void sca3000_exit(void) +{ + spi_unregister_driver(&sca3000_l01_driver); + spi_unregister_driver(&sca3000_e05_driver); + spi_unregister_driver(&sca3000_e04_driver); + spi_unregister_driver(&sca3000_e02_driver); + spi_unregister_driver(&sca3000_d03_driver); + spi_unregister_driver(&sca3000_d01_driver); +} + +module_init(sca3000_init); +module_exit(sca3000_exit); + +MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>"); +MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/iio/accel/sca3000_ring.c b/drivers/staging/iio/accel/sca3000_ring.c new file mode 100644 index 000000000000..d5ea237793a6 --- /dev/null +++ b/drivers/staging/iio/accel/sca3000_ring.c @@ -0,0 +1,331 @@ +/* + * sca3000_ring.c -- support VTI sca3000 series accelerometers via SPI + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * Copyright (c) 2009 Jonathan Cameron <jic23@cam.ac.uk> + * + */ + +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/fs.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/spi/spi.h> +#include <linux/sysfs.h> + +#include "../iio.h" +#include "../sysfs.h" +#include "../ring_generic.h" +#include "../ring_hw.h" +#include "accel.h" +#include "sca3000.h" + +/* RFC / future work + * + * The internal ring buffer doesn't actually change what it holds depending + * on which signals are enabled etc, merely whether you can read them. + * As such the scan mode selection is somewhat different than for a software + * ring buffer and changing it actually covers any data already in the buffer. + * Currently scan elements aren't configured so it doesn't matter. + */ + +/** + * sca3000_rip_hw_rb() - main ring access function, pulls data from ring + * @r: the ring + * @count: number of samples to try and pull + * @data: output the actual samples pulled from the hw ring + * @dead_offset: cheating a bit here: Set to 1 so as to allow for the + * leading byte used in bus comms. + * + * Currently does not provide timestamps. As the hardware doesn't add them they + * can only be inferred aproximately from ring buffer events such as 50% full + * and knowledge of when buffer was last emptied. This is left to userspace. + **/ +static int sca3000_rip_hw_rb(struct iio_ring_buffer *r, + size_t count, u8 **data, int *dead_offset) +{ + struct iio_hw_ring_buffer *hw_ring = iio_to_hw_ring_buf(r); + struct iio_dev *indio_dev = hw_ring->private; + struct sca3000_state *st = indio_dev->dev_data; + u8 *rx; + int ret, num_available, num_read = 0; + int bytes_per_sample = 1; + + if (st->bpse == 11) + bytes_per_sample = 2; + + mutex_lock(&st->lock); + /* Check how much data is available: + * RFC: Implement an ioctl to not bother checking whether there + * is enough data in the ring? Afterall, if we are responding + * to an interrupt we have a minimum content guaranteed so it + * seems slight silly to waste time checking it is there. + */ + ret = sca3000_read_data(st, + SCA3000_REG_ADDR_BUF_COUNT, + &rx, 1); + if (ret) + goto error_ret; + else + num_available = rx[1]; + /* num_available is the total number of samples available + * i.e. number of time points * number of channels. + */ + kfree(rx); + if (count > num_available * bytes_per_sample) + num_read = num_available*bytes_per_sample; + else + num_read = count - (count % (bytes_per_sample)); + + /* Avoid the read request byte */ + *dead_offset = 1; + ret = sca3000_read_data(st, + SCA3000_REG_ADDR_RING_OUT, + data, num_read); +error_ret: + mutex_unlock(&st->lock); + + return ret ? ret : num_read; +} + +/* This is only valid with all 3 elements enabled */ +static int sca3000_ring_get_length(struct iio_ring_buffer *r) +{ + return 64; +} + +/* only valid if resolution is kept at 11bits */ +static int sca3000_ring_get_bpd(struct iio_ring_buffer *r) +{ + return 6; +} +static void sca3000_ring_release(struct device *dev) +{ + struct iio_ring_buffer *r = to_iio_ring_buffer(dev); + kfree(iio_to_hw_ring_buf(r)); +} + +static IIO_RING_ENABLE_ATTR; +static IIO_RING_BPS_ATTR; +static IIO_RING_LENGTH_ATTR; + +/** + * sca3000_show_ring_bpse() -sysfs function to query bits per sample from ring + * @dev: ring buffer device + * @attr: this device attribute + * @buf: buffer to write to + **/ +static ssize_t sca3000_show_ring_bpse(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int len = 0, ret; + u8 *rx; + struct iio_ring_buffer *r = dev_get_drvdata(dev); + struct sca3000_state *st = r->indio_dev->dev_data; + + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (ret) + goto error_ret; + len = sprintf(buf, "%d\n", (rx[1] & SCA3000_RING_BUF_8BIT) ? 8 : 11); + kfree(rx); +error_ret: + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +/** + * sca3000_store_ring_bpse() - bits per scan element + * @dev: ring buffer device + * @attr: attribute called from + * @buf: input from userspace + * @len: length of input + **/ +static ssize_t sca3000_store_ring_bpse(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_ring_buffer *r = dev_get_drvdata(dev); + struct sca3000_state *st = r->indio_dev->dev_data; + int ret; + u8 *rx; + long val; + ret = strict_strtol(buf, 10, &val); + if (ret) + return ret; + + mutex_lock(&st->lock); + + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (!ret) + switch (val) { + case 8: + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, + rx[1] | SCA3000_RING_BUF_8BIT); + st->bpse = 8; + break; + case 11: + ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, + rx[1] & ~SCA3000_RING_BUF_8BIT); + st->bpse = 11; + break; + default: + ret = -EINVAL; + break; + } + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +static IIO_CONST_ATTR(bpse_available, "8 11"); + +static IIO_DEV_ATTR_BPSE(S_IRUGO | S_IWUSR, + sca3000_show_ring_bpse, + sca3000_store_ring_bpse); + +/* + * Ring buffer attributes + * This device is a bit unusual in that the sampling frequency and bpse + * only apply to the ring buffer. At all times full rate and accuracy + * is available via direct reading from registers. + */ +static struct attribute *iio_ring_attributes[] = { + &dev_attr_length.attr, + &dev_attr_bps.attr, + &dev_attr_ring_enable.attr, + &iio_dev_attr_bpse.dev_attr.attr, + &iio_const_attr_bpse_available.dev_attr.attr, + NULL, +}; + +static struct attribute_group sca3000_ring_attr = { + .attrs = iio_ring_attributes, +}; + +static const struct attribute_group *sca3000_ring_attr_groups[] = { + &sca3000_ring_attr, + NULL +}; + +static struct device_type sca3000_ring_type = { + .release = sca3000_ring_release, + .groups = sca3000_ring_attr_groups, +}; + +static struct iio_ring_buffer *sca3000_rb_allocate(struct iio_dev *indio_dev) +{ + struct iio_ring_buffer *buf; + struct iio_hw_ring_buffer *ring; + + ring = kzalloc(sizeof *ring, GFP_KERNEL); + if (!ring) + return 0; + ring->private = indio_dev; + buf = &ring->buf; + iio_ring_buffer_init(buf, indio_dev); + buf->dev.type = &sca3000_ring_type; + device_initialize(&buf->dev); + buf->dev.parent = &indio_dev->dev; + dev_set_drvdata(&buf->dev, (void *)buf); + + return buf; +} + +static inline void sca3000_rb_free(struct iio_ring_buffer *r) +{ + if (r) + iio_put_ring_buffer(r); +} + +int sca3000_configure_ring(struct iio_dev *indio_dev) +{ + indio_dev->ring = sca3000_rb_allocate(indio_dev); + if (indio_dev->ring == NULL) + return -ENOMEM; + indio_dev->modes |= INDIO_RING_HARDWARE_BUFFER; + + indio_dev->ring->access.rip_lots = &sca3000_rip_hw_rb; + indio_dev->ring->access.get_length = &sca3000_ring_get_length; + indio_dev->ring->access.get_bpd = &sca3000_ring_get_bpd; + + return 0; +} + +void sca3000_unconfigure_ring(struct iio_dev *indio_dev) +{ + sca3000_rb_free(indio_dev->ring); +} + +static inline +int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state) +{ + struct sca3000_state *st = indio_dev->dev_data; + int ret; + u8 *rx; + + mutex_lock(&st->lock); + ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1); + if (ret) + goto error_ret; + if (state) { + printk(KERN_INFO "supposedly enabling ring buffer\n"); + ret = sca3000_write_reg(st, + SCA3000_REG_ADDR_MODE, + (rx[1] | SCA3000_RING_BUF_ENABLE)); + } else + ret = sca3000_write_reg(st, + SCA3000_REG_ADDR_MODE, + (rx[1] & ~SCA3000_RING_BUF_ENABLE)); + kfree(rx); +error_ret: + mutex_unlock(&st->lock); + + return ret; +} +/** + * sca3000_hw_ring_preenable() hw ring buffer preenable function + * + * Very simple enable function as the chip will allows normal reads + * during ring buffer operation so as long as it is indeed running + * before we notify the core, the precise ordering does not matter. + **/ +static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev) +{ + return __sca3000_hw_ring_state_set(indio_dev, 1); +} + +static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev) +{ + return __sca3000_hw_ring_state_set(indio_dev, 0); +} + +void sca3000_register_ring_funcs(struct iio_dev *indio_dev) +{ + indio_dev->ring->preenable = &sca3000_hw_ring_preenable; + indio_dev->ring->postdisable = &sca3000_hw_ring_postdisable; +} + +/** + * sca3000_ring_int_process() ring specific interrupt handling. + * + * This is only split from the main interrupt handler so as to + * reduce the amount of code if the ring buffer is not enabled. + **/ +void sca3000_ring_int_process(u8 val, struct iio_ring_buffer *ring) +{ + if (val & SCA3000_INT_STATUS_THREE_QUARTERS) + iio_push_or_escallate_ring_event(ring, + IIO_EVENT_CODE_RING_75_FULL, + 0); + else if (val & SCA3000_INT_STATUS_HALF) + iio_push_ring_event(ring, + IIO_EVENT_CODE_RING_50_FULL, 0); +} |