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* mmc: dw_mmc: exynos: move definitions to header fileSeungwon Jeon2015-01-192-42/+62
| | | | | | | | | | | | Move exynos related definition to header file. And this also changes some of the registers name to match the standard naming convention. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> [Alim: updated the commit message] Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: exynos: don't use if clock isn't availableSeungwon Jeon2015-01-191-4/+7
| | | | | | | | | Add checking whether the clock is valid. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: fix the max_blk_count in IDMACSeungwon Jeon2015-01-191-2/+2
| | | | | | | | | | | | | | Even though 1MB is reserved for descriptor table in IDMAC, the dw_mmc host driver is allowed to receive only maximum 128KB block length in one request. This is caused by setting improper max_blk_count. It needs to be e adjusted so that descriptor table is used fully. It is found that the performance is improved with the increased the max_blk_count. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mxs-mmc: remove unneeded NULL checkDan Carpenter2015-01-191-2/+1Star
| | | | | | | | | | | | Static checkers complain about the inconsistent NULL checking here: drivers/mmc/host/mxs-mmc.c:680 mxs_mmc_probe() warn: variable dereferenced before check 'ssp->dmach' (see line 660) The variable can't actually be NULL so we can remove the check. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Removing unused codeDavid Lanzendörfer2015-01-191-9/+1Star
| | | | | | | | | | Removing a relict from reverse engineering of the Android driver code in sunxi_mmc_clk_set_rate. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Correcting SDXC_HARDWARE_RESET bitDavid Lanzendörfer2015-01-191-1/+1
| | | | | | | | | | | Fixing the register name in sunxi_mmc_reset_host since the SDXC_HARDWARE_RESET bit is actually located within REG_GCTRL and not REG_CMDR as it was pointed out by Allwinner. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Lock fixDavid Lanzendörfer2015-01-191-1/+12
| | | | | | | | | | | | | | | | | | 1) Adding a comment in order to clarify the choice of the locks within sunxi_mmc_handle_manual_stop 2) As <lixiang@allwinnertech.com> has pointed out the wait_dma variable was not accessed within the spin lock block in sunxi_mmc_request and so (even if it should never happend) it would have theoretically been possible that some other function would access the variable at the same time as the function. This has been changed now and the function is using local variables outside the lock and copys the value over during the lock phase. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Fix setup of last descriptor of dma transferHans de Goede2015-01-191-1/+3
| | | | | | | | | | | | | | | The last descriptor might be the first descriptor as well, so use masking to add the LD (last descriptor) bit and drop the DIC (disable interrupt on completion) bit rather then hard assignment as hard assignment will override the FD (first descriptor) bit if there is only 1 descriptor. Also set the ER (end of ring) bit and clear buf_addr_ptr2 on the last descriptor, like the android kernel code does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap_hsmmc: remove prepare/complete system suspend support.NeilBrown2015-01-192-54/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | The only function of these 'prepare' and 'complete' is to disable the 'card detect' irq during suspend. The commit which added this, commit a48ce884d5819d5df2cf1139ab3c43f8e9e419b3 mmc: omap_hsmmc: Introduce omap_hsmmc_prepare/complete justified it by the need to avoid the registration of new devices during suspend. However mmc_pm_notify will set ->rescan_disable in the 'prepare' stage and clear it in the 'complete' stage, so no card detection will actually happen. Also the interrupt will be disabled before final suspend as part of common suspend processing. So this disabling of the interrupt is unnecessary, and interferes with a transition to using common code for card-detect management. Cc: Felipe Balbi <balbi@ti.com> Cc: Venkatraman S <svenkatr@ti.com> Cc: Chris Ball <cjb@laptop.org> Signed-off-by: NeilBrown <neilb@suse.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: toshsd: Fix unbalanced lockingAxel Lin2015-01-191-1/+3
| | | | | | | Fix returning IRQ_HANDLED with spin_lock held. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: toshsd: use module_pci_driver to simplify the codeWei Yongjun2015-01-191-12/+1Star
| | | | | | | | Use the module_pci_driver() macro to make the code simpler by eliminating module_init and module_exit calls. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Fix FSL ESDHC reset handling quirkAlessio Igor Bogani2015-01-191-1/+9
| | | | | | | | | | | | | | The commit 0718e59ae259 ("mmc: sdhci: move FSL ESDHC reset handling quirk into esdhc code") states that Freescale esdhc is the only controller which needs the interrupt registers restored after a reset. So it moves SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET quirk handling code into the esdhc-imx driver only. Unfortunately the same controller is used in other boards which use the of-esdhc driver instead (like powerpc P2020). Restore interrupts after reset in the sdhci-of-esdhc driver also. Signed-off-by: Alessio Igor Bogani <alessio.bogani@elettra.eu> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-sirf: add sirf tuning function (cmd 19)Minda Chen2015-01-191-0/+71
| | | | | | | | | | | | | | | | | | Add manual tuning function in CSR atlas7 SoC. It is mainly used for the UHS-I SD card working SDR50 SDR104 mode. The tuning principle can be seen in SD spec part1 v3.01 4.2.4.5 (tuning command). SD host send the cmd19 and set the delay value(0-127). and the sdcard return 64 bytes data. If the data is same with the tuning data. The delay value is valid. Execute this commmand 128 times. And calculate the longest window of the valid values. The value in the middle of this window is the best value. Signed-off-by: Minda Chen <Minda.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: Protect read-modify-write of INTMASK with a lockDoug Anderson2015-01-192-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're running into cases where our enabling of the SDIO interrupt in dw_mmc doesn't actually take effect. Specifically, adding patch like this: +++ b/drivers/mmc/host/dw_mmc.c @@ -1076,6 +1076,9 @@ static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) mci_writel(host, INTMASK, (int_mask | SDMMC_INT_SDIO(slot->id))); + int_mask = mci_readl(host, INTMASK); + if (!(int_mask & SDMMC_INT_SDIO(slot->id))) + dev_err(&mmc->class_dev, "failed to enable sdio irq\n"); } else { ...actually triggers the error message. That's because the dw_mci_enable_sdio_irq() unsafely does a read-modify-write of the INTMASK register. We can't just use the standard host->lock since that lock is not irq safe and mmc_signal_sdio_irq() (called from interrupt context) calls dw_mci_enable_sdio_irq(). Add a new irq-safe lock to protect INTMASK. An alternate solution to this is to punt mmc_signal_sdio_irq() to the tasklet and then protect INTMASK modifications by the standard host lock. This seemed like a bit more of a high-latency change. Reported-by: Bing Zhao <bzhao@marvell.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: Cleanup disable of low power mode w/ SDIO interruptsDoug Anderson2015-01-192-34/+36
| | | | | | | | | | | | | | | | | | In the patch (9623b5b mmc: dw_mmc: Disable low power mode if SDIO interrupts are used) I added code that disabled the low power mode of dw_mmc when SDIO interrupts are used. That code worked but always felt a little hacky because we ended up disabling low power as a side effect of the first enable_sdio_irq() call. That wouldn't be so bad except that disabling low power involves a complicated process of writing to the CMD/CMDARG registers and that extra process makes it difficult to cleanly the read-modify-write race in dw_mci_enable_sdio_irq() (see future patch in the series). Change the code to take advantage of the init_card() callback of the mmc core to do this right at bootup. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: Support the optional init_card() callback for MMC and SDDoug Anderson2015-01-192-1/+12
| | | | | | | | | | | | | | | | | | | | | In (3fcb027 ARM: MXC: mxcmmc: work around a bug in the SDHC busy line handling) the optional init_card() callback was added. According to the original change it was "for now only called from mmc_sdio_init_card()". This callback really ought to be called from the SD and MMC init functions as well. One current user of this callback (mxcmci_init_card) will not work as expected if you insert an SDIO card, then eject it and put a normal SD card in. Specifically the normal SD card will not get to run with 4-bit data. I'd like to use the init_card() callback to handle a similar quirk on dw_mmc when using SDIO Interrupts (the "low power" feature of the card needs to be disabled), so that will add a second user of the function. Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Grant Grundler <grundler@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* ARM: OMAP2+: Make sure pandora_wl1251_init_card() applies to SDIO onlyDoug Anderson2015-01-191-6/+8
| | | | | | | | | | In preparation for having init_card() called for all card types (not just SDIO), change pandora_wl1251_init_card() so it checks whether the card type is SDIO. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* Linux 3.19-rc5Linus Torvalds2015-01-181-1/+1
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* Merge tag 'armsoc-for-linus' of ↵Linus Torvalds2015-01-1832-80/+272
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "We've been sitting on our fixes branch for a while, so this batch is unfortunately on the large side. A lot of these are tweaks and fixes to device trees, fixing various bugs around clocks, reg ranges, etc. There's also a few defconfig updates (which are on the late side, no more of those). All in all the diffstat is bigger than ideal at this time, but nothing in here seems particularly risky" * tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits) reset: sunxi: fix spinlock initialization ARM: dts: disable CCI on exynos5420 based arndale-octa drivers: bus: check cci device tree node status ARM: rockchip: disable jtag/sdmmc autoswitching on rk3288 ARM: nomadik: fix up leftover device tree pins ARM: at91: board-dt-sama5: add phy_fixup to override NAND_Tree ARM: at91/dt: sam9263: Add missing clocks to lcdc node ARM: at91: sama5d3: dt: correct the sound route ARM: at91/dt: sama5d4: fix the timer reg length ARM: exynos_defconfig: Enable LM90 driver ARM: exynos_defconfig: Enable options for display panel support arm: dts: Use pmu_system_controller phandle for dp phy ARM: shmobile: sh73a0 legacy: Set .control_parent for all irqpin instances ARM: dts: berlin: correct BG2Q's SM GPIO location. ARM: dts: berlin: add broken-cd and set bus width for eMMC in Marvell DMP DT ARM: dts: berlin: fix io clk and add missing core clk for BG2Q sdhci2 host ARM: dts: Revert disabling of smc91x for n900 ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling ARM: dts: dra7-evm: fix qspi device tree partition size ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT ...
| * Merge tag 'samsung-fixes-3.19' of ↵Olof Johansson2015-01-173-4/+20
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes Merge "Samsung fixes for v3.19" from Kukjin Kim: Samsung fixes for v3.19 - exynos_defconfig: enable LM90 driver and display panel support - HWMON - SENSORS_LM90 - Direct Rendering Manager (DRM) - DRM bridge registration and lookup framework - Parade ps8622/ps8625 eDP/LVDS bridge - NXP ptn3460 eDP/LVDS bridge - Exynos Fully Interactive Mobile Display controller (FIMD) - Panel registration and lookup framework - Simple panels - Backlight & LCD device support - use pmu_system_controller phandle for dp phy : DP PHY requires pmu_system_controller to handle PMU reg. now * tag 'samsung-fixes-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: exynos_defconfig: Enable LM90 driver ARM: exynos_defconfig: Enable options for display panel support arm: dts: Use pmu_system_controller phandle for dp phy Signed-off-by: Olof Johansson <olof@lixom.net>
| | * ARM: exynos_defconfig: Enable LM90 driverAndreas Faerber2015-01-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | multi_v7_defconfig has it as Y already, so build it in here, too, for consistency, and therefore build in HWMON as well. Signed-off-by: Andreas Faerber <afaerber@suse.de> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
| | * ARM: exynos_defconfig: Enable options for display panel supportJavier Martinez Canillas2015-01-121-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many Exynos devices have a display panel. Most of them just have a simple panel while others have more complex configurations that requires an embedded DisplayPort (eDP) to LVDS bridges. This patch enables the following features to be built in the kernel image to support both setups: - Direct Rendering Manager (DRM) - DRM bridge registration and lookup framework - Parade ps8622/ps8625 eDP/LVDS bridge - NXP ptn3460 eDP/LVDS bridge - Exynos Fully Interactive Mobile Display controller (FIMD) - Panel registration and lookup framework - Simple panels - Backlight & LCD device support Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kukjin Kim <kgene@kernel.org>
| | * arm: dts: Use pmu_system_controller phandle for dp phyVivek Gautam2015-01-082-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DP PHY now require pmu-system-controller to handle PMU register to control PHY's power isolation. Adding the same to dp-phy node. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
| * | reset: sunxi: fix spinlock initializationTyler Baker2015-01-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call spin_lock_init() before the spinlocks are used, both in early init and probe functions preventing a lockdep splat. I have been observing lockdep complaining [1] during boot on my a80 optimus [2] when CONFIG_PROVE_LOCKING has been enabled. This patch resolves the splat, and has been tested on a few other sunxi platforms without issue. [1] http://storage.kernelci.org/next/next-20150107/arm-multi_v7_defconfig+CONFIG_PROVE_LOCKING=y/lab-tbaker/boot-sun9i-a80-optimus.html [2] http://kernelci.org/boot/?a80-optimus Signed-off-by: Tyler Baker <tyler.baker@linaro.org> Cc: <stable@vger.kernel.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | Merge tag 'renesas-soc-fixes-for-v3.19' of ↵Olof Johansson2015-01-172-0/+10
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes Merge "Renesas ARM Based SoC Fixes for v3.19" from Simon Horman: Renesas ARM Based SoC Fixes for v3.19 This pull request is based on the last round of SoC updates for v3.19, Fourth Round of Renesas ARM Based SoC Updates for v3.19, tagged as renesas-soc3-for-v3.19, merged into your next/soc branch and included in v3.19-rc1. - ARM: shmobile: r8a7740: Instantiate GIC from C board code in legacy builds Set .control_parent for all irqpin instances for sh73a0 SoC when booting using legacy C. - ARM: shmobile: r8a7740: Instantiate GIC from C board code in legacy builds This fixes a long standing problem which has been present since the sh73a0 SoC started using the INTC External IRQ pin driver. The patch that introduced the problem is 341eb5465f67437a ("ARM: shmobile: INTC External IRQ pin driver on sh73a0") which was included in v3.10. * tag 'renesas-soc-fixes-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: sh73a0 legacy: Set .control_parent for all irqpin instances ARM: shmobile: r8a7740: Instantiate GIC from C board code in legacy builds
| | * | ARM: shmobile: sh73a0 legacy: Set .control_parent for all irqpin instancesGeert Uytterhoeven2015-01-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sh73a0 INTC can't mask interrupts properly most likely due to a hardware bug. Set the .control_parent flag to delegate masking to the parent interrupt controller, like was already done for irqpin1. Without this, accessing the three-axis digital accelerometer ADXL345 on kzm9g through /dev/input/event1 causes an interrupt storm, which requires a power-cycle to recover from. This was inspired by a patch for arch/arm/boot/dts/sh73a0.dtsi from Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Fixes: 341eb5465f67437a ("ARM: shmobile: INTC External IRQ pin driver on sh73a0") Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | ARM: shmobile: r8a7740: Instantiate GIC from C board code in legacy buildsGeert Uytterhoeven2014-12-191-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq domain."), armadillo-legacy hangs during boot with: sh-tmu.0: ch0: used for clock events sh-tmu.0: ch0: used for periodic clock events sh-tmu.0: ch0: failed to request irq 230 sh-tmu.0: ch1: used as clock source sh-cmt-48.1: ch0: failed to request irq 90 sh-cmt-48.1: ch0: registration failed earlytimer: unable to probe sh-cmt-48 early. Calibrating delay loop... This happens because the IRQ numbers of the GIC are now virtual, and no longer match the hardcoded hardware IRQ numbers in the platform board code. To fix this, instantiate the GIC from platform board code when compiling a legacy kernel, like is done on sh73a0 for kzm9g-legacy. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | ARM: dts: disable CCI on exynos5420 based arndale-octaAbhilash Kesavan2015-01-172-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arndale-octa board was giving "imprecise external aborts" during boot-up with MCPM enabled. CCI enablement of the boot cluster was found to be the cause of these aborts (possibly because the secure f/w was not allowing it). Hence, disable CCI for the arndale-octa board. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Tyler Baker <tyler.baker@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | drivers: bus: check cci device tree node statusAbhilash Kesavan2015-01-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm-cci driver completes the probe sequence even if the cci node is marked as disabled. Add a check in the driver to honour the cci status in the device tree. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | Merge tag 'at91-fixes' of ↵Olof Johansson2015-01-174-2/+22
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into fixes Merge "at91: fixes for 3.19 #1 (ter)" from Nicolas Ferre: First fixes batch for AT91 on 3.19: - fix some DT entries - correct clock entry for the at91sam9263 LCD - add a phy_fixup for Eth1 on sama5d4 * tag 'at91-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91: board-dt-sama5: add phy_fixup to override NAND_Tree ARM: at91/dt: sam9263: Add missing clocks to lcdc node ARM: at91: sama5d3: dt: correct the sound route ARM: at91/dt: sama5d4: fix the timer reg length Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | ARM: at91: board-dt-sama5: add phy_fixup to override NAND_TreeWenyou Yang2015-01-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Appearance: On some SAMA5D4EK boards, after power up, the Eth1 doesn't work. Reason: The PIOE2 pin is connected to the NAND_Tree# of KSZ8081, But it outputs LOW during the reset period, which cause the NAND_Tree# enabled. Add phy_fixup() to disable NAND_Tree by overriding the Operation Mode Strap Override register(i.e. Register 16h) to clear the NAND_Tree bit. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | | ARM: at91/dt: sam9263: Add missing clocks to lcdc nodeAlexander Stein2015-01-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | atmel_lcdfb needs also uses hclk clock, but AT91SAM9263 doesn't have that specific clock, so use lcd_clk twice. The same was done in arch/arm/mach-at91/at91sam9263.c Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | | ARM: at91: sama5d3: dt: correct the sound routeBo Shen2015-01-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MICBIAS is a supply, should route to MIC while not IN1L. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | | ARM: at91/dt: sama5d4: fix the timer reg lengthBo Shen2015-01-121-1/+1
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | The second property of reg is the length, so correct it for timer. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | | ARM: rockchip: disable jtag/sdmmc autoswitching on rk3288Heiko Stübner2015-01-171-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rk3288 SoCs have a function to automatically switch between jtag/sdmmc pinmux settings depending on the card state. This collides with a lot of assumptions. It only works when using the internal card-detect mechanism and breaks horribly when using either the normal card-detect via the slot-gpio function or via any other pin. Also there is of course no link between the mmc and jtag on the software-side, so the jtag clocks may very well be disabled when the card is ejected and the soc switches back to the jtag pinmux. Leaving the switching function enabled did result in mmc timeouts and rcu stalls thus hanging the system on 3.19-rc1. Therefore disable it in all cases, as we expect the devicetree to explicitly select either mmc or jtag pinmuxes anyway. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | Merge tag 'berlin-fixes-for-3.19-1' of ↵Olof Johansson2015-01-172-31/+34
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.infradead.org/users/hesselba/linux-berlin into fixes Merge "ARM: berlin: Fixes for v3.19 (round 1)" from Sebastian Hesselbarth: Marvell Berlin fixes for v3.19 round 1: - SDHCI DT fixes for BG2Q and BG2Q reference board - BG2Q SM GPIO DT node relocation * tag 'berlin-fixes-for-3.19-1' of git://git.infradead.org/users/hesselba/linux-berlin: ARM: dts: berlin: correct BG2Q's SM GPIO location. ARM: dts: berlin: add broken-cd and set bus width for eMMC in Marvell DMP DT ARM: dts: berlin: fix io clk and add missing core clk for BG2Q sdhci2 host Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | ARM: dts: berlin: correct BG2Q's SM GPIO location.Jisheng Zhang2015-01-071-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpio4 and gpio5 are in 0xf7fc0000 apb which is located in the SM domain. This patch moves gpio4 and gpio5 to the correct location. This patch also renames them as the following to match the names we internally used in marvell: gpio4 -> sm_gpio1 gpio5 -> sm_gpio0 porte -> portf portf -> porte This also matches what we did for BG2 and BG2CD's SM GPIO. Cc: stable@vger.kernel.org # 3.16+ Fixes: cedf57fc4f2f ("ARM: dts: berlin: add the BG2Q GPIO nodes") Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| | * | | ARM: dts: berlin: add broken-cd and set bus width for eMMC in Marvell DMP DTJisheng Zhang2015-01-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no card detection for the eMMC, so this patch adds the missing broken-cd property. This patch also sets bus width as 8 to add MMC_CAP_8_BIT_DATA in the Host capabilities. Cc: stable@vger.kernel.org # 3.16+ Fixes: 3047086dfd56 ("ARM: dts: berlin: enable SD card reader and eMMC for the BG2Q DMP") Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| | * | | ARM: dts: berlin: fix io clk and add missing core clk for BG2Q sdhci2 hostJisheng Zhang2015-01-071-1/+2
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On BG2Q, the sdhci2 host uses nfcecc for "io" clk and nfc for "core" clk. The shdci2 can't work without this patch due to the "core" clk is gated. Cc: stable@vger.kernel.org # 3.16+ Fixes: 0d859a6a9d14 ("ARM: dts: berlin: add the SDHCI nodes for the BG2Q") Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| * | | ARM: nomadik: fix up leftover device tree pinsLinus Walleij2015-01-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We altered the device tree bindings for the Nomadik family of pin controllers to be standard, this file was merged out-of-order so we missed fixing this. Fix it up. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | Merge tag 'omap-for-v3.19/fixes-rc1' of ↵Olof Johansson2015-01-179-17/+100
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Merge "omap fixes against v3.19-rc1" from Tony Lindgren: Fixes for omaps mostly to deal with dra7 timer issues and hypervisor mode. The other fixes are minor fixes for various boards. The summary of the fixes is: - Fix real-time counter rate typos for some frequencies - Fix counter frequency drift for am572x - Fix booting of secondary CPU in HYP mode - Fix n900 board name for legacy user space - Fix cpufreq in omap2plus_defconfig after Kconfig change - Fix dra7 qspi partitions And also, let's re-enable smc91x on some n900 boards that we have sitting in a few test boot systems after the boot loader dependencies got fixed. * tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Revert disabling of smc91x for n900 ARM: dts: dra7-evm: fix qspi device tree partition size ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT ARM: OMAP2+: Fix n900 board name for legacy user space ARM: omap5/dra7xx: Enable booting secondary CPU in HYP mode ARM: dra7xx: Fix counter frequency drift for AM572x errata i856 ARM: omap5/dra7xx: Fix frequency typos Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | ARM: dts: Revert disabling of smc91x for n900Tony Lindgren2015-01-061-3/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "ARM: dts: Disable smc91x on n900 until bootloader dependency is removed". We've now fixed the issues that caused problems with uninitialized hardware depending on the bootloader version. Mostly things got fixed with the following commits: 9a894953a97b ("ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins") 7d2911c43815 ("net: smc91x: Fix gpios for device tree based booting") Note that this only affects the early development boards with Ethernet that we still have in a few automated boot test systems. And it's also available supposedly in some versions of qemu. Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: dts: dra7-evm: fix qspi device tree partition sizeMugunthan V N2015-01-061-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 64KiB is allocated for qspi dtb partition which is not sufficient, so updating the partition table size to 512KiB for device tree partition. This also aligns the QSPI partition definitions between kernel and U-Boot. Fixes: dc2dd5b8 ("ARM: dts: dra7: Add qspi device") Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DTNishanth Menon2015-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_GENERIC_CPUFREQ_CPU0 disappeared with commit bbcf071969b20f ("cpufreq: cpu0: rename driver and internals to 'cpufreq_dt'") Use the renamed CONFIG_CPUFREQ_DT generic driver. It looks like with v3.18-rc1, commit bbcf071969b20f and fdc509b15eb3eb came in via different trees causing the resultant v3.18-rc1 to be non-functional for cpufreq as default supported with omap2plus_defconfig. Fixes: fdc509b15eb3eb ("ARM: omap2plus_defconfig: Add cpufreq to defconfig") Cc: <stable@vger.kernel.org> # 3.18 Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: OMAP2+: Fix n900 board name for legacy user spaceTony Lindgren2015-01-061-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | N900 legacy user space apps need the board name in /proc/cpuinfo to work properly for the Hardware entry. For other boards this should not be an issues and they can use the generic Hardware entry. Let's fix the issue by adding a custom DT_MACHINE_START for n900. Tested-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: omap5/dra7xx: Enable booting secondary CPU in HYP modeLennart Sorensen2015-01-063-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the boot loader enables HYP mode on the boot CPU, the secondary CPU also needs to call into the ROM to switch to HYP mode before booting. The firmwares on the omap5 and dra7xx unfortunately do not take care of this, so it has to be handled by the kernel. This patch is based on "[PATCH 2/2] ARM: OMAP5: Add HYP mode entry support for secondary CPUs" by Santosh Shilimkar <santosh.shilimkar@ti.com>, except this version does not require a compile time CONFIG to control if it should enable HYP mode or not, it simply does it based on the mode of the boot CPU, so it works whether the CPU boots in SVC or HYP mode, and should even work as a guest kernel inside kvm if qemu decides to support emulating the omap5 or dra7xx. Cc: stable@vger.kernel.org #v3.16+ Signed-off-by: Len Sorensen <lsorense@csclub.uwaterloo.ca> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: dra7xx: Fix counter frequency drift for AM572x errata i856Lennart Sorensen2015-01-062-2/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external crystal is not enabled at power up. Instead the CPU falls back to using an emulation for the 32KHz clock which is SYSCLK1/610. SYSCLK1 is usually 20MHz on boards so far (which gives an emulated frequency of 32.786KHz), but can also be 19.2 or 27MHz which result in much larger drift. Since this is used to drive the master counter at 32.768KHz * 375 / 2 = 6.144MHz, the emulated speed for 20MHz is of by 570ppm, or about 43 seconds per day, and more than the 500ppm NTP is able to tolerate. Checking the CTRL_CORE_BOOTSTRAP register can determine if the CPU is using the real 32.768KHz crystal or the emulated SYSCLK1/610, and by known that the real counter frequency can be determined and used. The real speed is then SYSCLK1 / 610 * 375 / 2 or SYSCLK1 * 75 / 244. Signed-off-by: Len Sorensen <lsorense@csclub.uwaterloo.ca> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: omap5/dra7xx: Fix frequency typosLennart Sorensen2015-01-061-4/+4
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The switch statement of the possible list of SYSCLK1 frequencies is missing a 0 in 4 out of the 7 frequencies. Fixes: fa6d79d27614 ("ARM: OMAP: Add initialisation for the real-time counter") Cc: stable@vger.kernel.org # v3.7+ Signed-off-by: Len Sorensen <lsorense@csclub.uwaterloo.ca> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | Merge tag 'imx-fixes-3.19' of ↵Olof Johansson2015-01-176-21/+13Star
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes Merge "ARM: imx: fixes for 3.19" from Shawn Guo: The i.MX fixes for 3.19: - One fix for incorrect i.MX25 SPI1 clock assignment in device tree, which causes system hang when accessing SPI1. - Correct i.MX6SX QSPI parent clock configuration to fix a kernel Oops. - Fix ULPI PHY reset modelling on imx51-babbage board to remove the dependency on bootloader for USB3317 ULPI PHY reset. - Correct video divider setting on i.MX6Q rev T0 1.0 to fix the issue that HDMI is not working at high resolution on T0 1.0. - One incremental fix for CODA960 VPU enabling in device tree to correct interrupt order. - LS1021A SCFG block works in BE mode, add device tree property big-endian to make it right. * tag 'imx-fixes-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling ARM: imx6sx: Set PLL2 as parent of QSPI clocks ARM: dts: imx25: Fix the SPI1 clocks ARM: clk-imx6q: fix video divider for rev T0 1.0 ARM: dts: imx6qdl: Fix CODA960 interrupt order ARM: ls1021a: dtsi: add 'big-endian' property for scfg node Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | ARM: dts: imx51-babbage: Fix ULPI PHY reset modellingFabio Estevam2015-01-061-17/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO2_5 is the reset GPIO for the USB3317 ULPI PHY. Instead of modelling it as a regulator, the correct approach is to use the 'reset_gpios' property of the "usb-nop-xceiv" node. GPIO1_7 is the reset GPIO for the USB2517 USB hub. As we currently don't have dt bindings to describe a HUB reset, let's keep using the regulator approach. Rename the regulator to 'reg_hub_reset' to better describe its function and bind it with the USB host1 port instead. USB host support has been introduced by commit 9bf206a9d13be3 ("ARM: dts: imx51-babbage: Add USB Host1 support"), which landed in 3.16 and it seems that USB has only been functional due to previous bootloader initialization. With this patch applied we can get USB host to work without relying on the bootloader. Cc: <stable@vger.kernel.org> # 3.16+ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-09-11 05:27:09 +0200