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| * [SPARC64]: Fix mini RTC driver reading.David S. Miller2006-03-201-0/+2
| | | | | | | | | | | | | | Need to subtract 1900 from year and 1 from month before giving it back to userspace. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Do not allow mapping pages within 4GB of 64-bit VA hole.David S. Miller2006-03-203-24/+73
| | | | | | | | | | | | | | | | | | | | The UltraSPARC T1 manual recommends this because the chip could instruction prefetch into the VA hole, and this would also make decoding certain kinds of memory access traps more difficult (because the chip sign extends certain pieces of trap state). Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix _PAGE_EXEC handling.David S. Miller2006-03-203-8/+15
| | | | | | | | | | | | | | | | | | | | | | First of all, use the known _PAGE_EXEC_{4U,4V} value instead of loading _PAGE_EXEC from memory. We either know which one to use by context, or we can code patch the test. Next, we need to check executability of a PTE in the generic TSB miss handler. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix typo in SUN4V D-TLB miss handler.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | Should put FAULT_CODE_DTLB into %g3 not FAULT_CODE_ITLB. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill bogus function externs in asm/pgtable.hDavid S. Miller2006-03-201-24/+0Star
| | | | | | | | | | | | These are all implemented inline earlier in the file. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add mini-RTC driver for Starfire and SUN4V.David S. Miller2006-03-201-0/+279
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix bugs in SUN4V cpu mondo dispatch.David S. Miller2006-03-203-57/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were several bugs in the SUN4V cpu mondo dispatch code. In fact, if we ever got a EWOULDBLOCK or other error from the hypervisor call, we'd potentially send a cpu mondo multiple times to the same cpu and even worse we could loop until the timeout resending the same mondo over and over to such cpus. So let's bulletproof this thing as follows: 1) Implement cpu_mondo_send() and cpu_state() hypervisor calls in arch/sparc64/kernel/entry.S, add prototypes to asm/hypervisor.h 2) Don't build and update the cpulist using inline functions, this was causing the cpu mask to not get updated in the caller. 3) Disable interrupts during the entire mondo send, otherwise our cpu list and/or mondo block could get overwritten if we take an interrupt and do a cpu mondo send on the current cpu. 4) Check for all possible error return types from the cpu_mondo_send() hypervisor call. In particular: HV_EOK) Our work is done, all cpus have received the mondo. HV_CPUERROR) One or more of the cpus in the cpu list we passed to the hypervisor are in error state. Use cpu_state() calls over the entries in the cpu list to see which ones. Record them in "error_mask" and report this after we are done sending the mondo to cpus which are not in error state. HV_EWOULDBLOCK) We need to keep trying. Any other error we consider fatal, we report the event and exit immediately. 5) We only timeout if forward progress is not made. Forward progress is defined as having at least one cpu get the mondo successfully in a given cpu_mondo_send() call. Otherwise we bump a counter and delay a little. If the counter hits a limit, we signal an error and report the event. Also, smp_call_function_mask() error handling reports the number of cpus incorrectly. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix bugs in SMP TLB context version expiration handling.David S. Miller2006-03-201-6/+10
| | | | | | | | | | | | | | | | | | 1) We must flush the TLB, duh. 2) Even if the sw context was seen to be valid, the local cpu's hw context can be out of date, so reload it unconditionally. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix indexing into kpte_linear_bitmap.David S. Miller2006-03-201-0/+1
| | | | | | | | | | | | | | Need to shift back up by 3 bits to get 8-byte entry index. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Use 13-bit context size always.David S. Miller2006-03-201-13/+1Star
| | | | | | | | | | | | | | We no longer have the problems that require using the smaller sizes. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Avoid dcache-dirty page state management on sun4v.David S. Miller2006-03-202-23/+30
| | | | | | | | | | | | | | It is totally wasted work, since we have no D-cache aliasing issues on sun4v. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Bulletproof hypervisor TLB flushing.David S. Miller2006-03-202-26/+80
| | | | | | | | | | | | | | | | | | | | | | Check TLB flush hypervisor calls for errors and report them. Pass HV_MMU_ALL always for now, we can add back the optimization to avoid the I-TLB flush later. Always explicitly page align the virtual address arguments. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Report mondo error correctly in hypervisor_xcall_deliver().David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | It's in "arg0" not "func". Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Niagara optimized XOR functions for RAID.David S. Miller2006-03-203-5/+342
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix binfmt_aout32.c build.Andrew Morton2006-03-201-1/+1
| | | | | | | | | | Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: destroy_context() needs to disable interrupts.David S. Miller2006-03-201-2/+3
| | | | | | | | | | | | | | | | | | | | get_new_mmu_context() can be invoked from interrupt context now for the new SMP version wrap handling. So disable interrupt while taking ctx_alloc_lock in destroy_context() so we don't deadlock. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix TLB context allocation with SMT style shared TLBs.David S. Miller2006-03-204-25/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The context allocation scheme we use depends upon there being a 1<-->1 mapping from cpu to physical TLB for correctness. Chips like Niagara break this assumption. So what we do is notify all cpus with a cross call when the context version number changes, and if necessary this makes them allocate a valid context for the address space they are running at the time. Stress tested with make -j1024, make -j2048, and make -j4096 kernel builds on a 32-strand, 8 core, T2000 with 16GB of ram. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Put syscall tables after trap table.David S. Miller2006-03-201-1/+2
| | | | | | | | | | | | | | Otherwise with too much stuff enabled in the kernel config we can end up with an unaligned trap table. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Export _PAGE_E and _PAGE_CACHE to modules.David S. Miller2006-03-201-0/+4
| | | | | | | | | | | | | | | | SBUS flash driver needs it. Noticed by Fabbione. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix %tstate ASI handling in start_thread{,32}()David S. Miller2006-03-201-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Niagara helps us find a ancient bug in the sparc64 port :-) The ASI_* values are plain constant defines, thus signed 32-bit on sparc64. To put shift this into the regs->tstate value we were doing or'ing "(ASI_PNF << 24)" into there. ASI_PNF is 0x82 and shifted left by 24 makes that topmost bit the sign bit in a 32-bit value. This would get sign extended to 64-bits and thus corrupt the top-half of the reg->tstate value. This never caused problems in pre-Niagara cpus because the only thing up there were the condition code values. But Niagara has the global register level field, and this all 1's value is illegal there so Niagara gives an illegal instruction trap due to this bug. I'm pretty sure this bug is about as old as the sparc64 port itself. This also points out that we weren't setting ASI_PNF for 32-bit tasks. We should, so fix that while we're here. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Drop %gl to 0 before re-enabling PSTATE_IE in rtrapDavid S. Miller2006-03-201-1/+2
| | | | | | | | | | | | | | | | If we take a window fault, on SUN4V set %gl to zero before we turn PSTATE_IE back on in %pstate. Otherwise if we take an interrupt we'll end up with corrupt register state. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.David S. Miller2006-03-203-6/+48
| | | | | | | | | | | | | | | | | | | | It can map all of the linear kernel mappings with zero TSB hash conflicts for systems with 16GB or less ram. In such cases, on SUN4V, once we load up this TSB the first time with all the mappings, we never take a linear kernel mapping TLB miss ever again, the hypervisor handles them all. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings.David S. Miller2006-03-202-15/+96
| | | | | | | | | | | | | | | | | | | | | | We use a bitmap, one bit for every 256MB of memory. If the bit is set we can use a 256MB PTE for linear mappings, else we have to use a 4MB PTE. SUN4V support is there, and we can very easily add support for Panther cpu 256MB PTEs in the future. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Use sun4v_cpu_idle() in cpu_idle() on SUN4V.David S. Miller2006-03-201-49/+32Star
| | | | | | | | | | | | | | | | | | | | | | We have to turn off the "polling nrflag" bit when we sleep the cpu like this, so that we'll get a cross-cpu interrupt to wake the processor up from the yield. We also have to disable PSTATE_IE in %pstate around the yield call and recheck need_resched() in order to avoid any races. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64] math-emu: Delete debugging printk left by previous commit.David S. Miller2006-03-201-1/+0Star
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add sun4v_cpu_yield().David S. Miller2006-03-202-0/+12
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill cpudata->idle_volume.David S. Miller2006-03-203-11/+3Star
| | | | | | | | | | | | | | | | | | Set, but never used. We used to use this for dynamic IRQ retargetting, but that code died a long time ago. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Niagara optimized memset/bzero/clear_user.David S. Miller2006-03-203-1/+165
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Pass multiple CPUs at once to hypervisor cross-call API.David S. Miller2006-03-201-54/+0Star
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Args to SUNW,set-trap-table are 64-bit.David S. Miller2006-03-201-2/+7
| | | | | | | | | | | | | | | | They were getting truncated to 32-bit and this is very bad when your MMU fault status area is in physical memory above 4GB on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Handle unimplemented FPU square-root on Niagara.David S. Miller2006-03-201-2/+23
| | | | | | | | | | | | | | | | The math-emu code only expects unfinished fpop traps when emulating FPU sqrt instructions on pre-Niagara chips. On Niagara we can get unimplemented fpop, so handle that. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC] serial: Make sure sysfs nodes get named correctly.David S. Miller2006-03-204-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Because we play this trick where we use ttyS? in increasing minor numbers for different sunfoo.c drivers, we have to inform the TTY layer of this. Do so by setting the tty->name_base appropriately. Probably there should be a generic way to do this in the serial core, but for now... Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Typo in sun4v_data_access_exception log message.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | Should be "Dax" not "Iax". Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Handle zero-length map requests in pci_sun4v.cDavid S. Miller2006-03-201-2/+2
| | | | | | | | | | | | | | By simply changing the do-while loop into a plain while loop. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill stray PGLIST_NENTS check in pci_sun4v.cDavid S. Miller2006-03-201-2/+0Star
| | | | | | | | | | | | | | I forgot to remove the one in pci_4v_map_sg() during the iommu batching commit. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix typo in dump_tl1_traplog()David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | Actually make use of the 'limit' we compute. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Disable smp_report_regs() for now.David S. Miller2006-03-201-1/+2
| | | | | | | | | | | | | | | | | | | | It's extremely noisy and causes much grief on slow consoles with large numbers of cpus. We'll have to provide this some saner way in order to re-enable this. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Remove PGLIST_NENTS PCI IOMMU mapping limitation on SUN4V.David S. Miller2006-03-203-83/+171
| | | | | | | | | | | | | | Use a batching queue system for IOMMU mapping setup, with a page sized batch. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Use KERN_EMERG in dump_tl1_traplog() and sun4v TLB errors.David S. Miller2006-03-201-7/+13
| | | | | | | | | | | | | | We're about to seriously die in these cases so it is important that the messages make it to the console. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix unaligned access winfxup handling on SUN4V.David S. Miller2006-03-202-17/+34
| | | | | | | | | | | | | | | | | | | | | | Another case where we have to force ourselves into global register level one. Also make sure the arguments passed to sun4v_do_mna() are correct. This area actually needs some more work, for example spill fixup is not necessarily going to do the right thing for this case. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Set %gl to 1 in kvmap_itlb_longpath on SUN4V.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | | | | | Just like kvmap_dtlb_longpath we have to force the global register level to one in order to mimick the PSTATE_MG --> PSTATE_AG trasition done on SUN4U. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64] sunhv: Fix locking in sunhv_start_tx()David S. Miller2006-03-201-6/+2Star
| | | | | | | | | | | | | | | | | | | | Caller takes the lock already. Also, fixup the poll loop in sunhv_break_ctl(). Just like in console write, we udelay(2) and use a loop limit of 1000000 iterations. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Put sunhv.o earliest in the list of sparc serial drivers.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | | | | | So that it will show up as /dev/ttyS0. Otherwise things like installers will try to run on whatever serial port gets probed first. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Export a PAGE_SHARED symbol.David S. Miller2006-03-202-0/+6
| | | | | | | | | | | | For drivers/media/*, noticed by Fabbione. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64] Fix build if CONFIG_HUGETLB_PAGE is not setFabio M. Di Nitto2006-03-201-0/+2
| | | | | | | | | | Signed-off-by: Fabio M. Di Nitto <fabbione@ubuntu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: More TLB/TSB handling fixes.David S. Miller2006-03-209-57/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SUN4V convention with non-shared TSBs is that the context bit of the TAG is clear. So we have to choose an "invalid" bit and initialize new TSBs appropriately. Otherwise a zero TAG looks "valid". Make sure, for the window fixup cases, that we use the right global registers and that we don't potentially trample on the live global registers in etrap/rtrap handling (%g2 and %g6) and that we put the missing virtual address properly in %g5. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Don't do anything in flush_ptrace_access() on SUN4V.David S. Miller2006-03-201-0/+3
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix some SUN4V TLB handling bugs.David S. Miller2006-03-203-5/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add error return checking for TLB load hypervisor calls. 2) Don't fallthru to dtlb tsb miss handler from itlb tsb miss handler, oops. 3) On window fixups, propagate fault information to fixup handler correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Check for errors in hypervisor_tlb_lock().David S. Miller2006-03-201-0/+5
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Init boot cpu's trap_block[] before paging_init()David S. Miller2006-03-201-2/+2
| | | | | | | | | | | | It must be ready when we take over the trap table. Signed-off-by: David S. Miller <davem@davemloft.net>
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