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* dt-bindings: msm/dsi: Add assigned clocks bindingsArchit Taneja2016-07-161-1/+15
| | | | | | | | | | | | | | | The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC uses these as source clocks for some of its RCGs to generate clocks that finally feed to the DSI host controller. Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to the DSI host. Use the DSI PHY provided clocks to set up the parents of these assigned clocks. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* dt-bindings: msm/dsi: Modify port and PHY bindingsArchit Taneja2016-07-161-11/+34
| | | | | | | | | | | | | The DSI node now has two ports that describe the connection between the MDP interface output and the DSI input, and the connection between the DSI output and the connected panel/bridge. Update the properties and the example. Also, use generic PHY bindings instead of the custom one. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* dt-bindings: msm/dsi: Use standard data lanes bindingArchit Taneja2016-07-161-18/+19
| | | | | | | | | | | | | | | | | | | The "qcom,data-lane-map" binding mentioned in the document is changed to the more generic "data-lanes" property specified in: Documentation/devicetree/bindings/media/video-interfaces.txt The previous binding expressed physical to logical data lane mappings, the standard "data-lanes" binding uses logical to physical data lane mappings. Update the docs to reflect this change. The example had the property incorrectly named as "lanes", update this too. The MSM DSI DT bindings aren't used anywhere at the moment, so it's okay to update this property. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Use a standard DT binding for data lanesArchit Taneja2016-07-161-3/+14
| | | | | | | | | | | | | | | | A more standard DT binding describing data lanes already exists here: Documentation/devicetree/bindings/media/video-interfaces.txt Use this binding instead of "qcom,data-lane-map". One difference in the standard binding w.r.t to the existing binding is that it provides a logical to physical mapping instead of the other way round. Tweak the code to translate the data the way we want it. The MSM DSI DT bindings aren't used anywhere at the moment, so it's okay to update this property. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Use generic PHY bindingsArchit Taneja2016-07-161-1/+1
| | | | | | | | | The DSI host links to the DSI PHY device using a custom binding. Switch to the generic PHY bindings. The DSI PHY driver itself doesn't use the common PHY framework for now. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Modify port parsingArchit Taneja2016-07-161-5/+5
| | | | | | | | | | | | | | | | | | The DSI interface is going to have two ports defined in its device node. The first port is always going to be the link between the MDP output and the input to DSI, the second port is going to be the link between the DSI output and the connected panel/bridge: ----- ----- ------- | MDP | ------> | DSI | ------> | Panel | ----- ----- ------- (Port 0) (Port 1) Until now, there was only one Port representing the output. Update the DSI host driver such that it parses Port #1 for a connected device. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* dt-bindings: msm/mdp: Fix up clock related bindingsArchit Taneja2016-07-161-7/+5Star
| | | | | | | | | | | | | | | | | Address some issues wiht clock related bindings. It's okay to change these since these bindings aren't used in any dtsi files until now. MDP5: - Don't ask for source clock MDP4: - Give a better name for MDP_TV_CLK - Remove TV_SRC - Add MDP_AXI_CLK Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: Clean up some MDP4 clocksArchit Taneja2016-07-162-20/+13Star
| | | | | | | | | | | | | | | | | Fix some issues with MDP4 clocks: - mdp4_dtv_encoder tries to get "src_clk", which is a RCG(TV_SRC) in MSM8960 and APQ8064. This isn't something the driver should access or configure. Instead of this, configure the "mdp_clk" (MDP_TV_CLK), a branch clock in MMCC that has the TV_SRC as its parent. Setting rate/enabling the "mdp_clk" will eventually configure "src_clk", which is what we want. - Rename "mdp_clk" to "tv_clk" because that's slightly less confusing. - Rename "mdp_axi_clk" to "bus_clk" because that's what we do elsewhere too. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Don't get source of MDP core clockArchit Taneja2016-07-162-6/+2Star
| | | | | | | | | | The driver expects DT to provide the parent to MDP core clock. The only operation done to the parent clock is to set a rate. This can be achieved by setting the rate on the core clock itsef. Don't try to get the parent clock anymore. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Print the correct virtual addresses in map/unmap funcsArchit Taneja2016-07-161-2/+2
| | | | | | | | The msm_iommu_map/unmap funcs have debug prints to show the list of VA:PA mappings. Use the correct variable to print the VAs. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Use correct type for physical addressesArchit Taneja2016-07-161-2/+2
| | | | | | | | | The u32 type used to pass the physical addresses to iommu_map can't accommodate 64 bit addresses. Move to dma_addr_t to ensure wrong addresses aren't provided to the IOMMU driver. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* Merge tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux into ↵Dave Airlie2016-07-166-44/+496
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drm-next This pull request brings in vc4 shader validation for branching, allowing GLSL shaders with non-unrolled loops. * tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux: drm/vc4: Fix a "the the" typo in a comment. drm/vc4: Fix definition of QPU_R_MS_REV_FLAGS drm/vc4: Add a getparam to signal support for branches. drm/vc4: Add support for branching in shader validation. drm/vc4: Add a bitmap of branch targets during shader validation. drm/vc4: Move validation's current/max ip into the validation struct. drm/vc4: Add a getparam ioctl for getting the V3D identity regs.
| * drm/vc4: Fix a "the the" typo in a comment.Eric Anholt2016-07-161-1/+1
| | | | | | | | Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Fix definition of QPU_R_MS_REV_FLAGSEric Anholt2016-07-161-1/+1
| | | | | | | | | | | | | | We don't use it in shader validation currently, so it had no effect, but best to fix it anyway in case we do some day. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Add a getparam to signal support for branches.Eric Anholt2016-07-162-0/+4
| | | | | | | | | | | | | | | | Userspace needs to know if it can create shaders that do branching. Otherwise, for backwards compatibility with old kernels it needs to lower if statements to conditional assignments. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Add support for branching in shader validation.Eric Anholt2016-07-164-17/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're already checking that branch instructions are between the start of the shader and the proper PROG_END sequence. The other thing we need to make branching safe is to verify that the shader doesn't read past the end of the uniforms stream. To do that, we require that at any basic block reading uniforms have the following instructions: load_imm temp, <next offset within uniform stream> add unif_addr, temp, unif The instructions are generated by userspace, and the kernel verifies that the load_imm is of the expected offset, and that the add adds it to a uniform. We track which uniform in the stream that is, and at draw call time fix up the uniform stream to have the address of the start of the shader's uniforms at that location. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Add a bitmap of branch targets during shader validation.Eric Anholt2016-07-162-2/+124
| | | | | | | | | | | | | | | | | | | | This isn't used yet, it's just a first step toward loop validation. During the main parsing of instructions, we need to know when we hit a new basic block so that we can reset validated state. v2: Fix a stray semicolon after an if block. (caught by kbuild test). Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Move validation's current/max ip into the validation struct.Eric Anholt2016-07-141-24/+30
| | | | | | | | | | | | | | Reduces the argument count for some of the functions, and will be used more with the upcoming looping support. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Add a getparam ioctl for getting the V3D identity regs.Eric Anholt2016-07-142-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | As I extend the driver to support different V3D revisions, userspace needs to know what version it's targeting. This is most easily detected using the V3D identity registers. v2: Make sure V3D is runtime PM on when reading the registers. v3: Switch to a 64-bit param value (suggested by Rob Clark in review) Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2) Reviewed-by: Rob Clark <robdclark@gmail.com> (v3, over irc)
* | Merge tag 'drm/panel/for-4.8-rc1' of ↵Dave Airlie2016-07-168-5/+204
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/panel: Changes for v4.8-rc1 This set of changes contains a few cleanups for existing panels as well as improved handling of certain backlights. In addition there's support for a few new simple panels. * tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/panel: simple: Add support for Starry KR122EA0SRA panel dt-bindings: Add Starry KR122EA0SRA panel binding dt-bindings: Add vendor prefix for Starry dt-bindings: display: Add Sharp LQ101K1LY04 panel binding drm/panel: simple: Add support for Sharp LQ101K1LY04 drm/panel: simple: Add support for LG LP079QX1-SP0V panel dt-bindings: Add support for LG LP079QX1-SP0V panel drm/panel: simple: Add support for Sharp LQ123P1JX31 panel dt-bindings: Add Sharp LQ123P1JX31 panel binding drm/panel: simple: Add support for Samsung LSN122DL01-C01 panel dt-bindings: Add Samsung LSN122DL01-C01 panel binding drm/panel: simple: Add support for LG LP097QX1-SPA1 panel dt-bindings: Add LG LP097QX1-SPA1 panel binding drm/panel: simple: Update backlight state property drm/panel: simple: Remove gratuitous blank line drm/panel: simple: Fix a couple of physical sizes
| * | drm/panel: simple: Add support for Starry KR122EA0SRA panelDouglas Anderson2016-07-111-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected using eDP interfaces. EDID shows: Detailed mode: Clock 147.000 MHz, 263 mm x 164 mm 1920 1936 1952 1984 hborder 0 1200 1215 1217 1235 vborder 0 -hsync -vsync Manufacturer-specified data, tag 15 ASCII string: STARRY ASCII string: KR122EA0SRA Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | dt-bindings: Add Starry KR122EA0SRA panel bindingDouglas Anderson2016-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected using eDP interfaces. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | dt-bindings: Add vendor prefix for StarryDoug Anderson2016-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From their website: http://www.b001.com.cn/ Starry appears to be a company involved in LCD panels and related components. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | dt-bindings: display: Add Sharp LQ101K1LY04 panel bindingJoshua Clayton2016-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Sharp LQ101K1LY04 is a 10" WXGA (1280x800) LVDS panel and is compatible with the simple-panel binding. Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for Sharp LQ101K1LY04Joshua Clayton2016-07-111-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | Add simple-panel support for the Sharp LQ101K1LY04, which is a 10" WXGA (1280x800) LVDS panel. Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for LG LP079QX1-SP0V panelYakir Yang2016-07-111-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and 32 pins eDP interface. This module supports 1536x2048 mode. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | dt-bindings: Add support for LG LP079QX1-SP0V panelYakir Yang2016-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and 32 pins eDP interface. This module supports 1536x2048 mode. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for Sharp LQ123P1JX31 panelYakir Yang2016-07-111-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sharp LQ123P1JX31 is an 12.3", 2400x1600 TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | dt-bindings: Add Sharp LQ123P1JX31 panel bindingYakir Yang2016-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sharp LQ123P1JX31 is an 12.3" 2400x1600 TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for Samsung LSN122DL01-C01 panelYakir Yang2016-07-111-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | dt-bindings: Add Samsung LSN122DL01-C01 panel bindingYakir Yang2016-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for LG LP097QX1-SPA1 panelYakir Yang2016-07-111-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | dt-bindings: Add LG LP097QX1-SPA1 panel bindingYakir Yang2016-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Update backlight state propertyThierry Reding2016-07-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Some backlight drivers ignore the power property and instead only use the state property. Fixup the panel driver to set the state property in addition to the power property. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Remove gratuitous blank lineThierry Reding2016-06-131-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | This blank line was introduced in commit c8521969dea2 ("drm/panel: simple: Add support for BOE TV080WUM-NL0"), likely by mistake. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Fix a couple of physical sizesThierry Reding2016-06-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Both the Innolux ZJ070NA-01P and Samsung LTN101NT05 were listing the horizontal and vertical resolutions in the size.width and size.height fields, whereas they should contain the physical dimensions of the panel. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | | Merge tag 'drm/tegra/for-4.8-rc1' of ↵Dave Airlie2016-07-1628-702/+1636
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.8-rc1 This set of changes contains a bunch of cleanups to the host1x driver as well as the addition of a pin controller for DPAUX, which is required by boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C mode (for HDMI and DDC). Included is also a bit of rework of the SOR driver in preparation to add DisplayPort support as well as some refactoring and cleanup. Finally, all output drivers are converted to runtime PM, which greatly simplifies the handling of clocks and resets. * tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits) drm/tegra: sor: Reject HDMI 2.0 modes drm/tegra: sor: Prepare for generic PM domain support drm/tegra: dsi: Prepare for generic PM domain support drm/tegra: sor: Make XBAR configurable per SoC drm/tegra: sor: Use sor1_src clock to set parent for HDMI dt-bindings: display: tegra: Add source clock for SOR drm/tegra: sor: Implement sor1_brick clock drm/tegra: sor: Implement runtime PM drm/tegra: hdmi: Implement runtime PM drm/tegra: dsi: Implement runtime PM drm/tegra: dc: Implement runtime PM drm/tegra: hdmi: Enable audio over HDMI drm/tegra: sor: Do not support deep color modes drm/tegra: sor: Extract tegra_sor_mode_set() drm/tegra: sor: Split out tegra_sor_apply_config() drm/tegra: sor: Rename tegra_sor_calc_config() drm/tegra: sor: Factor out tegra_sor_set_parent_clock() drm/tegra: dpaux: Add pinctrl support dt-bindings: Add bindings for Tegra DPAUX pinctrl driver drm/tegra: Prepare DPAUX for supporting generic PM domains ...
| * | | drm/tegra: sor: Reject HDMI 2.0 modesThierry Reding2016-07-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling HDMI 2.0 modes requires extra programming and will not work with the current driver, so reject all those modes. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: sor: Prepare for generic PM domain supportJon Hunter2016-07-141-22/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SOR driver for Tegra requires the SOR power partition to be enabled. Now that Tegra supports the generic PM domain framework we manage the SOR power partition via this framework. However, the sequence for gating/ungating the SOR power partition requires that the SOR reset is asserted/de-asserted at the time the SOR power partition is gated/ungated, respectively. Now that the reset control core assumes that resets are exclusive, the Tegra generic PM domain code and the SOR driver cannot request the same reset unless we mark the reset as shared. Sharing resets will not work in this case because we cannot guarantee that the reset will be asserted/de-asserted at the appropriate time. Therefore, given that the Tegra generic PM domain code will handle the resets, do not request the reset in the SOR driver if the SOR device has a PM domain associated. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: dsi: Prepare for generic PM domain supportJon Hunter2016-07-141-11/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSI driver for Tegra requires the SOR power partition to be enabled. Now that Tegra supports the generic PM domain framework we manage the SOR power partition via this framework. However, the sequence for gating/ungating the SOR power partition requires that the DSI reset is asserted/de-asserted at the time the SOR power partition is gated/ungated, respectively. Now that the reset control core assumes that resets are exclusive, the Tegra generic PM domain code and the DSI driver cannot request the same reset unless we mark the reset as shared. Sharing resets will not work in this case because we cannot guarantee that the reset will be asserted/de-asserted at the appropriate time. Therefore, given that the Tegra generic PM domain code will handle the resets, do not request the reset in the DSI driver if the DSI device has a PM domain associated. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: sor: Make XBAR configurable per SoCThierry Reding2016-07-141-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a per-SoC mapping of lanes which can be used to configure the XBAR. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: sor: Use sor1_src clock to set parent for HDMIThierry Reding2016-07-141-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running in HDMI mode, the sor1 IP block needs to use the sor1_src as parent clock, and in turn configure the sor1_src to use pll_d2_out0 as its parent. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | dt-bindings: display: tegra: Add source clock for SORThierry Reding2016-07-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SOR clock can have various sources, with the most commonly used being the sor_safe, pll_d2_out0, pll_dp and sor_brick clocks. These are configured using a three level mux, of which the first 2 levels can be treated as one. The direct parents of the SOR clock are the sor_safe, sor_brick and sor_src clocks, whereas the pll_d2_out0 and pll_dp clocks can be selected as parents of the sor_src clock via a second mux. Previous generations of Tegra have only supported eDP and LVDS with the SOR, where LVDS was never used on publicly available hardware. Clocking for this only ever required the first level mux (to select between sor_safe and sor_brick). Tegra210 has a new revision of the SOR that supports HDMI and hence needs to support the second level mux to allow selecting pll_d2_out0 as the SOR clock's parent. This second mux is knows as sor_src, and operating system software needs a reference to it in order to select the proper parent. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: sor: Implement sor1_brick clockThierry Reding2016-07-141-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sor1_brick is a clock that can be used as a source for the sor1 clock. The registers to control the clock output are part of the sor1 IP block and hence the sor driver is the best place to implement it. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: sor: Implement runtime PMThierry Reding2016-07-041-19/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use runtime PM to clock-(un)gate and (de)assert reset to the SOR controller. This ties in nicely with atomic DPMS in that a runtime PM reference is taken before a pipe is enabled and dropped after it has been shut down. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: hdmi: Implement runtime PMThierry Reding2016-07-041-47/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use runtime PM to clock-(un)gate and (de)assert reset to the HDMI controller. This ties in nicely with atomic DPMS in that a runtime PM reference is taken before a pipe is enabled and dropped after it has been shut down. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: dsi: Implement runtime PMThierry Reding2016-07-041-103/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use runtime PM to clock-(un)gate, (de)assert reset and control power to the DSI controller. This ties in nicely with atomic DPMS in that a runtime PM reference is taken before a pipe is enabled and dropped after it has been shut down. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: dc: Implement runtime PMThierry Reding2016-07-042-71/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use runtime PM to clock-gate, assert reset and powergate the display controller. This ties in nicely with atomic DPMS in that a runtime PM reference is taken before a pipe is enabled and dropped after it has been shut down. To make sure this works, make sure to only ever update planes on active CRTCs, otherwise register accesses to a clock-gated and reset CRTC will hang the CPU. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: hdmi: Enable audio over HDMIThierry Reding2016-07-043-105/+361
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to use the HDA codec to forward audio data to the HDMI codec it needs the ELD that is parsed from the monitor's EDID. Also implement an interoperability mechanism between the HDA controller and the HDMI codec. This uses vendor-defined scratch registers to pass data from the HDMI codec driver to the HDMI driver (that implements the receiving end of the HDMI codec). A custom format is used to pass audio sample rate and channel count to the HDMI driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | drm/tegra: sor: Do not support deep color modesThierry Reding2016-07-042-14/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Current generations of Tegra do not support deep color modes, so force 8 bits per color even if the connected monitor or panel supports more. Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-08 23:09:19 +0200