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* ARM: BCM: Enable ARM erratum 798181 for BRCMSTBGregory Fong2015-08-111-0/+1
| | | | | | | | | | | Commit 04fcab32d3fa1d3f6afe97e0ab431c5572e07a2c ("ARM: 8111/1: Enable erratum 798181 for Broadcom Brahma-B15") enables this erratum for affected Broadcom Brahma-B15 CPUs when CONFIG_ARM_ERRATA_798181=y. Let's make sure that config option is actually set. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: davinci: cp_intc: use IRQCHIP_SKIP_SET_WAKE instead of irq_set_wake ↵Sudeep Holla2015-08-051-11/+1Star
| | | | | | | | | | | | | | | | | callback Commit 60f96b41f71d ("genirq: Add IRQCHIP_SKIP_SET_WAKE flag") introduced a new flag to skip the irq_set_wake callback in the irqchip core to avoid adding dummy irq_set_wake in the irqchip implementations. This patch removes the dummy callback and sets the IRQCHIP_SKIP_SET_WAKE flags. Cc: Sekhar Nori <nsekhar@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* soc: mediatek: Fix SCPSYS compilationMatthias Brugger2015-08-051-0/+1
| | | | | | | | | | | SCPSYS driver misses the module.h include which makes it fail when compiling with allmodconf. This patch fixes this. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'mvebu-soc-4.3-1' of git://git.infradead.org/linux-mvebu into next/socOlof Johansson2015-08-054-39/+103
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mvebu soc changes for v4.3 (part #1) - Extend suspend to RAM support in order to add new mvebu SoC - Add standby support for all Armada 3xx/XP SoCs * tag 'mvebu-soc-4.3-1' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Warn about the wake-up sources not taken into account in suspend ARM: mvebu: Add standby support ARM: mvebu: Use __init for the PM initialization functions ARM: mvebu: prepare pm-board.c for the introduction of Armada 38x support ARM: mvebu: prepare mvebu_pm_store_bootinfo() to support multiple SoCs ARM: mvebu: do not check machine in mvebu_pm_init() ARM: mvebu: prepare set_cpu_coherent() for future extension Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: mvebu: Warn about the wake-up sources not taken into account in suspendGregory CLEMENT2015-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the Armada 370/XP/38x/39x SoCs when the suspend to ram feature is supported, the SoCs are shutdown and will be woken up by an external micro-controller, so there is no possibility to setup wake-up sources from Linux. However, in standby mode, the SoCs stay powered and it is possible to wake-up from any interrupt sources. Since when the users configures the enabled wake-up sources there is no way to know if the user will be doing suspend to RAM or standby, we just allow all wake-up sources to be enabled, and only warn when entering suspend to RAM The purpose of this patch is to inform the user that in suspend to ram mode, the wake-up sources won't be taken into consideration. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM: mvebu: Add standby supportGregory CLEMENT2015-07-253-12/+56
| | | | | | | | | | | | | | | | | | | | | | | | Until now only one Armada XP and one Armada 388 based board supported suspend to ram. However, most of the recent mvebu SoCs can support the standby mode. Unlike for the suspend to ram, nothing special has to be done for these SoCs. This patch allows the system to use the standby mode on Armada 370, 38x, 39x and XP SoCs. There are issues with the Armada 375, and the support might be added (if possible) in a future patch. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM: mvebu: Use __init for the PM initialization functionsGregory CLEMENT2015-07-252-2/+2
| | | | | | | | | | | | | | | | mvebu_pm_init and mvebu_armada_pm_init are only called during boot, so flag them with __init and save some memory. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
| * ARM: mvebu: prepare pm-board.c for the introduction of Armada 38x supportThomas Petazzoni2015-07-251-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm-board.c code contains the board-specific logic to enter suspend to RAM. Until now, the code supported only the Armada XP GP board, so all functions and symbols were named with armada_xp_gp. However, it turns out that the Armada 388 GP also uses the same 3 GPIOs protocol to talk to the PIC microcontroller that controls the power supply. Since we are going to re-use the same code with no change for Armada 38x, this commit renames the functions and symbols to use just "armada" instead of "armada_xp_gp". Better names can be found if one day other boards having a different protocol/mechanism are supported in the kernel. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM: mvebu: prepare mvebu_pm_store_bootinfo() to support multiple SoCsThomas Petazzoni2015-07-251-4/+21
| | | | | | | | | | | | | | | | | | | | | | As we are going to introduce support for Armada 38x in pm.c, split out the Armada XP part of mvebu_pm_store_bootinfo() into mvebu_pm_store_armadaxp_bootinfo(), and make the former retunr an error when an unsupported SoC is used. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM: mvebu: do not check machine in mvebu_pm_init()Thomas Petazzoni2015-07-251-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mvebu_pm_init() initializes the support for suspend/resume, and before doing that, it checks if we are on a board on which suspend/resume is actually supported. However, this check is already done by mvebu_armada_xp_gp_pm_init(), and there is no need to duplicate the check: callers of mvebu_pm_init() should now what they are doing. This commit is done in preparation to the addition of suspend/resume support on Armada 38x. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM: mvebu: prepare set_cpu_coherent() for future extensionNadav Haklai2015-07-251-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prepares the set_cpu_coherent() function in coherency.c to be extended to support other SoCs than Armada XP. It will be needed on Armada 38x to re-enable the coherency after exiting from suspend to RAM. This preparation simply moves the function further down in coherency.c so that it can use coherency_type(), and uses that function to only do the Armada XP specific work if we are on Armada XP. Signed-off-by: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | Merge tag 'zynq-soc-for-4.3' of https://github.com/Xilinx/linux-xlnx into ↵Olof Johansson2015-08-055-6/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/soc arm: Xilinx Zynq SoC patches for v4.2 - Fix earlyprintk, jump trampoline for SMP - Update git tree location - Setup PL310 aux (bit 22) * tag 'zynq-soc-for-4.3' of https://github.com/Xilinx/linux-xlnx: ARM: zynq: reserve space for jump target in secondary trampoline clk: zynq: remove redundant $(CONFIG_ARCH_ZYNQ) in Makefile MAINTAINERS: Update Zynq git tree location ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1) ARM: zynq: Fix earlyprintk in big endian mode Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: zynq: reserve space for jump target in secondary trampolineNathan Lynch2015-07-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a zero argument to the .word directive in zynq_secondary_trampoline. Without an expression the assembler emits nothing for the .word directive. This makes it so that the intended range is communicated to ioremap and outer_flush_range in zynq_cpun_start; e.g. for LE trampoline_code_size evaluates to 12 now instead of 8. Found by inspection. I'm not aware of any real problem this fixes. Tested by doing on online/offline loop on ZC702. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | clk: zynq: remove redundant $(CONFIG_ARCH_ZYNQ) in MakefileMasahiro Yamada2015-07-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kbuild descends into drivers/clk/zynq/ only when CONFIG_ARCH_ZYNQ is enabled. (see drivers/clk/Makefile) $(CONFIG_ARCH_ZYNQ) in drivers/clk/zynq/Makefile always evaluates to 'y'. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | MAINTAINERS: Update Zynq git tree locationSoren Brinkmann2015-07-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The git tree for Zynq moved to Github. Update the MAINTAINERS record to reflect the change. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)Thomas Betker2015-07-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on the commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register") Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. For Zynq, this fix avoids memory inconsistencies between Gigabit Ethernet controller (GEM) and CPU when DMA_CMA is disabled. Suggested-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Fix earlyprintk in big endian modeArun Chandran2015-07-221-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | earlyprintk messages are not appearing on the terminal emulator during a big endian kernel boot. In BE mode sending full words to UART will result in unprintable characters as they are byte swapped versions of printable ones. So send only bytes. Signed-off-by: Arun Chandran <achandran@mvista.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: at91/soc: add basic support for new sama5d2 SoCNicolas Ferre2015-08-057-1/+35
| | | | | | | | | | | | | | | | | | | | Add Kconfig entries, header file changes and addition to the documentation. The early debug infrastructure is also added for easy development. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | ARM: zx: Add power domains for ZX296702Jun Nie2015-07-303-1/+204
| | | | | | | | | | | | | | | | | | Add power domains for ZX296702 to power off inactive power domains in runtime. Signed-off-by: Jun Nie <jun.nie@linaro.org> [olof: Marked zx296702_pd_driver as __initdata to avoid section mismatch] Signed-off-by: Olof Johansson <olof@lixom.net>
* | Merge tag 'socfpga_updates_for_v4.3' of ↵Olof Johansson2015-07-283-0/+40
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc SoCFPGA updates for v4.3 - Add smp.ops.cpu_kill() for kexec - Add reboot capability for Arria10 * tag 'socfpga_updates_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: add reset for the Arria 10 platform ARM: socfpga: add smp_ops.cpu_kill to make kexec/kdump available Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: socfpga: add reset for the Arria 10 platformDinh Nguyen2015-07-202-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the Arria10's reset register offset is different from the Cyclone/Arria 5, it's best to add a new DT_MACHINE_START() for the Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: use altera_a10_dt_match for the A10 machine desc
| * | ARM: socfpga: add smp_ops.cpu_kill to make kexec/kdump availableHiraku Toyooka2015-07-071-0/+13
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kexec_load syscall in ARM requires that machine-specific code has the smp_ops.cpu_kill() before loading kernel image. This patch adds the cpu_kill(), as a result, kexec reboot and kernel crash dump become available in mach-socfpga. Signed-off-by: Hiraku Toyooka <hiraku.toyooka.gu@hitachi.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348004.html Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | Merge tag 'v4.2-next-soc' of https://github.com/mbgg/linux-mediatek into ↵Olof Johansson2015-07-289-1/+682
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/soc - ARM: mediatek: Add regmap to mediatek Kconfig - soc: mediatek: Drop owner assignment from platform_driver - soc: Mediatek: Add SCPSYS power domain driver - dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit - soc: mediatek: Add infracfg misc driver support * tag 'v4.2-next-soc' of https://github.com/mbgg/linux-mediatek: ARM: mediatek: Add regmap to mediatek Kconfig soc: mediatek: Drop owner assignment from platform_driver soc: Mediatek: Add SCPSYS power domain driver dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit soc: mediatek: Add infracfg misc driver support Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: mediatek: Add regmap to mediatek KconfigMatthias Brugger2015-07-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Mediatek SoC needs the regmap/syscon infrastructure. The infrastructure is used by the clock and pinctrl driver. This patch adds MD_SYSCON to Kconfig for all Mediatek devices. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| * | soc: mediatek: Drop owner assignment from platform_driverKrzysztof Kozlowski2015-07-101-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | platform_driver does not need to set an owner because platform_driver_register() will set it. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| * | soc: Mediatek: Add SCPSYS power domain driverSascha Hauer2015-07-064-0/+513
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a power domain driver for the Mediatek SCPSYS unit. The System Control Processor System (SCPSYS) has several power management related tasks in the system. The tasks include thermal measurement, dynamic voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control. The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power domain control. For now this driver only adds power domain support, the more advanced features are not yet supported. The driver implements the generic PM domain device tree bindings, the first user will most likely be the Mediatek AFE audio driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| * | dt-bindings: soc: Add documentation for the MediaTek SCPSYS unitSascha Hauer2015-07-061-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | This adds documentation for the MediaTek SCPSYS unit found in MT8173 SoCs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| * | soc: mediatek: Add infracfg misc driver supportSascha Hauer2015-07-064-0/+127
| |/ | | | | | | | | | | | | | | | | | | | | This adds support for some miscellaneous bits of the infracfg controller. The mtk_infracfg_set/clear_bus_protection functions are necessary for the scpsys power domain driver to handle the bus protection bits which are contained in the infacfg register space. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* | MAINTAINERS: add entries for UniPhier device trees and driversMasahiro Yamada2015-07-271-0/+3
| | | | | | | | | | | | | | This clarifies the location of the files maintained by me. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | Merge tag 'pxa-for-4.3-v2' of https://github.com/rjarzmik/linux into next/socOlof Johansson2015-07-278-29/+69
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the pxa changes for v4.3 cycle. There is mostly one evolution on the dma side, to enable cooperation of the legacy pxa DMA API, and the new dmaengine API. Once all drivers using DMA are converted, the legacy DMA API should be removed. * tag 'pxa-for-4.3-v2' of https://github.com/rjarzmik/linux: ARM: pxa: Use setup_timer ARM: pxa: Use module_platform_driver ARM: pxa: transition to dmaengine phase 1 Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: pxa: Use setup_timerVaishali Thakkar2015-07-181-4/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the timer API function setup_timer instead of structure field assignments to initialize a timer. A simplified version of the Coccinelle semantic patch that performs this transformation is as follows: @change@ expression e1, e2, a; @@ -init_timer(&e1); +setup_timer(&e1, a, 0UL); ... when != a = e2 -e1.function = a; Signed-off-by: Vaishali Thakkar <vthakkar1994@gmail.com> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
| * | ARM: pxa: Use module_platform_driverVaishali Thakkar2015-07-181-14/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use module_platform_driver for drivers whose init and exit functions only register and unregister, respectively. A simplified version of the Coccinelle semantic patch that performs this transformation is as follows: @a@ identifier f, x; @@ -static f(...) { return platform_driver_register(&x); } @b depends on a@ identifier e, a.x; @@ -static e(...) { platform_driver_unregister(&x); } @c depends on a && b@ identifier a.f; declarer name module_init; @@ -module_init(f); @d depends on a && b && c@ identifier b.e, a.x; declarer name module_exit; declarer name module_platform_driver; @@ -module_exit(e); +module_platform_driver(x); Signed-off-by: Vaishali Thakkar <vthakkar1994@gmail.com> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
| * | ARM: pxa: transition to dmaengine phase 1Robert Jarzmik2015-07-186-11/+66
| |/ | | | | | | | | | | | | | | | | | | | | | | In order to slowly transition pxa to dmaengine, the legacy code will now rely on dmaengine to request a channel. This implies that PXA architecture selects DMADEVICES and PXA_DMA, which is not pretty. Yet it enables PXA drivers to be ported one by one, with part of them using dmaengine, and the other part using the legacy code. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
* | Merge tag 'omap-for-v4.3/soc-signed' of ↵Olof Johansson2015-07-2731-279/+778
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc SoC changes for omaps for v4.3 merge window: - Clean-up omap4_local_timer_init to drop deal legacy code - Provide proper IO map table for dra7 - Clean-up IOMMU layer init code as it now uses IOMMU framework - A series of changes to fix up dm814x support that's been in a broken half-merged state for quite some time - A series of PRCM and hwmod changes via Paul Walmsley <paul@pwsan.com>: - I/O wakeup support for AM43xx - register lock and unlock support to the hwmod code (needed for the RTC IP blocks on some chips) - several fixes for sparse warnings and an unnecessary null pointer test - a DRA7xx clockdomain configuration workaround, to deal with some hardware bugs * tag 'omap-for-v4.3/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: OMAP2: Add minimal dm814x hwmod support ARM: OMAP2+: Prepare dm81xx hwmod code for adding minimal dm814x support ARM: PRM: AM437x: Enable IO wakeup feature ARM: OMAP4+: PRM: Add AM437x specific data ARM: OMAP: PRM: Remove hardcoding of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 register offsets ARM: dts: AM4372: Add PRCM IRQ entry ARM: AM43xx: Add the PRM IRQ register offsets ARM: OMAP4: PRM: Remove hardcoding of PRM_IO_PMCTRL_OFFSET register ARM: OMAP2+: Add support for initializing dm814x clocks ARM: OMAP2+: Add custom prwdm_operations for 81xx to support dm814x ARM: OMAP2+: Add minimal clockdomains for dm814x ARM: OMAP2+: Fix scm compatible for dm814x ARM: OMAP2+: Fix dm814x DT_MACHINE_START ARM: OMAP2+: Remove module references from IOMMU machine layer ARM: DRA7: Provide proper IO map table ARM: OMAP2+: Clean up omap4_local_timer_init ARM: OMAP2: Delete an unnecessary check ARM: OMAP2+: sparse: add missing function declarations ARM: OMAP2+: sparse: add missing static declaration ARM: OMAP2+: hwmod: add support for lock and unlock hooks ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * \ Merge branch 'dm814x-soc' into omap-for-v4.3/socTony Lindgren2015-07-2414-213/+569
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update dm814x changes for sparse fixes to make data structures static. Conflicts: arch/arm/mach-omap2/omap_hwmod_81xx_data.c
| | * | ARM: OMAP2: Add minimal dm814x hwmod supportTony Lindgren2015-07-244-5/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's add minimal set of dm814x hwmods to have a bootable system. Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | ARM: OMAP2+: Prepare dm81xx hwmod code for adding minimal dm814x supportTony Lindgren2015-07-241-193/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's change the defines so we can share the hwmod code better between dm816x and dm814x, and let's add the dm814x specific defines. And let's rename the shared ones to start with dm81xx. No functional changes. Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | ARM: OMAP2+: Add support for initializing dm814x clocksTony Lindgren2015-07-165-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's add a minimal clocks for dm814x to get it booted. This is mostly a placeholder and relies on the PLLs being on from the bootloader. Note that the divider clocks work the same way as on dm816x and am335x. Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Tero Kristo <t-kristo@ti.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | ARM: OMAP2+: Add custom prwdm_operations for 81xx to support dm814xTony Lindgren2015-07-162-3/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Looking at the TI kernel tree I noticed that dm81xx need custom ti81xx_pwrdm_operations. Let's also change dm816x over to use them as the registers are different for dm81xx compared to others. Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | ARM: OMAP2+: Add minimal clockdomains for dm814xTony Lindgren2015-07-163-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For now, let's just add the ones shared with dm816x. The dm814x specific ones can be added as they are tested. Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | ARM: OMAP2+: Fix scm compatible for dm814xTony Lindgren2015-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix scm compatible for dm814x. Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | ARM: OMAP2+: Fix dm814x DT_MACHINE_STARTTony Lindgren2015-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix dm814x DT_MACHINE_START. Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | Merge tag 'for-v4.3/omap-hwmod-prcm-a' of ↵Tony Lindgren2015-07-2416-50/+92
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.3/soc ARM: OMAP2+: PRCM and hwmod changes for v4.3 This series adds: - I/O wakeup support for AM43xx - register lock and unlock support to the hwmod code (needed for the RTC IP blocks on some chips) - several fixes for sparse warnings and an unnecessary null pointer test - a DRA7xx clockdomain configuration workaround, to deal with some hardware bugs Basic build, boot, and PM tests are here: http://www.pwsan.com/omap/testlogs/hwmod-prcm-for-v4.3/20150723080012/ Since I do not have an AM43xx or DRA7xx device, I can't test on those platforms.
| | * \ \ Merge branch 'prcm-a-for-v4.3' into hwmod-prcm-for-v4.3Paul Walmsley2015-07-235-24/+48
| | |\ \ \
| | | * | | ARM: PRM: AM437x: Enable IO wakeup featureKeerthy2015-07-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable IO wakeup feature. This enables am437x pads to generate daisy chained wake ups(eventually generates aprcm Interrupt) especially when in low power modes. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: OMAP4+: PRM: Add AM437x specific dataKeerthy2015-07-231-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register offsets for some of the PRM Registers are different hence populating the differing fields. This is needed to support IO wake up feature for am437x family. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: OMAP: PRM: Remove hardcoding of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 ↵Keerthy2015-07-231-18/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register offsets The register offsets of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 are hardcoded. This makes it difficult to reuse the code for SoCs like AM437x that have a single instance of IRQENABLE_MPU and IRQSTATUS_MPU registers. Hence handling the case using offset of 4 to accommodate single set of IRQ* registers generically. Signed-off-by: Keerthy <j-keerthy@ti.com> [paul@pwsan.com: fixed whitespace alignment problems reported by checkpatch.pl] Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: dts: AM4372: Add PRCM IRQ entryKeerthy2015-07-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PRCM IRQ entry. This is needed for I/O wakeup support. Signed-off-by: Keerthy <j-keerthy@ti.com> [paul@pwsan.com: added I/O wakeup note in commit description] Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: AM43xx: Add the PRM IRQ register offsetsKeerthy2015-07-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PRM IRQ register offsets. This is needed to support PRM I/O wakeup on AM43xx. Signed-off-by: Keerthy <j-keerthy@ti.com> [paul@pwsan.com: improved patch description, moved the PRM_IO_PMCTRL macro out of the CM section] Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: OMAP4: PRM: Remove hardcoding of PRM_IO_PMCTRL_OFFSET registerKeerthy2015-07-232-5/+8
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PRM_IO_PMCTRL_OFFSET need not be same for all SOCs hence remove hardcoding and use the value provided by the omap_prcm_irq_setup structure. This is done to support IO wakeup on am437x series. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-10 15:55:08 +0200