summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* vxlan: improve validation of address family configurationMatthias Schiffer2017-06-201-11/+28
| | | | | | | | | | | Address families of source and destination addresses must match, and changelink operations can't change the address family. In addition, always use the VXLAN_F_IPV6 to check if a VXLAN device uses IPv4 or IPv6. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
* vxlan: get rid of redundant vxlan_dev.flagsMatthias Schiffer2017-06-203-42/+39Star
| | | | | | | | There is no good reason to keep the flags twice in vxlan_dev and vxlan_config. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
* vxlan: refactor verification and application of configurationMatthias Schiffer2017-06-201-97/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vxlan_dev_configure function was mixing validation and application of the vxlan configuration; this could easily lead to bugs with the changelink operation, as it was hard to see if the function wcould return an error after parts of the configuration had already been applied. This commit splits validation and application out of vxlan_dev_configure as separate functions to make it clearer where error returns are allowed and where the vxlan_dev or net_device may be configured. Log messages in these functions are removed, as it is generally unexpected to find error output for netlink requests in the kernel log. Userspace should be able to handle errors based on the error codes returned via netlink just fine. In addition, some validation and initialization is moved to vxlan_validate and vxlan_setup respectively to improve grouping of similar settings. Finally, this also fixes two actual bugs: * if set, conf->mtu would overwrite dev->mtu in each changelink operation, reverting other changes of dev->mtu * the "if (!conf->dst_port)" branch would never be run, as conf->dst_port was set in vxlan_setup before. This caused VXLAN-GPE to use the same default port as other VXLAN sockets instead of the intended IANA-assigned 4790. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'net-more-skb_put-work'David S. Miller2017-06-2065-218/+166Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | yuan linyu says: ==================== net: more skb_put_[data:zero] related work yuan linyu (3): net: introduce __skb_put_[zero, data, u8] net: replace more place to skb_put_[data:zero] net: manual clean code which call skb_put_[data:zero] ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: manual clean code which call skb_put_[data:zero]yuan linyu2017-06-2039-135/+93Star
| | | | | | | | | | Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: replace more place to skb_put_[data:zero]yuan linyu2017-06-207-16/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spatch file, @@ expression skb, len, data; type t; @@ -memcpy((t *)skb_put(skb, len), data, len); +skb_put_data(skb, data, len); @@ identifier p; expression skb, len, data; type t; @@ -p = (t *)memset(skb_put(skb, len), data, len); +p = skb_put_zero(skb, len); @@ expression skb, len, data; type t; @@ -memcpy((t *)__skb_put(skb, len), data, len); +__skb_put_data(skb, data, len); @@ identifier p; expression skb, len, data; type t; @@ -p = (t *)memset(__skb_put(skb, len), data, len); +p = __skb_put_zero(skb, len); Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: introduce __skb_put_[zero, data, u8]yuan linyu2017-06-2019-67/+64Star
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | follow Johannes Berg, semantic patch file as below, @@ identifier p, p2; expression len; expression skb; type t, t2; @@ ( -p = __skb_put(skb, len); +p = __skb_put_zero(skb, len); | -p = (t)__skb_put(skb, len); +p = __skb_put_zero(skb, len); ) ... when != p ( p2 = (t2)p; -memset(p2, 0, len); | -memset(p, 0, len); ) @@ identifier p; expression len; expression skb; type t; @@ ( -t p = __skb_put(skb, len); +t p = __skb_put_zero(skb, len); ) ... when != p ( -memset(p, 0, len); ) @@ type t, t2; identifier p, p2; expression skb; @@ t *p; ... ( -p = __skb_put(skb, sizeof(t)); +p = __skb_put_zero(skb, sizeof(t)); | -p = (t *)__skb_put(skb, sizeof(t)); +p = __skb_put_zero(skb, sizeof(t)); ) ... when != p ( p2 = (t2)p; -memset(p2, 0, sizeof(*p)); | -memset(p, 0, sizeof(*p)); ) @@ expression skb, len; @@ -memset(__skb_put(skb, len), 0, len); +__skb_put_zero(skb, len); @@ expression skb, len, data; @@ -memcpy(__skb_put(skb, len), data, len); +__skb_put_data(skb, data, len); @@ expression SKB, C, S; typedef u8; identifier fn = {__skb_put}; fresh identifier fn2 = fn ## "_u8"; @@ - *(u8 *)fn(SKB, S) = C; + fn2(SKB, C); Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: better IEEE Prio Mapping Table descriptionVivien Didelot2017-06-202-7/+8
| | | | | | | | | Kill the remaining shift macro in favor of calculating at compile time its value from the more descriptive mask, which gives us a better representation of the register layout. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'net-dsa-Global-2-cosmetics'David S. Miller2017-06-204-299/+479
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vivien Didelot says: ==================== net: dsa: Global 2 cosmetics Similarly to what has been done for the Port and Global 1 registers, this patch series prefixes and documents the macros of Global 2. It brings no functional changes except for 1/10 which fixes the IRL init for 88E6390 family. Changes in v2: make *_g2_irl_init_all static inline without NET_DSA_MV88E6XXX_GLOBAL2 and compile test with and without the symbol. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: prefix Global 2 remaining macrosVivien Didelot2017-06-202-35/+57
| | | | | | | | | | | | | | Prefix and document the remaining Global 2 registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: prefix Global 2 Watchdog macrosVivien Didelot2017-06-202-43/+52
| | | | | | | | | | | | | | | | | | | | The Marvell 88E6352 family has a Global 2 register dedicated to the watchdog setup. But the 88E6390 turned it into an indirect table. Prefix and document that. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: prefix Global 2 Switch MAC macrosVivien Didelot2017-06-202-2/+7
| | | | | | | | | | | | | | Prefix and document the Global 2 Switch MAC registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: prefix Global 2 EEPROM macrosVivien Didelot2017-06-202-25/+38
| | | | | | | | | | | | | | Prefix and document the Global 2 EEPROM registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: prefix Global 2 PVT macrosVivien Didelot2017-06-202-12/+21
| | | | | | | | | | | | | | Prefix and document the Global 2 Cross-chip Port VLAN registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: prefix Global 2 MGMT macrosVivien Didelot2017-06-202-13/+21
| | | | | | | | | | | | | | Prefix and document the Global 2 MGMT registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: prefix Global 2 Device Mapping macrosVivien Didelot2017-06-202-5/+7
| | | | | | | | | | | | | | Prefix and document the Global 2 Device Mapping macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: prefix Global 2 Trunk macrosVivien Didelot2017-06-202-14/+17
| | | | | | | | | | | | | | | | Prefix and document the Global 2 Trunk registers macros. At the same time, fix the hask -> hash typo and use the mv88e6xxx_port_mask helper. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: clarify SMI PHY functionsVivien Didelot2017-06-202-100/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell chips with an SMI PHY access in Global 2 registers handle both Clause 22 and Clause 45 of IEEE 802.3. The 88E6390 family has addition bits to target the internal or external PHYs connected to the device, and a Setup function in addition to the default (register) Access function. Prefix the SMI PHY Command and Data registers macros, implement clear helpers for Clause 22 and 44 Access functions, rename variable to match the SMI and switch vocabulary (device and register addresses for Clause 22 and port and device class for Clause 45.) Finally do not use complex macros but simple 16-bit mask to document the registers organization. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: mv88e6xxx: add irl_init_all opVivien Didelot2017-06-204-50/+116
|/ | | | | | | | | | | | | | | | | Some Marvell chips have an Ingress Rate Limit unit. But the command values slightly differs between models: 88E6352 use 3-bit for operations while 88E6390 use different 2-bit operations. This commit kills the IRL flags in favor of a new operation implementing the "Init all resources to the initial state" operation. This fixes the operation of 88E6390 family where 0x1000 means Read the selected resource 0, register 0 on port 16, instead of init all. A mv88e6xxx_irl_setup helper is added to wrap the operation call. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'net-next-stmmac-dwmac-sun8i-add-support-for-V3s'David S. Miller2017-06-204-2/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Icenowy Zheng says: ==================== net-next: stmmac: dwmac-sun8i: add support for V3s Allwinner V3s features an EMAC like the on in H3, but without external MII interfaces, so being not able really to use RMII/RGMII. And it has a different default value of syscon (0x38000 instead of 0x58000 on H3), which shows a problem that the EMAC clock freq should be 24MHz. (Both H3 and V3s SoCs doesn't have extra xtal input for EPHY, and the main xtal is 24MHz. The default value of H3 is set to 24MHz, but the V3s default value is set to 25MHz). First two patches are device tree binding patches, the third forces the frequency to 24MHz and the fourth really add the V3s support. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
| * net-next: stmmac: dwmac-sun8i: add support for V3s EMACIcenowy Zheng2017-06-202-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner V3s SoC has an Ethernet MAC and an internal PHY like the ones in H3 SoC, however the MAC has no external *MII interfaces available at GPIOs, thus only MII connection to internal PHY is supported. Add this variant of EMAC to dwmac-sun8i driver. The default value of the syscon EMAC-related register seems to have changed from H3, but it seems to be a harmless change. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net-next: stmmac: dwmac-sun8i: force EPHY clock freq to 24MHzIcenowy Zheng2017-06-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EPHY control part of the EMAC syscon register has a bit called CLK_SEL. On the datasheet it says that if it's 0 the EPHY clock is 25MHz and if it's 1 the clock is 24MHz. However, according to the datasheets, no Allwinner SoC with EPHY has any extra xtal input pins for the EPHY, and the system xtal is 24MHz. That means the EPHY is not possible to get a 25MHz xtal input, and thus the frequency can only be 24MHz. It doesn't matter on H3 as the default value of H3 is 24MHz, however on V3s the default value is wrongly set to 25MHz, which prevented the EPHY from working properly. Force the EPHY clock frequency to 24MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: David S. Miller <davem@davemloft.net>
| * dt-bindings: syscon: Add DT bindings documentation for Allwinner V3s sysconIcenowy Zheng2017-06-201-0/+1
| | | | | | | | | | | | | | | | | | Allwinner V3s SoC has a syscon like the one in H3. Add its compatible string. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: David S. Miller <davem@davemloft.net>
| * dt-bindings: net-next: Add DT bindings documentation for Allwinner V3s EMACIcenowy Zheng2017-06-201-2/+8
|/ | | | | | | | | | | Allwinner V3s SoC has a Ethernet MAC like the one in Allwinner H3, but have no external MII capability. That means that it can only use the EPHY and cannot do Gbps transmission. Add binding for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'net-Introduction-of-the-tc-tests'David S. Miller2017-06-2010-0/+1863
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lucas Bates says: ==================== net: Introduction of the tc tests Apologies for sending this as one big patch. I've been sitting on this a little too long, but it's ready and I wanted to get it out. There are a limited number of tests to start - I plan to add more on a regular basis. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
| * selftests: Introduce tc testsuiteLucas Bates2017-06-2010-0/+1863
|/ | | | | | | | | | | | | | | | | | | | | | | Add the beginnings of a testsuite for tc functionality in the kernel. These are a series of unit tests that use the tc executable and verify the success of those commands by checking both the exit codes and the output from tc's 'show' operation. To run the tests: # cd tools/testing/selftests/tc-testing # sudo ./tdc.py You can specify the tc executable to use with the -p argument on the command line or editing the 'TC' variable in tdc_config.py. Refer to the README for full details on how to run. The initial complement of test cases are limited mostly to tc actions. Test cases are most welcome; see the creating-testcases subdirectory for help in creating them. Signed-off-by: Lucas Bates <lucasb@mojatatu.com> Signed-off-by: Jamal Hadi Salim <jhs@mojatatu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'qed-RDMA-and-infrastructure-for-iWARP'David S. Miller2017-06-2022-202/+353
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Yuval Mintz says: ==================== qed*: RDMA and infrastructure for iWARP This series focuses on RDMA in general with emphasis on required changes toward adding iWARP support. The vast majority of the changes introduced are in qed/qede, with a couple of small changes to qedr [mentioned below]. The infrastructure changes: - Patch #1 adds the ability to pass PBL memory externally for a newly created chain. - Patches #4, #5 rename qede_roce.[ch] into qede_rdma.[ch] + change prefixes from _roce_ to _rdma_, as the API between qede and qedr is agnostic to the variant of the RDMA protocol used. These patches also touch qedr [basically to align it with the renaming, nothing more]. - Patch #7 replaces the current SPQ async mechanism into serving registered callbacks [before adding iWARP which would add another client in need of this sort of functionallity]. The non-infrastrucutre changes: - Patches #2, #3 contain DCB-related changes to better align RDMA with configured DCB. - Patch #6 contains a minor [mostly theoretical fix] to release flow. Changes from previous versions ------------------------------ - V4: This is actually a repost of V3 due to some confusion regarding the sent cover-letter - V3: Add commit log message in #4 indicating change in header inclusion - V2: Add several inclusion into qede_rdma.h to have proper declarations of all variable types used in it ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
| * qed: SPQ async callback registrationMichal Kalderon2017-06-207-55/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whenever firmware indicates that there's an async indication it needs to handle, there's a switch-case where the right functionality is called based on function's personality and information. Before iWARP is added [as yet another client], switch over the SPQ into a callback-registered mechanism, allowing registration of the relevant event-processing logic based on the function's personality. This allows us to tidy the code by removing protocol-specifics from a common file. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * qed: Wait for resources before FUNC_CLOSEMichal Kalderon2017-06-201-15/+20
| | | | | | | | | | | | | | | | | | Driver needs to wait for all resources to return from FW before it can send the FUNC_CLOSE ramrod. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * qed*: Set rdma generic functions prefixMichal Kalderon2017-06-205-100/+101
| | | | | | | | | | | | | | | | | | Rename the functions common to both iWARP and RoCE to have a prefix of _rdma_ instead of _roce_. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * qed*: qede_roce.[ch] -> qede_rdma.[ch]Michal Kalderon2017-06-207-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Once we have iWARP support, the qede portion of the qedr<->qede would serve all the RDMA protocols - so rename the file to be appropriate to its function. While we're at it, we're also moving a couple of inclusions to it into .h files and adding includes to make sure it contains all type definitions it requires. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * qed: Disable RoCE dpm when DCBx change occursMintz, Yuval2017-06-203-0/+49
| | | | | | | | | | | | | | | | If DCBx update occurs while QPs are open, stop sending edpms until all QPs are closed. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * qed: RoCE EDPM to honor PFCMintz, Yuval2017-06-202-0/+22
| | | | | | | | | | | | | | | | Configure device according to DCBx results so that EDPMs made by RoCE would honor flow-control. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * qed: Chain support for external PBLMintz, Yuval2017-06-2010-28/+56
|/ | | | | | | | iWARP would require the chains to allocate/free their PBL memory independently, so add the infrastructure to provide it externally. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* tcp: md5: add TCP_MD5SIG_EXT socket option to set a key address prefixIvan Delalande2017-06-195-15/+41
| | | | | | | | | | | | | Replace first padding in the tcp_md5sig structure with a new flag field and address prefix length so it can be specified when configuring a new key for TCP MD5 signature. The tcpm_flags field will only be used if the socket option is TCP_MD5SIG_EXT to avoid breaking existing programs, and tcpm_prefixlen only when the TCP_MD5SIG_FLAG_PREFIX flag is set. Signed-off-by: Bob Gilligan <gilligan@arista.com> Signed-off-by: Eric Mowat <mowat@arista.com> Signed-off-by: Ivan Delalande <colona@arista.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* tcp: md5: add an address prefix for key lookupIvan Delalande2017-06-193-16/+70
| | | | | | | | | | | This allows the keys used for TCP MD5 signature to be used for whole range of addresses, specified with a prefix length, instead of only one address as it currently is. Signed-off-by: Bob Gilligan <gilligan@arista.com> Signed-off-by: Eric Mowat <mowat@arista.com> Signed-off-by: Ivan Delalande <colona@arista.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb4: notify uP to route ctrlq compl to rdma rspqRaju Rangoju2017-06-191-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the module initialisation there is a possible race (basically race between uld and lld) where neither the uld nor lld notifies the uP about where to route the ctrl queue completions. LLD skips notifying uP as the rdma queues were not created by then (will leave it to ULD to notify the uP). As the ULD comes up, it also skips notifying the uP as the flag FULL_INIT_DONE is not set yet (ULD assumes that the interface is not up yet). Consequently, this race between uld and lld leaves uP unnotified about where to send the ctrl queue completions to, leading to iwarp RI_RES WR failure. Here is the race: CPU 0 CPU1 - allocates nic rx queus - t4_sge_alloc_ctrl_txq() (if rdma rsp queues exists, tell uP to route ctrl queue compl to rdma rspq) - acquires the mutex_lock - allocates rdma response queues - if FULL_INIT_DONE set, tell uP to route ctrl queue compl to rdma rspq - relinquishes mutex_lock - acquires the mutex_lock - enable_rx() - set FULL_INIT_DONE - relinquishes mutex_lock This patch fixes the above issue. Fixes: e7519f9926f1('cxgb4: avoid enabling napi twice to the same queue') Signed-off-by: Raju Rangoju <rajur@chelsio.com> Acked-by: Steve Wise <swise@opengridcomputing.com> CC: Stable <stable@vger.kernel.org> # 4.9+ Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb4: add new T6 pci device id'sGanesh Goudar2017-06-191-0/+3
| | | | | | | Add 0x6082, 0x6083 and 0x6084 T6 device id's Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* nfp: add VLAN filtering supportPablo Cascón2017-06-192-1/+100
| | | | | | | | | Add general use per-vNIC mailbox area and use it for VLAN filtering support. Initially proto is hardcoded to 802.1q. Signed-off-by: Pablo Cascón <pablo.cascon@netronome.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb4: fix a NULL dereferenceGanesh Goudar2017-06-191-1/+4
| | | | | | | | | Avoid NULL dereference in setup_sge_queues() when the adapter is in non offload mode. Fixes: 0fbc81b3ad51 ('chcr/cxgb4i/cxgbit/RDMA/cxgb4: Allocate resources dynamically for all cxgb4 ULD's') Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* liquidio: replace info-pointer mode with buffer-pointer-only modePrasad Kanneganti2017-06-1911-109/+37Star
| | | | | | | | | | | | | | | | | | | | | Each Octeon output ring can DMA packets to host memory in two modes: info- pointer mode and buffer-pointer-only mode. In info-pointer mode, Octeon takes two buffer pointers for each packet and places the length of the packet along with specified number of bytes from the beginning of the packet into one buffer and the rest of the packet in a separate buffer. In buffer-pointer-only mode, Octeon takes single buffer pointer and places the length of the packet at the beginning of the buffer followed by the packet data. This patch switches all Octeon output rings from info-pointer mode to buffer-pointer-only mode. This results in fewer DMA setups and cache line snoops. Signed-off-by: Prasad Kanneganti <pkanneganti@cavium.com> Signed-off-by: Derek Chickles <derek.chickles@cavium.com> Signed-off-by: Satanand Burla <satananda.burla@cavium.com> Signed-off-by: Felix Manlunas <felix.manlunas@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pptp: Remove unused variable in pptp_release()Christos Gkekas2017-06-191-2/+0Star
| | | | | | | | Variable opt in pptp_release() is set but never used, thus needs to be removed. Signed-off-by: Christos Gkekas <chris.gekas@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* liquidio: implement vlan filter enable and disablePrasad Kanneganti2017-06-193-10/+32
| | | | | | | | | | | | Add implementation to support ethtool -K ethX rx-vlan-filter on/off. Rename OCTNET_CMD_ENABLE_VLAN_FILTER command to OCTNET_CMD_VLAN_FILTER_CTL and add OCTNET_CMD_VLAN_FILTER_ENABLE and OCTNET_CMD_VLAN_FILTER_DISABLE parameters so that it can be used to enable or disable the filter. Signed-off-by: Prasad Kanneganti <prasad.kanneganti@cavium.com> Signed-off-by: Derek Chickles <derek.chickles@cavium.com> Signed-off-by: Felix Manlunas <felix.manlunas@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: Fix legacy probingFlorian Fainelli2017-06-181-11/+8Star
| | | | | | | | | | | | | | | | | After commit 6d3c8c0dd88a ("net: dsa: Remove master_netdev and use dst->cpu_dp->netdev") and a29342e73911 ("net: dsa: Associate slave network device with CPU port") we would be seeing NULL pointer dereferences when accessing dst->cpu_dp->netdev too early. In the legacy code, we actually know early in advance the master network device, so pass it down to the relevant functions. Fixes: 6d3c8c0dd88a ("net: dsa: Remove master_netdev and use dst->cpu_dp->netdev") Fixes: a29342e73911 ("net: dsa: Associate slave network device with CPU port") Reported-by: Jason Cobham <jcobham@questertangent.com> Tested-by: Jason Cobham <jcobham@questertangent.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* tls: update KconfigDave Watson2017-06-181-2/+5
| | | | | | | | | | | | | | | | | | | | | | Missing crypto deps for some platforms. Default to n for new module. config: m68k-amcore_defconfig (attached as .config) compiler: m68k-linux-gcc (GCC) 4.9.0 make.cross ARCH=m68k All errors (new ones prefixed by >>): net/built-in.o: In function `tls_set_sw_offload': >> (.text+0x732f8): undefined reference to `crypto_alloc_aead' net/built-in.o: In function `tls_set_sw_offload': >> (.text+0x7333c): undefined reference to `crypto_aead_setkey' net/built-in.o: In function `tls_set_sw_offload': >> (.text+0x73354): undefined reference to `crypto_aead_setauthsize' Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Dave Watson <davejwatson@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'net-remove-dst-garbage-collector-logic'David S. Miller2017-06-1817-466/+218Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wei Wang says: ==================== remove dst garbage collector logic The current mechanism of dst release is a bit complicated. It is because the users of dst get divided into 2 situations: 1. Most users take the reference count when using a dst and release the reference count when done. 2. Exceptional users like IPv4/IPv6/decnet/xfrm routing code do not take reference count when referencing to a dst due to some histotic reasons. Due to those exceptional use cases in 2, reference count being 0 is not an adequate evidence to indicate that no user is using this dst. So users in 1 can't free the dst simply based on reference count being 0 because users in 2 might still hold reference to it. Instead, a dst garbage list is needed to hold the dst entries that already get removed by the users in 2 but are still held by users in 1. And a periodic garbage collector task is run to check all the dst entries in the list to see if the users in 1 have released the reference to those dst entries. If so, the dst is now ready to be freed. This logic introduces unnecessary complications in the dst code which makes it hard to understand and to debug. In order to get rid of the whole dst garbage collector (gc) and make the dst code more unified and simplified, we can make the users in 2 also take reference count on the dst and release it properly when done. This way, dst can be safely freed once the refcount drops to 0 and no gc thread is needed anymore. This patch series' target is to completely get rid of dst gc logic and free dst based on reference count only. Patch 1-3 are preparation patches to do some cleanup/improvement on the existing code to make later work easier. Patch 4-21 are real implementations. In these patches, a temporary flag DST_NOGC is used to help transition those exceptional users one by one. Once every component is transitioned, this temporary flag is removed. By the end of this patch series, all dst are refcounted when being used and released when done. And dst will be freed when its refcount drops to 0. No dst gc task is running anymore. Note: This patch series depends on the decnet fix that was sent right before: "decnet: always not take dst->__refcnt when inserting dst into hash table" v2: add curly braces in udp_v4/6_early_demux() in patch 02 add EXPORT_SYMBOL() for dst_dev_put() in patch 05 ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: add debug atomic_inc_not_zero() in dst_hold()Wei Wang2017-06-181-1/+1
| | | | | | | | | | | | | | | | | | | | This patch is meant to add a debug warning on the situation where dst is being held during its destroy phase. This could potentially cause double free issue on the dst. Signed-off-by: Wei Wang <weiwan@google.com> Acked-by: Martin KaFai Lau <kafai@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: reorder all the dst flagsWei Wang2017-06-181-5/+5
| | | | | | | | | | | | | | | | | | | | | | As some dst flags are removed, reorder the dst flags to fill in the blanks. Note: these flags are not exposed into user space. So it is safe to reorder. Signed-off-by: Wei Wang <weiwan@google.com> Acked-by: Martin KaFai Lau <kafai@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: remove DST_NOCACHE flagWei Wang2017-06-188-25/+17Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DST_NOCACHE flag check has been removed from dst_release() and dst_hold_safe() in a previous patch because all the dst are now ref counted properly and can be released based on refcnt only. Looking at the rest of the DST_NOCACHE use, all of them can now be removed or replaced with other checks. So this patch gets rid of all the DST_NOCACHE usage and remove this flag completely. Signed-off-by: Wei Wang <weiwan@google.com> Acked-by: Martin KaFai Lau <kafai@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: remove DST_NOGC flagWei Wang2017-06-186-19/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that all the components have been changed to release dst based on refcnt only and not depend on dst gc anymore, we can remove the temporary flag DST_NOGC. Note that we also need to remove the DST_NOCACHE check in dst_release() and dst_hold_safe() because now all the dst are released based on refcnt and behaves as DST_NOCACHE. Signed-off-by: Wei Wang <weiwan@google.com> Acked-by: Martin KaFai Lau <kafai@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-11 20:53:38 +0200