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* ARM: ep93xx: simone: support for SPI-based MMC/SD cardsMika Westerberg2015-06-111-1/+134
| | | | | | | | | | | This includes setting up EGPIOs 0 and 9 for card detection and chip select respectively. This patch is needed to mount a root filesystem on the SPI-based MMC card reader found on the Sim.One. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
* Merge tag 'hi6220-soc-for-4.2' of git://github.com/hisilicon/linux-hisi into ↵Kevin Hilman2015-06-112-0/+6
|\ | | | | | | | | | | | | | | | | | | | | next/soc ARM64: Hisilicon ARM64 SoC Updates for V4.2 - Added Hisilicon ARM64 SoC family support in Kconfig and defconfig * tag 'hi6220-soc-for-4.2' of git://github.com/hisilicon/linux-hisi: arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig
| * arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfigBintian Wang2015-06-052-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces ARCH_HISI to enable Hisilicon SoC family in Kconfig and defconfig. Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Wei Xu <xuwei5@hisilicon.com> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Tyler Baker <tyler.baker@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
* | MAINTAINERS: update Shawn's email to use kernel.org oneShawn Guo2015-06-111-2/+2
| | | | | | | | | | | | | | | | Update my mailbox to use kernel.org one for handling kernel community maintenance traffic. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
* | Merge tag 'imx-soc-4.2' of ↵Kevin Hilman2015-06-1159-561/+2593
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc The i.MX SoC updates for 4.2: - Add new SoC i.MX7D support, which integrates two Cortex-A7 and one Cortex-M4 cores. - Support suspend from IRAM on i.MX53, so that DDR pins can be set to high impedance for more power saving during suspend. - Move i.MX clock drivers from arch/arm/mach-imx to drivers/clk/imx. - Move i.MX GPT timer driver from arch/arm/mach-imx into drivers/clocksource. - A couple of clock driver update for VF610 and i.MX6Q. - A few random code correction and improvement. * tag 'imx-soc-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits) ARM: imx: imx7d requires anatop clocksource: timer-imx-gpt: remove include of <asm/mach/time.h> ARM: imx: move timer driver into drivers/clocksource ARM: imx: remove platform headers from timer driver ARM: imx: provide gpt device specific irq functions ARM: imx: get rid of variable timer_base ARM: imx: define gpt register offset per device type ARM: imx: move clock event variables into imx_timer ARM: imx: set up .set_next_event hook via imx_gpt_data ARM: imx: setup tctl register in device specific function ARM: imx: initialize gpt device type for DT boot ARM: imx: define an enum for gpt timer device type ARM: imx: move timer resources into a structure ARM: imx: use relaxed IO accessor in timer driver ARM: imx: make imx51/3 suspend optional ARM: clk-imx6q: refine sata's parent ARM: imx: clk-v610: Add clock for I2C2 and I2C3 ARM: mach-imx: iomux-imx31: Use DECLARE_BITMAP ARM: imx: add imx7d clk tree support ARM: clk: imx: update pllv3 to support imx7 ... Conflicts: arch/arm/mach-imx/Kconfig
| * | ARM: imx: imx7d requires anatopArnd Bergmann2015-06-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like i.MX6, the i.MX7 code calls into the anatop driver, which fails if that is disabled: arch/arm/mach-imx/built-in.o: In function `imx7d_init_machine': arch/arm/mach-imx/mach-imx7d.c:24: undefined reference to `imx_anatop_init' arch/arm/mach-imx/built-in.o: In function `imx7d_init_irq': arch/arm/mach-imx/mach-imx7d.c:29: undefined reference to `imx_init_revision_from_anatop' This patch ensures that for an imx7-only build, we still get anatop built-in, matching what we do for imx6. We also need to select HAVE_IMX_MMDC, as that is needed by the anatop code. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | clocksource: timer-imx-gpt: remove include of <asm/mach/time.h>Shawn Guo2015-06-031-2/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | The include of <asm/mach/time.h> is not needed at all, and causes build error in some cases. Remove it. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * | ARM: imx: move timer driver into drivers/clocksourceShawn Guo2015-06-035-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | After the cleanup on imx timer driver, now it's ready to be moved into drivers/clocksource/. Let's do it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * | ARM: imx: remove platform headers from timer driverShawn Guo2015-06-031-6/+0Star
| | | | | | | | | | | | | | | | | | | | | With the cleanup done before, the platform specific headers now can be removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: provide gpt device specific irq functionsShawn Guo2015-06-031-26/+54
| | | | | | | | | | | | | | | | | | | | | | | | It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: get rid of variable timer_baseShawn Guo2015-06-031-29/+26Star
| | | | | | | | | | | | | | | | | | | | | | | | We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: define gpt register offset per device typeShawn Guo2015-06-031-11/+20
| | | | | | | | | | | | | | | | | | | | | | | | It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: move clock event variables into imx_timerShawn Guo2015-06-031-31/+33
| | | | | | | | | | | | | | | | | | | | | | | | Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: set up .set_next_event hook via imx_gpt_dataShawn Guo2015-06-031-3/+7
| | | | | | | | | | | | | | | | | | | | | Set up .set_next_event hook via imx_gpt_data, so that we can save the use of timer_is_v2(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: setup tctl register in device specific functionShawn Guo2015-06-031-20/+78
| | | | | | | | | | | | | | | | | | | | | It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: initialize gpt device type for DT bootShawn Guo2015-06-031-9/+46
| | | | | | | | | | | | | | | | | | | | | Use different initialization function in CLOCKSOURCE_OF_DECLARE() to initialize gpt device type for DT boot. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: define an enum for gpt timer device typeShawn Guo2015-06-038-13/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: move timer resources into a structureShawn Guo2015-06-031-35/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: use relaxed IO accessor in timer driverShawn Guo2015-06-031-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed which is endian-safe, as a step of moving the driver code into folder drivers/clocksource. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: make imx51/3 suspend optionalArnd Bergmann2015-06-031-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent change to the imx53 power management caused a build regression when CONFIG_SOC_IMX53 is disabled: mach-imx/built-in.o:(.init.rodata+0x60): undefined reference to `imx53_suspend' mach-imx/built-in.o:(.init.rodata+0x64): undefined reference to `imx53_suspend_sz' This avoids the problem by compiling the code in question conditionally on the presence of CONFIG_SOC_IMX53. For consistency, I'm also changing the same thing for CONFIG_SOC_IMX51. An additional benefit of this approach is reduced code size for kernels that only include support for one of the two SoCs. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 1579c7b9fe01 ("ARM: imx53: Set DDR pins to high impedance when in suspend to RAM.") Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: clk-imx6q: refine sata's parentSébastien Szymanski2015-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | According to IMX6D/Q RM, table 18-3, sata clock's parent is ahb, not ipg. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: clk-v610: Add clock for I2C2 and I2C3Mirza Krak2015-06-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add support for clock gating of I2C2 and I2C3. We use I2C2 in a (not yet mainlined) device tree. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mach-imx: iomux-imx31: Use DECLARE_BITMAPJoe Perches2015-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use the generic mechanism to declare a bitmap instead of unsigned long. Signed-off-by: Joe Perches <joe@perches.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: add imx7d clk tree supportFrank Li2015-06-032-0/+861
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX7D clk tree support. Enable all clock to bring up imx7. Clock framework need be modified a little since imx7d change clock design. otherwise system will halt and block the other part upstream. All clock refine need wait for Dong Aisheng's patch clk: support clocks which requires parent clock on during operation Or other solution ready. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: clk: imx: update pllv3 to support imx7Frank Li2015-06-032-1/+9
| | | | | | | | | | | | | | | | | | | | | Add type IMX_PLLV3_ENET_IMX7 Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: clk-vf610: enable debug access port by defaultStefan Agner2015-06-032-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled DAP (debug access port) by default. This enables the hw- breakpoint framework to make use of the breakpoints and watchpoints supported by hardware. [ 0.215805] hw-breakpoint: found 2 (+1 reserved) breakpoint and 1 watchpoint registers. [ 0.224624] hw-breakpoint: maximum watchpoint size is 4 bytes. Without this clock, the hw-breakpoint driver claims an undefined instruction during initialization: [ 0.227380] hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 [ 0.227519] hw-breakpoint: CPU 0 failed to disable vector catch Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx53: Set DDR pins to high impedance when in suspend to RAM.Martin Fuzzey2015-06-034-1/+333
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to save power the DDR pins should be put into high impedance when in suspend to RAM. This requires manually requesting self refresh (rather than using the automatic mode implemented by the CCM / ESDCTL), followed by reconfiguring the IOMUXC. Of course the code to do this cannot itself run from DDR so the code is copied to and executed from internal memory. In my tests using a custom i.MX53 board with LPDDR2 RAM this reduced the suspend power consumption from 200mW to 60mW. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: add msl support for imx7dAnson Huang2015-06-036-2/+65
| | | | | | | | | | | | | | | | | | | | | | | | Add i.MX7D MSL support. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx7d: add low level debug uart supportAnson Huang2015-06-032-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add low level uart debug support for imx7d Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: mmdc: Include "common.h" header fileFabio Estevam2015-06-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Include the "common.h" header file to fix the following sparse warning: arch/arm/mach-imx/mmdc.c:66:5: warning: symbol 'imx_mmdc_get_ddr_type' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | clk: imx: clk-cpu: Include "clk.h" header fileFabio Estevam2015-06-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Include the "clk.h" header file to fix the following sparse warning: drivers/clk/imx/clk-cpu.c:77:12: warning: symbol 'imx_clk_cpu' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: Correct the comments in time.cShenwei Wang2015-06-031-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The comments were corrected as the following to reflect the real situation of Freescale MXC timer IP block. There are totally 4 version of the timer on Freescale i.MX SoCs. Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: Remove the duplicated function declarationShenwei Wang2015-06-031-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | Removed the duplicated function declaration of mxc_timer_init which was already declared in drivers/clk/imx/clk.h. Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: Constify irq_domain_opsKrzysztof Kozlowski2015-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: using unsigned variable for do_divAnson Huang2015-06-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definition of do_div uses unsigned long long variable as its first parameter, better to pass a u64 variable as first parameter when calling do_div function. Signed-off-by: Anson Huang <b20788@freescale.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6: initialize CCM_CLPCR_LPM into RUN mode earlierShawn Guo2015-06-035-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function") moves imx6_set_lpm() from clock init function into imx6_pm_common_init(). This causes a hang when cpuidle support is enabled. The reason for that is ARM core clock is shut down unexpectedly by WAIT mode. It happens with the following call stack: cpuidle_register_governor() cpuidle_switch_governor() cpuidle_uninstall_idle_handler() synchronize_sched() wait_rcu_gp() wait_for_completion() When wait_for_completion() is called as above, all cores are idle/WFI. Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a hardware shutdown of the ARM core clock. To fix the regression, we need to ensure that CCM_CLPCR_LPM is initialized into RUN mode earlier than cpuidle governor registration, which is a postcore_initcall. This patch creates function imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into RUN mode, and have the function called from machine .init_irq hook, which should be early enough. Reported-by: Kevin Hilman <khilman@kernel.org> Fixes: 8fb76a07e2cb ("ARM: imx6: set initial power mode in pm function") Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Tyler Baker <tyler.baker@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: drop epit timer initialization from imx35 clock driverShawn Guo2015-06-031-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EPIT provides another timer implementation besides the default GPT timer. The imx35 clock driver will use EPIT timer when option CONFIG_MXC_USE_EPIT is enabled. However, initializing timers from clock driver is a workaround solution and causes problem when we move clock drivers into driver/clk. Let's simply drop the EPIT initialization from there. If people really want this EPIT option, EPIT timer driver needs to be reworked to do the initialization in a standard way - use CLOCKSOURCE_OF_DECLARE() with device tree support. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | MAINTAINERS: add new folders into IMX entryShawn Guo2015-06-031-0/+2
| | | | | | | | | | | | | | | | | | | | | Add new created folders drivers/clk/imx/ and include/soc/imx/ into IMX entry. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: move clock drivers into drivers/clkShawn Guo2015-06-0326-16/+37
| | | | | | | | | | | | | | | | | | | | | | | | After the cleanup on clock drivers, they are now ready to be moved into drivers/clk. Let's move them into drivers/clk/imx folder. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * | ARM: imx: remove inclusions of platform headersShawn Guo2015-06-0312-23/+59
| | | | | | | | | | | | | | | | | | | | | | | | With the cleanup done before, we now can simply define base address and irq as needed in clock driver, to get those platform header inclusions removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: add clk-pllv1 type supportShawn Guo2015-06-038-22/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of calling cpu_is_xxx() in clk-pllv1 driver, let's add clk-pllv1 type support to handle the difference/quirk in particular SoC designs. Doing so will help get clk-pllv1 driver ready for being moved out of arch/arm/mach-imx folder. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6: do not use cpu_is_xxx() in clock driverShawn Guo2015-06-031-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | As we're about to move clock drivers out of arch/arm/mach-imx, cpu_is_xxx() shouldn't be used any more. Let's avoid the call by looking at the device tree machine compatible string to determine which SoC the clock driver is running on. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6: let pm code map CCM block on its ownShawn Guo2015-06-035-15/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | We are about to move imx6 clock driver into drivers/clk, so let's get imx6 pm code map CCM block on its own rather than relying on clock driver to do the mapping. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6: set initial power mode in pm functionShawn Guo2015-06-038-22/+15Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than setting initial low-power mode in every single i.MX6 clock initialization function, we should really do that in pm code. Let's move imx6q_set_lpm(WAIT_CLOCKED) call into imx6_pm_common_init(). While at it, let's rename the function to imx6_set_lpm() since it's actually common for all i.MX6 SoCs. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx5: let pm code map CCM block on its ownShawn Guo2015-06-033-9/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | We are about to move imx5 clock driver into drivers/clk, so let's get imx5 pm code map CCM block on its own rather than relying on clock driver to do the mapping. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: move revision definitions and declarations into a headerShawn Guo2015-06-036-31/+38
| | | | | | | | | | | | | | | | | | | | | | | | The revision definitions and declarations are widely used by clock drivers. As a step of moving clock drivers out of arch/arm/mach-imx, let's create header include/soc/imx/revision.h to accommodate them. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: use dynamic mapping for CCMShawn Guo2015-06-033-3/+10
| | | | | | | | | | | | | | | | | | | | | Replace the static mapping of CCM block in clock drivers with dynamic mapping. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: use dynamic mapping for timerShawn Guo2015-06-037-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | Pass physical address of timer block to mxc_timer_init() call, which in turn does dynamic mapping within the function. Thus, we can avoid using static mapping in clock drivers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | dt-bindings: add imx7d clock ID definitionsFrank Li2015-06-031-0/+450
| |/ | | | | | | | | | | | | | | It adds the imx7d clock ID definitions which will be used by both imx7d clock driver and device tree. Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge branch 'socfpga/soc' into next/socKevin Hilman2015-06-117-6/+342
|\ \ | | | | | | | | | | | | | | | | | | * socfpga/soc: ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
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