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* ARM: LPAE: Introduce the 3-level page table format definitionsCatalin Marinas2011-12-086-0/+261
| | | | | | | | | | | | | | | This patch introduces the pgtable-3level*.h files with definitions specific to the LPAE page table format (3 levels of page tables). Each table is 4KB and has 512 64-bit entries. An entry can point to a 40-bit physical address. The young, write and exec software bits share the corresponding hardware bits (negated). Other software bits use spare bits in the PTE. The patch also changes some variable types from unsigned long or int to pteval_t or pgprot_t. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM: LPAE: add ISBs around MMU enabling codeWill Deacon2011-12-084-0/+16
| | | | | | | | | | | | | Before we enable the MMU, we must ensure that the TTBR registers contain sane values. After the MMU has been enabled, we jump to the *virtual* address of the following function, so we also need to ensure that the SCTLR write has taken effect. This patch adds ISB instructions around the SCTLR write to ensure the visibility of the above. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.SCatalin Marinas2011-12-082-149/+174
| | | | | | | | This patch modifies the proc-v7.S file so that it only contains code shared between classic MMU and LPAE. The non-common code is factored out into a separate file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM: LPAE: Move the FSR definitions to separate filesCatalin Marinas2011-12-083-93/+100
| | | | | | | | | The FSR structure is different with LPAE and this patch moves the classic MMU specific definition to a separate fsr-2level.c file that is included in fault.c. It also moves the fsr_fs and FSR bits to the fault.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM: LPAE: Move page table maintenance macros to pgtable-2level.hCatalin Marinas2011-12-082-38/+41
| | | | | | | | The page table maintenance macros need to be duplicated between the classic and the LPAE MMU so this patch moves those that are not common to the pgtable-2level.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM: pgtable: switch to use pgtable-nopud.hRussell King2011-12-083-11/+15
| | | | | | | | | | | | | | Nick Piggin noted upon introducing 4level-fixup.h: | Add a temporary "fallback" header so architectures can run with | the 4level pagetables patch without modification. All architectures | should be converted to use the folding headers (include/asm-generic/ | pgtable-nop?d.h) as soon as possible, and the fallback header removed. This makes ARM compliant with this statement. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM: pgtable: Fix compiler warning in ioremap.c introduced by nopudCatalin Marinas2011-12-081-12/+19
| | | | | | | | | | | | With the arch/arm code conversion to pgtable-nopud.h, the section and supersection (un|re)map code triggers compiler warnings on UP systems. This is caused by pmd_offset() being given a pgd_t argument rather than a pud_t one. This patch makes the necessary conversion with the assumption that the pud is folded into the pgd. The page table setting code only loops over the pmd which is enough with the classic page tables. This code is not compiled when LPAE is enabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM: SMP: use idmap_pgd for mapping MMU enable during secondary bootingWill Deacon2011-12-064-66/+6Star
| | | | | | | | | | | | | | | | | | | | | | The ARM SMP booting code allocates a temporary set of page tables containing an identity mapping of the kernel image and provides this to secondary CPUs for initial booting. In reality, we only need to include the __turn_mmu_on function in the identity mapping since the rest of the kernel is executing from virtual addresses after this point. This patch adds __turn_mmu_on to the .idmap.text section, allowing the SMP booting code to use the idmap_pgd directly and not have to populate its own set of page table. As a result of this patch, we can make the identity_mapping_add function static (since it is only used within mm/idmap.c) and also remove the identity_mapping_del function. The identity map population is moved to an early initcall so that it is setup in time for secondary CPU bringup. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: head.S: only include __turn_mmu_on in the initial identity mappingWill Deacon2011-12-061-7/+7
| | | | | | | | | | | | __create_page_tables identity maps the region of memory from __enable_mmu to the end of __turn_mmu_on. In preparation for including __turn_mmu_on in the .idmap.text section, this patch modifies the identity mapping so that it only includes the __turn_mmu_on code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: idmap: use idmap_pgd when setting up mm for rebootWill Deacon2011-12-061-9/+10
| | | | | | | | | | | | | | | | | | | | | For soft-rebooting a system, it is necessary to map the MMU-off code with an identity mapping so that execution can continue safely once the MMU has been switched off. Currently, switch_mm_for_reboot takes out a 1:1 mapping from 0x0 to TASK_SIZE during reboot in the hope that the reset code lives at a physical address corresponding to a userspace virtual address. This patch modifies the code so that we switch to the idmap_pgd tables, which contain a 1:1 mapping of the cpu_reset code. This has the advantage of only remapping the code that we need and also means we don't need to worry about allocating a pgd from an atomic context in the case that the physical address of the cpu_reset code aliases with the virtual space used by the kernel. Acked-by: Dave Martin <dave.martin@linaro.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: proc-*.S: place cpu_reset functions into .idmap.text sectionWill Deacon2011-12-0624-0/+72
| | | | | | | | | | | The CPU reset functions disable the MMU and therefore must be executed with an identity mapping in place. This patch places the CPU reset functions into the .idmap.text section, causing the idmap code to include them as part of the identity mapping. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: suspend: use idmap_pgd instead of suspend_pgdWill Deacon2011-12-062-15/+5Star
| | | | | | | | | | | | | | | | The ARM CPU suspend code requires cpu_resume_mmu to be identity mapped in order to re-enable the MMU when coming out of suspend. Currently, this is accomplished by maintaining a suspend_pgd with the relevant mapping put in place at init time. This patch replaces the use of suspend_pgd with the new idmap_pgd. cpu_resume_mmu is placed in the .idmap.text section so that it is included in the identity map. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Dave Martin <dave.martin@linaro.org> Tested-by: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: idmap: populate identity map pgd at init time using .init.textWill Deacon2011-12-065-3/+51
| | | | | | | | | | | | | | | | | | When disabling and re-enabling the MMU, it is necessary to take out an identity mapping for the code that manipulates the SCTLR in order to avoid it disappearing from under our feet. This is useful when soft rebooting and returning from CPU suspend. This patch allocates a set of page tables during boot and populates them with an identity mapping for the .idmap.text section. This means that users of the identity map do not need to manage their own pgd and can instead annotate their functions with __idmap or, in the case of assembly code, place them in the correct section. Acked-by: Dave Martin <dave.martin@linaro.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: 7189/1: OMAP3: Fix build break in cpuidle34xx.c because of irq functionSantosh Shilimkar2011-12-061-0/+1
| | | | | | | | | | | | Fix the below build break by including common.h arch/arm/mach-omap2/cpuidle34xx.c: In function 'omap3_enter_idle': arch/arm/mach-omap2/cpuidle34xx.c:117: error: implicit declaration of function 'omap_irq_pending' make[1]: *** [arch/arm/mach-omap2/cpuidle34xx.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7188/1: OMAP2PLUS: Fix build error: 'omap2/omap3_intc_handle_irq' ↵Santosh Shilimkar2011-12-061-0/+2
| | | | | | | | | | undeclared. Fix the build break by adding the necessary irq functions to common header. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'irqchip-consolidation' of ↵Russell King2011-12-032-2/+2
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into devel-stable
| * ARM: exynos4: Fix build errorAxel Lin2011-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | Trivial fix to fix below build error: CC arch/arm/mach-exynos/mach-universal_c210.o arch/arm/mach-exynos/mach-universal_c210.c:24: error: expected identifier or '(' before '<' token Signed-off-by: Axel Lin <axel.lin@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: exynos4: Fix build error due to 'gic_bank_offset' undeclaredAxel Lin2011-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix below build error: CC arch/arm/mach-exynos/cpu.o arch/arm/mach-exynos/cpu.c: In function 'exynos4_init_irq': arch/arm/mach-exynos/cpu.c:245: error: 'gic_bank_offset' undeclared (first use in this function) arch/arm/mach-exynos/cpu.c:245: error: (Each undeclared identifier is reported only once arch/arm/mach-exynos/cpu.c:245: error: for each function it appears in.) arch/arm/mach-exynos/cpu.c:243: warning: unused variable 'bank_offset' make[1]: *** [arch/arm/mach-exynos/cpu.o] Error 1 make: *** [arch/arm/mach-exynos] Error 2 Signed-off-by: Axel Lin <axel.lin@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | Merge branch 'irqchip-consolidation' of ↵Russell King2011-11-21419-3746/+4216
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into devel-stable Conflicts: arch/arm/mach-omap2/board-4430sdp.c arch/arm/mach-omap2/board-omap4panda.c arch/arm/mach-omap2/include/mach/omap4-common.h arch/arm/plat-omap/include/plat/irqs.h The changes to omap4-common.h were moved to arch/arm/mach-omap2/common.h and the other trivial conflicts resolved. The now empty ifdef in irqs.h was also eliminated.
| * ARM: VIC: remove non MULTI_IRQ_HANDLER supportJamie Iles2011-11-154-70/+1Star
| | | | | | | | | | | | | | | | Now that all platforms are converted to MULTI_IRQ_HANDLER, remove the legacy support. Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: picoxcell: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-153-12/+9Star
| | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for picoxcell to help building multi platform kernels. Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: samsung: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-1512-65/+23Star
| | | | | | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for samsung to help building multi platform kernels. Cc: Kukjin Kim <kgene.kim@samsung.com> Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: versatile: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-155-30/+7Star
| | | | | | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for versatile to help building multi platform kernels. Cc: Russell King <linux@arm.linux.org.uk> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: u300: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-153-24/+3Star
| | | | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for u300 to help building multi platform kernels. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: spear: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-157-63/+9Star
| | | | | | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for spear to help building multi platform kernels. Acked-by: Viresh Kumar <viresh.kumar@st.com> Cc: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: s3c64xx: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-1512-3/+25
| | | | | | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for s3c64xx to help building multi platform kernels. Cc: Ben Dooks <ben-linux@fluff.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: nomadik: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-153-30/+3Star
| | | | | | | | | | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for nomadik to help building multi platform kernels. Cc: Alessandro Rubini <rubini@unipv.it> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: STEricsson <STEricsson_nomadik_linux@list.st.com> Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: netx: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-155-13/+7Star
| | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for netx to help building multi platform kernels. Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: ep93xx: convert to MULTI_IRQ_HANDLERJamie Iles2011-11-159-42/+25Star
| | | | | | | | | | | | | | | | | | Now that there is a generic IRQ handler for multiple VIC devices use it for ep93xx to help building multi platform kernels. Cc: Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ryan Mallon <rmallon@gmail.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: vic: MULTI_IRQ_HANDLER handlerJamie Iles2011-11-152-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a handler for the VIC that is suitable for MULTI_IRQ_HANDLER platforms. This can replace the ASM entry macros for platforms that use the VIC. v4: - rebase ontop of move __exception and friends to asm/exception.h - rework polling loop to handle as many irqs as possible in one go v3: - simplify irq handling loop as suggested by Grant - service interrupts from msb->lsb order v2: - allow the handler be used for !CONFIG_OF - use irq_domain_to_irq() Cc: Rob Herring <robherring2@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: vic: device tree bindingJamie Iles2011-11-154-29/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a device tree binding for the VIC based on the of_irq_init() support. This adds an irqdomain to the vic and always registers all vics in the static vic array rather than for pm only to keep track of the irq domain. struct irq_data::hwirq is used where appropriate rather than runtime masking. v3: - include linux/export.h for THIS_MODULE v2: - use irq_domain_simple_ops - remove stub implementation of vic_of_init for !CONFIG_OF - Make VIC select IRQ_DOMAIN Reviewed-by: Rob Herring <robherring2@gmail.com> Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: GIC: Make MULTI_IRQ_HANDLER mandatoryMarc Zyngier2011-11-1510-76/+2Star
| | | | | | | | | | | | | | Now that MULTI_IRQ_HANDLER is selected by all the in-tree GIC users, make it mandatory and remove the unused macros. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: omap2plus: remove irq-related global base addressesMarc Zyngier2011-11-155-9/+4Star
| | | | | | | | | | | | | | After the MULTI_IRQ_HANDLER conversion, a couple of global variables can be removed. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-1529-137/+36Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the omap2plus platforms to be using CONFIG_MULTI_IRQ_HANDLER. Each machine is modified to provide either omap2_intc_handle_irq(), omap3_intc_handle_irq() or gic_handle_irq(). This allows for a major cleanup, removing the MULTI_OMAP setup from the interrupt path. Tested on both Panda and IGEPv2 (single kernel image) Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: omap2/3: Add global omap2/3_intc_handle_irq() functionsMarc Zyngier2011-11-152-0/+52
| | | | | | | | | | | | | | | | | | | | Provide the OMAP2/3 IRQ code with low level handlers that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handlers are written in C, the compiled code looks very similar to its assembly counterpart (at least with my gcc 4.4.1). Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-153-3/+2Star
| | | | | | | | | | | | | | | | Convert the zynq platform to be using the gic_handle_irq function as its primary interrupt handler. Acked-by: John Linn <john.linn@xilinx.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-153-2/+3
| | | | | | | | | | | | | | | | Convert the cns3xxx platform to be using the gic_handle_irq function as its primary interrupt handler. Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: shmobile: convert smp platforms to gic_handle_irq()Marc Zyngier2011-11-155-22/+2Star
| | | | | | | | | | | | | | | | Convert the SMP shmobile platforms to use gic_handle_irq() instead of the assembly macro. Cc: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-154-2/+7
| | | | | | | | | | | | | | | | Convert the ux500 platforms to be using the gic_handle_irq function as their primary interrupt handler. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-157-20/+15Star
| | | | | | | | | | | | | | | | | | | | | | | | Convert the tegra2 platforms to be using the gic_handle_irq function as their primary interrupt handler. Tested on harmony. Cc: Colin Cross <ccross@android.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-159-78/+18Star
| | | | | | | | | | | | | | | | | | Convert the Exynos4 platforms to be using the gic_handle_irq function as their primary interrupt handler. Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-156-58/+31Star
| | | | | | | | | | | | | | | | | | Convert the SMP msm platforms to be using the gic_handle_irq function as their primary interrupt handler. Tested-by: David Brown <davidb@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: VExpress: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-153-2/+3
| | | | | | | | | | | | | | Convert the VExpress platform to be using the gic_handle_irq function as its primary interrupt handler. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: RealView: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-157-2/+6
| | | | | | | | | | | | | | Convert the RealView platforms to be using the gic_handle_irq function as their primary interrupt handler. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: highbank: convert to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-153-2/+2
| | | | | | | | | | | | | | | | Convert the highbank platform to be using the gic_handle_irq function as its primary interrupt handler. Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: imx: convert smp platforms to global gic_handle_irq()Marc Zyngier2011-11-154-55/+1Star
| | | | | | | | | | | | | | | | | | Convert the SMP imx platforms to use the global gic_handle_irq() function instead a private function. Cc: Sascha Hauer <kernel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: GIC: Add global gic_handle_irq() functionMarc Zyngier2011-11-152-0/+28
| | | | | | | | | | | | | | Provide the GIC code with a low level handler that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: mxc: rename gic_handle_irq to avoid name clashMarc Zyngier2011-11-152-3/+3
| | | | | | | | | | | | | | | | | | | | Before introducing a global gic_handle_irq(), rename MXC's version to mxc_gic_handle_irq(). This function will be removed altogether in a later patch. Cc: Sascha Hauer <kernel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusiveMarc Zyngier2011-11-153-49/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code requires the arch_irq_handler_default macro to be defined as a fallback. It turns out nobody is using that particular feature as both PXA and shmobile have all their machine descriptors populated with the interrupt handler, leaving unused code (or empty macros) in their entry-macro.S file just to be able to compile entry-armv.S. Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default, which allows to remove one test from the hot path. Also cleanup both PXA and shmobile entry-macro.S. Cc: Paul Mundt <lethal@linux-sh.org> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Eric Miao <eric.y.miao@gmail.com> Tested-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: gic: allow GIC to support non-banked setupsMarc Zyngier2011-11-157-77/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC support code is heavily using the fact that hardware implementations are exposing banked registers. Unfortunately, it looks like at least one GIC implementation (EXYNOS) offers both the distributor and the CPU interfaces at different addresses, depending on the CPU. This problem is solved by allowing the distributor and CPU interface addresses to be per-cpu variables for the platforms that require it. The EXYNOS code is updated not to mess with the GIC internals while handling interrupts, and struct gic_chip_data is back to being private. The DT binding for the gic is updated to allow an optional "cpu-offset" value, which is used to compute the various base addresses. Finally, a new config option (GIC_NON_BANKED) is used to control this feature, so the overhead is only present on kernels compiled with support for EXYNOS. Tested on Origen (EXYNOS4) and Panda (OMAP4). Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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