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| * | | MIPS: Spelling fix lets -> let'sRalf Baechle2016-05-289-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As noticed by Sergei in the discussion of Andrea Gelmini's patch series. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
| * | | MIPS: VR41xx: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13338/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: oprofile: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: rric@kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/13334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: math-emu: Fix typoAndrea Gelmini2016-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: macro@imgtec.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13333/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: lib: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13331/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: kernel: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: paul.burton@imgtec.com Cc: macro@imgtec.com Cc: james.hogan@imgtec.com Cc: jslaby@suse.cz Cc: adam.buchbinder@gmail.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13330/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: R6: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: macro@imgtec.com Cc: paul.burton@imgtec.com Cc: Leonid.Yegoshin@imgtec.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13329/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: IP22/IP28: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: adam.buchbinder@gmail.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13328/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Cavium: Fix typoAndrea Gelmini2016-05-284-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: david.daney@cavium.com Cc: janne.huttunen@nokia.com Cc: aaro.koskinen@nokia.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13324/ Patchwork: https://patchwork.linux-mips.org/patch/13325/ Patchwork: https://patchwork.linux-mips.org/patch/13326/ Patchwork: https://patchwork.linux-mips.org/patch/13327/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: MT: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13323/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Loongson64: Fix typoAndrea Gelmini2016-05-282-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: chenhc@lemote.com Cc: viresh.kumar@linaro.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13322/ Patchwork: https://patchwork.linux-mips.org/patch/13332/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: IP32: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: IP27: Fix typoAndrea Gelmini2016-05-283-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13320/ Patchwork: https://patchwork.linux-mips.org/patch/13335/ Patchwork: https://patchwork.linux-mips.org/patch/13336/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: BCM63xx: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13319/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Alchemy: Fix typoAndrea Gelmini2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13318/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: hazards.h: Fix typoAndrea Gelmini2016-05-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: chenhc@lemote.com Cc: james.hogan@imgtec.com Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13317/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Lasat: A couple off by one bugs in picvue_proc.cDan Carpenter2016-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These should be ">=" instead of ">" or we go past the end of the pvc_lines[] array. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: linux-mips@linux-mips.org Cc: kernel-janitors@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6124/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: ralink: add MT7628 EPHY LEDs pinmux supportÁlvaro Fernández Rojas2016-05-281-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Cc: john@phrozen.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13308/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: ralink: fix MT7628 wled_an pinmux gpioÁlvaro Fernández Rojas2016-05-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Cc: john@phrozen.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: ralink: fix MT7628 pinmux typosÁlvaro Fernández Rojas2016-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Cc: john@phrozen.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13306/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Fix write_gc0_* macros when writing zeroJames Hogan2016-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The versions of the __write_{32,64}bit_gc0_register() macros for when there is no virt support in the assembler use the "J" inline asm constraint to allow integer zero, but this needs to be accompanied by the "z" formatting string so that it turns into $0. Fix both macros to do this. Fixes: bad50d79255a ("MIPS: Fix VZ probe gas errors with binutils <2.24") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13289/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: CPS: Copy EVA configuration when starting secondary VPs.Matt Redfearn2016-05-281-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When starting secondary VPEs which support EVA and the SegCtl registers, copy the memory segmentation configuration from the running VPE to ensure that all VPEs in the core have a consistent virtual memory map. The EVA configuration of secondary cores is dealt with when starting the core via the CM. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13291/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Add definitions of SegCtl registers and use themMatt Redfearn2016-05-282-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of these registers and use them rather than constants Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Chris Packham <judge.packham@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13290/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | dt/bindings: Correct clk binding example for PIC32 gpio.Purna Chandra Mandal2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: linux-gpio@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13270/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | dt/bindings: Correct clk binding example for PIC32 WDT.Purna Chandra Mandal2016-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Joshua Henderson <digitalpeer@digitalpeer.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13269/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | dt/bindings: Correct clk binding example for PIC32 DMT.Purna Chandra Mandal2016-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Joshua Henderson <digitalpeer@digitalpeer.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13268/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | dt/bindings: Correct clk binding example for PIC32 serial.Purna Chandra Mandal2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Joshua Henderson <digitalpeer@digitalpeer.com> Cc: Andrei Pistirica <andrei.pistirica@microchip.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13267/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | dt/bindings: Correct clk binding example for PIC32 pinctrlPurna Chandra Mandal2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Joshua Henderson <digitalpeer@digitalpeer.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13266/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | dt/bindings: Correct clk binding example for PIC32 SDHCIPurna Chandra Mandal2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update binding example based on new clock binding documentation. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Joshua Henderson <digitalpeer@digitalpeer.com> Cc: Andrei Pistirica <andrei.pistirica@microchip.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13265/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Fix incomplete separation of XPA CPU featureJames Hogan2016-05-281-3/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 12822570a29b ("MIPS: Separate XPA CPU feature into LPA and MVH") wasn't fully applied, possibly due to a conflict with commit f270d881fa55 ("MIPS: Detect MIPSr6 Virtual Processor support"). This left decode_config5() referring to the non-existent MIPS_CPU_XPA, which breaks the build when XPA is enabled: arch/mips/kernel/cpu-probe.c In function ‘decode_config5’: arch/mips/kernel/cpu-probe.c:838:17: error: ‘MIPS_CPU_XPA’ undeclared (first use in this function) c->options |= MIPS_CPU_XPA; ^ Apply the missing hunk, dropping the CONFIG_XPA ifdef and setting the MIPS_CPU_MVH option when Config5.MVH is set. Fixes: 12822570a29b ("MIPS: Separate XPA CPU feature into LPA and MVH") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Link: https://patchwork.linux-mips.org/patch/13112/ Patchwork: https://patchwork.linux-mips.org/patch/13277/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | irqchip: mips-gic: Setup EIC mode on each CPU if it's in usePaul Burton2016-05-281-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When EIC mode is in use (cpu_has_veic is true) enable it on each CPU during GIC initialisation. Otherwise there may be a mismatch between the hardware default interrupt model & that expected by the kernel. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com> Tested-by: Matt Redfearn <matt.redfearn@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13274/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: smp-cps: Clear Status IPL field when using EICPaul Burton2016-05-281-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com> Tested-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13273/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Clear Status IPL field when using EICPaul Burton2016-05-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Without doing so we default to arbitrarily ignoring all or some subset of interrupts. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com> Tested-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: Joe Perches <joe@perches.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13272/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | fs: fix binfmt_aout.c build errorGuenter Roeck2016-05-291-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various builds (such as i386:allmodconfig) fail with fs/binfmt_aout.c:133:2: error: expected identifier or '(' before 'return' fs/binfmt_aout.c:134:1: error: expected identifier or '(' before '}' token [ Oops. My bad, I had stupidly thought that "allmodconfig" covered this on x86-64 too, but it obviously doesn't. Egg on my face. - Linus ] Fixes: 5d22fc25d4fc ("mm: remove more IS_ERR_VALUE abuses") Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | Merge branch 'hash' of git://ftp.sciencehorizons.net/linuxLinus Torvalds2016-05-2917-150/+734
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull string hash improvements from George Spelvin: "This series does several related things: - Makes the dcache hash (fs/namei.c) useful for general kernel use. (Thanks to Bruce for noticing the zero-length corner case) - Converts the string hashes in <linux/sunrpc/svcauth.h> to use the above. - Avoids 64-bit multiplies in hash_64() on 32-bit platforms. Two 32-bit multiplies will do well enough. - Rids the world of the bad hash multipliers in hash_32. This finishes the job started in commit 689de1d6ca95 ("Minimal fix-up of bad hashing behavior of hash_64()") The vast majority of Linux architectures have hardware support for 32x32-bit multiply and so derive no benefit from "simplified" multipliers. The few processors that do not (68000, h8/300 and some models of Microblaze) have arch-specific implementations added. Those patches are last in the series. - Overhauls the dcache hash mixing. The patch in commit 0fed3ac866ea ("namei: Improve hash mixing if CONFIG_DCACHE_WORD_ACCESS") was an off-the-cuff suggestion. Replaced with a much more careful design that's simultaneously faster and better. (My own invention, as there was noting suitable in the literature I could find. Comments welcome!) - Modify the hash_name() loop to skip the initial HASH_MIX(). This would let us salt the hash if we ever wanted to. - Sort out partial_name_hash(). The hash function is declared as using a long state, even though it's truncated to 32 bits at the end and the extra internal state contributes nothing to the result. And some callers do odd things: - fs/hfs/string.c only allocates 32 bits of state - fs/hfsplus/unicode.c uses it to hash 16-bit unicode symbols not bytes - Modify bytemask_from_count to handle inputs of 1..sizeof(long) rather than 0..sizeof(long)-1. This would simplify users other than full_name_hash" Special thanks to Bruce Fields for testing and finding bugs in v1. (I learned some humbling lessons about "obviously correct" code.) On the arch-specific front, the m68k assembly has been tested in a standalone test harness, I've been in contact with the Microblaze maintainers who mostly don't care, as the hardware multiplier is never omitted in real-world applications, and I haven't heard anything from the H8/300 world" * 'hash' of git://ftp.sciencehorizons.net/linux: h8300: Add <asm/hash.h> microblaze: Add <asm/hash.h> m68k: Add <asm/hash.h> <linux/hash.h>: Add support for architecture-specific functions fs/namei.c: Improve dcache hash function Eliminate bad hash multipliers from hash_32() and hash_64() Change hash_64() return value to 32 bits <linux/sunrpc/svcauth.h>: Define hash_str() in terms of hashlen_string() fs/namei.c: Add hashlen_string() function Pull out string hash to <linux/stringhash.h>
| * | | | h8300: Add <asm/hash.h>George Spelvin2016-05-282-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will improve the performance of hash_32() and hash_64(), but due to complete lack of multi-bit shift instructions on H8, performance will still be bad in surrounding code. Designing H8-specific hash algorithms to work around that is a separate project. (But if the maintainers would like to get in touch...) Signed-off-by: George Spelvin <linux@sciencehorizons.net> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: uclinux-h8-devel@lists.sourceforge.jp
| * | | | microblaze: Add <asm/hash.h>George Spelvin2016-05-282-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microblaze is an FPGA soft core that can be configured various ways. If it is configured without a multiplier, the standard __hash_32() will require a call to __mulsi3, which is a slow software loop. Instead, use a shift-and-add sequence for the constant multiply. GCC knows how to do this, but it's not as clever as some. Signed-off-by: George Spelvin <linux@sciencehorizons.net> Cc: Alistair Francis <alistair.francis@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
| * | | | m68k: Add <asm/hash.h>George Spelvin2016-05-282-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a multiply by constant GOLDEN_RATIO_32 = 0x61C88647 for the original mc68000, which lacks a 32x32-bit multiply instruction. Yes, the amount of optimization effort put in is excessive. :-) Shift-add chain found by Yevgen Voronenko's Hcub algorithm at http://spiral.ece.cmu.edu/mcm/gen.html Signed-off-by: George Spelvin <linux@sciencehorizons.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Andreas Schwab <schwab@linux-m68k.org> Cc: Philippe De Muyter <phdm@macq.eu> Cc: linux-m68k@lists.linux-m68k.org
| * | | | <linux/hash.h>: Add support for architecture-specific functionsGeorge Spelvin2016-05-286-4/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is just the infrastructure; there are no users yet. This is modelled on CONFIG_ARCH_RANDOM; a CONFIG_ symbol declares the existence of <asm/hash.h>. That file may define its own versions of various functions, and define HAVE_* symbols (no CONFIG_ prefix!) to suppress the generic ones. Included is a self-test (in lib/test_hash.c) that verifies the basics. It is NOT in general required that the arch-specific functions compute the same thing as the generic, but if a HAVE_* symbol is defined with the value 1, then equality is tested. Signed-off-by: George Spelvin <linux@sciencehorizons.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Andreas Schwab <schwab@linux-m68k.org> Cc: Philippe De Muyter <phdm@macq.eu> Cc: linux-m68k@lists.linux-m68k.org Cc: Alistair Francis <alistai@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: uclinux-h8-devel@lists.sourceforge.jp
| * | | | fs/namei.c: Improve dcache hash functionGeorge Spelvin2016-05-281-40/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch 0fed3ac866 improved the hash mixing, but the function is slower than necessary; there's a 7-instruction dependency chain (10 on x86) each loop iteration. Word-at-a-time access is a very tight loop (which is good, because link_path_walk() is one of the hottest code paths in the entire kernel), and the hash mixing function must not have a longer latency to avoid slowing it down. There do not appear to be any published fast hash functions that: 1) Operate on the input a word at a time, and 2) Don't need to know the length of the input beforehand, and 3) Have a single iterated mixing function, not needing conditional branches or unrolling to distinguish different loop iterations. One of the algorithms which comes closest is Yann Collet's xxHash, but that's two dependent multiplies per word, which is too much. The key insights in this design are: 1) Barring expensive ops like multiplies, to diffuse one input bit across 64 bits of hash state takes at least log2(64) = 6 sequentially dependent instructions. That is more cycles than we'd like. 2) An operation like "hash ^= hash << 13" requires a second temporary register anyway, and on a 2-operand machine like x86, it's three instructions. 3) A better use of a second register is to hold a two-word hash state. With careful design, no temporaries are needed at all, so it doesn't increase register pressure. And this gets rid of register copying on 2-operand machines, so the code is smaller and faster. 4) Using two words of state weakens the requirement for one-round mixing; we now have two rounds of mixing before cancellation is possible. 5) A two-word hash state also allows operations on both halves to be done in parallel, so on a superscalar processor we get more mixing in fewer cycles. I ended up using a mixing function inspired by the ChaCha and Speck round functions. It is 6 simple instructions and 3 cycles per iteration (assuming multiply by 9 can be done by an "lea" instruction): x ^= *input++; y ^= x; x = ROL(x, K1); x += y; y = ROL(y, K2); y *= 9; Not only is this reversible, two consecutive rounds are reversible: if you are given the initial and final states, but not the intermediate state, it is possible to compute both input words. This means that at least 3 words of input are required to create a collision. (It also has the property, used by hash_name() to avoid a branch, that it hashes all-zero to all-zero.) The rotate constants K1 and K2 were found by experiment. The search took a sample of random initial states (I used 1023) and considered the effect of flipping each of the 64 input bits on each of the 128 output bits two rounds later. Each of the 8192 pairs can be considered a biased coin, and adding up the Shannon entropy of all of them produces a score. The best-scoring shifts also did well in other tests (flipping bits in y, trying 3 or 4 rounds of mixing, flipping all 64*63/2 pairs of input bits), so the choice was made with the additional constraint that the sum of the shifts is odd and not too close to the word size. The final state is then folded into a 32-bit hash value by a less carefully optimized multiply-based scheme. This also has to be fast, as pathname components tend to be short (the most common case is one iteration!), but there's some room for latency, as there is a fair bit of intervening logic before the hash value is used for anything. (Performance verified with "bonnie++ -s 0 -n 1536:-2" on tmpfs. I need a better benchmark; the numbers seem to show a slight dip in performance between 4.6.0 and this patch, but they're too noisy to quote.) Special thanks to Bruce fields for diligent testing which uncovered a nasty fencepost error in an earlier version of this patch. [checkpatch.pl formatting complaints noted and respectfully disagreed with.] Signed-off-by: George Spelvin <linux@sciencehorizons.net> Tested-by: J. Bruce Fields <bfields@redhat.com>
| * | | | Eliminate bad hash multipliers from hash_32() and hash_64()George Spelvin2016-05-282-53/+36Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "simplified" prime multipliers made very bad hash functions, so get rid of them. This completes the work of 689de1d6ca. To avoid the inefficiency which was the motivation for the "simplified" multipliers, hash_64() on 32-bit systems is changed to use a different algorithm. It makes two calls to hash_32() instead. drivers/media/usb/dvb-usb-v2/af9015.c uses the old GOLDEN_RATIO_PRIME_32 for some horrible reason, so it inherits a copy of the old definition. Signed-off-by: George Spelvin <linux@sciencehorizons.net> Cc: Antti Palosaari <crope@iki.fi> Cc: Mauro Carvalho Chehab <m.chehab@samsung.com>
| * | | | Change hash_64() return value to 32 bitsGeorge Spelvin2016-05-281-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That's all that's ever asked for, and it makes the return type of hash_long() consistent. It also allows (upcoming patch) an optimized implementation of hash_64 on 32-bit machines. I tried adding a BUILD_BUG_ON to ensure the number of bits requested was never more than 32 (most callers use a compile-time constant), but adding <linux/bug.h> to <linux/hash.h> breaks the tools/perf compiler unless tools/perf/MANIFEST is updated, and understanding that code base well enough to update it is too much trouble. I did the rest of an allyesconfig build with such a check, and nothing tripped. Signed-off-by: George Spelvin <linux@sciencehorizons.net>
| * | | | <linux/sunrpc/svcauth.h>: Define hash_str() in terms of hashlen_string()George Spelvin2016-05-281-31/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Finally, the first use of previous two patches: eliminate the separate ad-hoc string hash functions in the sunrpc code. Now hash_str() is a wrapper around hash_string(), and hash_mem() is likewise a wrapper around full_name_hash(). Note that sunrpc code *does* call hash_mem() with a zero length, which is why the previous patch needed to handle that in full_name_hash(). (Thanks, Bruce, for finding that!) This also eliminates the only caller of hash_long which asks for more than 32 bits of output. The comment about the quality of hashlen_string() and full_name_hash() is jumping the gun by a few patches; they aren't very impressive now, but will be improved greatly later in the series. Signed-off-by: George Spelvin <linux@sciencehorizons.net> Tested-by: J. Bruce Fields <bfields@redhat.com> Acked-by: J. Bruce Fields <bfields@redhat.com> Cc: Jeff Layton <jlayton@poochiereds.net> Cc: linux-nfs@vger.kernel.org
| * | | | fs/namei.c: Add hashlen_string() functionGeorge Spelvin2016-05-283-9/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We'd like to make more use of the highly-optimized dcache hash functions throughout the kernel, rather than have every subsystem create its own, and a function that hashes basic null-terminated strings is required for that. (The name is to emphasize that it returns both hash and length.) It's actually useful in the dcache itself, specifically d_alloc_name(). Other uses in the next patch. full_name_hash() is also tweaked to make it more generally useful: 1) Take a "char *" rather than "unsigned char *" argument, to be consistent with hash_name(). 2) Handle zero-length inputs. If we want more callers, we don't want to make them worry about corner cases. Signed-off-by: George Spelvin <linux@sciencehorizons.net>
| * | | | Pull out string hash to <linux/stringhash.h>George Spelvin2016-05-282-26/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... so they can be used without the rest of <linux/dcache.h> The hashlen_* macros will make sense next patch. Signed-off-by: George Spelvin <linux@sciencehorizons.net>
* | | | | Merge branch 'i2c/for-next' of ↵Linus Torvalds2016-05-281-1/+1
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux Pull i2c fix from Wolfram Sang: "A fix for a regression introduced yesterday. The regression didn't show up here locally because I did not have PAGE_POISONING enabled. And buildbots discovered this only after it hit your tree. Thanks to Dan for the quick response" * 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: i2c: dev: use after free in detach
| * | | | | i2c: dev: use after free in detachDan Carpenter2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to put_i2c_dev() frees "i2c_dev" so there is a use after free when we call cdev_del(&i2c_dev->cdev). Fixes: d6760b14d4a1 ('i2c: dev: switch from register_chrdev to cdev API') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* | | | | | Merge tag 'chrome-platform' of ↵Linus Torvalds2016-05-289-17/+234
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/olof/chrome-platform Pull chrome platform updates from Olof Johansson "A handful of Chrome driver and binding changes this merge window: - a few patches to fix probing and configuration of pstore - a few patches adding Elan touchpad registration on a few devices - EC changes: a security fix dealing with max message sizes and addition of compat_ioctl support. - keyboard backlight control support There was also an accidential duplicate registration of trackpads on 'Leon', which was reverted just recently" * tag 'chrome-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/chrome-platform: Revert "platform/chrome: chromeos_laptop: Add Leon Touch" platform/chrome: chromeos_laptop - Add Elan touchpad for Wolf platform/chrome: chromeos_laptop - Add elan trackpad option for C720 platform/chrome: cros_ec_dev - Populate compat_ioctl platform/chrome: cros_ec_lightbar - use name instead of ID to hide lightbar attributes platform/chrome: cros_ec_dev - Fix security issue platform/chrome: Add Chrome OS keyboard backlight LEDs support platform/chrome: use to_platform_device() platform/chrome: pstore: Move to larger record size. platform/chrome: pstore: probe for ramoops buffer using acpi platform/chrome: chromeos_laptop: Add Leon Touch
| * | | | | | Revert "platform/chrome: chromeos_laptop: Add Leon Touch"Benson Leung2016-05-281-15/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bff3c624dc7261a084a4d25a0b09c3fb0fec872a. Board "Leon" is otherwise known as "Toshiba CB35" and we already have the entry that supports that board as of this commit : 963cb6f platform/chrome: chromeos_laptop - Add Toshiba CB35 Touch Remove this duplicate. Signed-off-by: Benson Leung <bleung@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | platform/chrome: chromeos_laptop - Add Elan touchpad for WolfCharlie Mooney2016-05-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The upcoming Elan Wolf (Dell Chromebook 11) devices need to know to look for Elan touchpads on the i2c bus so that they will be functional. Based on the chromeos-kernel commit : https://chromium-review.googlesource.com/198283 Signed-off-by: Charlie Mooney <charliemooney@chromium.org> Signed-off-by: Benson Leung <bleung@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-11 02:30:19 +0200