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* | Merge branch 'pci/misc' into nextBjorn Helgaas2017-04-282-2/+3
|\ \ | | | | | | | | | | | | | | | | | | * pci/misc: PCI: Change pci_host_common_probe() visibility PCI: Fix typo pci_cfg_access_lock() comment PCI: Include pci.h for struct pci_ops definition
| * | PCI: Change pci_host_common_probe() visibilityMarc Gonzalez2017-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_host_common_probe() is defined when CONFIG_PCI_HOST_COMMON=y; therefore the function declaration should match that. drivers/pci/host/pcie-tango.c:300:9: error: implicit declaration of function 'pci_host_common_probe' Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Fix typo pci_cfg_access_lock() commentBrian Norris2017-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | | There is no pci_cfg_access_unlocked(). I think the author meant pci_cfg_access_unlock(). Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Include pci.h for struct pci_ops definitionMarc Gonzalez2017-03-231-0/+1
| |/ | | | | | | | | | | | | | | | | struct pci_ecam_ops embeds a struct pci_ops. Explicitly request the definition for struct pci_ops, otherwise gcc might complain: include/linux/pci-ecam.h:29:19: error: field 'pci_ops' has incomplete type Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/irq' into nextBjorn Helgaas2017-04-286-23/+115
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * pci/irq: PCI: Disable boot interrupt quirk for ASUS M2N-LR nvme/pci: Switch to pci_request_irq() PCI/irq: Add pci_request_irq() and pci_free_irq() helpers genirq: Return the IRQ name from free_irq() genirq: Fix indentation in remove_irq()
| * | PCI: Disable boot interrupt quirk for ASUS M2N-LRStefan Assmann2017-04-241-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ASUS M2N-LR should not trigger boot interrupt quirks although it carries an Intel 6702PXH. On this board the boot interrupt quirks cause incorrect IRQ assignments and should be disabled. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=43074 Tested-by: Solomon Peachy <pizza@shaftnet.org> Signed-off-by: Stefan Assmann <sassmann@kpanic.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | nvme/pci: Switch to pci_request_irq()Christoph Hellwig2017-04-181-17/+13Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Keith Busch <keith.busch@intel.com>
| * | PCI/irq: Add pci_request_irq() and pci_free_irq() helpersChristoph Hellwig2017-04-182-1/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are small wrappers around request_threaded_irq() and free_irq(), which dynamically allocate space for the device name so that drivers don't need to keep static buffers for these around. Additionally it works with device-relative vector numbers to make the usage easier, and force the IRQF_SHARED flag on given that it has no runtime overhead and should be supported by all PCI devices. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
| * | genirq: Return the IRQ name from free_irq()Christoph Hellwig2017-04-182-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | This allows callers to get back at them instead of having to store it in another variable. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
| * | genirq: Fix indentation in remove_irq()Christoph Hellwig2017-04-181-1/+1
| |/ | | | | | | | | Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
* | Merge branch 'pci/ioremap' into nextBjorn Helgaas2017-04-2824-31/+185
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/ioremap: PCI: versatile: Update PCI config space remap function PCI: keystone-dw: Update PCI config space remap function PCI: layerscape: Update PCI config space remap function PCI: hisi: Update PCI config space remap function PCI: tegra: Update PCI config space remap function PCI: xgene: Update PCI config space remap function PCI: armada8k: Update PCI config space remap function PCI: designware: Update PCI config space remap function PCI: iproc-platform: Update PCI config space remap function PCI: qcom: Update PCI config space remap function PCI: rockchip: Update PCI config space remap function PCI: spear13xx: Update PCI config space remap function PCI: xilinx-nwl: Update PCI config space remap function PCI: xilinx: Update PCI config space remap function PCI: ECAM: Map config region with pci_remap_cfgspace() PCI: Implement devm_pci_remap_cfgspace() devres: fix devm_ioremap_*() offset parameter kerneldoc description ARM: Implement pci_remap_cfgspace() interface ARM64: Implement pci_remap_cfgspace() interface linux/io.h: Add pci_remap_cfgspace() interface PCI: Remove __weak tag from pci_remap_iospace()
| * | PCI: versatile: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_ioremap_nopost* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rob Herring <robh@kernel.org>
| * | PCI: keystone-dw: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
| * | PCI: layerscape: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Mingkai Hu <mingkai.hu@freescale.com> Cc: Minghuan Lian <minghuan.Lian@freescale.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
| * | PCI: hisi: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-4/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Zhou Wang <wangzhou1@hisilicon.com>
| * | PCI: tegra: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use correct memory mapping attributes to map config space regions to enforce configuration space non-posted writes behaviour. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com>
| * | PCI: xgene: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Tanmay Inamdar <tinamdar@apm.com>
| * | PCI: armada8k: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
| * | PCI: designware: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
| * | PCI: iproc-platform: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com>
| * | PCI: qcom: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | PCI: rockchip: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Wenrui Li <wenrui.li@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
| * | PCI: spear13xx: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generate on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@gmail.com>
| * | PCI: xilinx-nwl: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
| * | PCI: xilinx: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
| * | PCI: ECAM: Map config region with pci_remap_cfgspace()Lorenzo Pieralisi2017-04-241-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ECAM kernel implementation uses ioremap() to map the ECAM configuration space memory region; this is not safe in that on some architectures the ioremap interface provides mappings that allow posted write transactions. This, as highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Address Mechanism"), can create ordering issues for software because posted writes transactions on the CPU host bus are non posted in the PCI express fabric. Update the ioremap() interface to use pci_remap_cfgspace() whose mapping attributes guarantee that non-posted writes transactions are issued for memory writes within the ECAM memory mapped address region. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jayachandran C <jnair@caviumnetworks.com>
| * | PCI: Implement devm_pci_remap_cfgspace()Lorenzo Pieralisi2017-04-243-2/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The introduction of the pci_remap_cfgspace() interface allows PCI host controller drivers to map PCI config space through a dedicated kernel interface. Current PCI host controller drivers use the devm_ioremap_*() devres interfaces to map PCI configuration space regions so in order to update them to the new pci_remap_cfgspace() mapping interface a new set of devres interfaces should be implemented so that PCI host controller drivers can make use of them. Introduce two new functions in the PCI kernel layer and Devres documentation: - devm_pci_remap_cfgspace() - devm_pci_remap_cfg_resource() so that PCI host controller drivers can make use of them to map PCI configuration space regions. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jonathan Corbet <corbet@lwn.net>
| * | devres: fix devm_ioremap_*() offset parameter kerneldoc descriptionLorenzo Pieralisi2017-04-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The offset parameter in the devres devm_ioremap_*() functions kerneldoc entries is erroneously defined as BUS offset whereas it is actually a resource address. Since it is actually misleading, fix the devres devm_ioremap_* offset parameter kerneldoc entry by replacing BUS offset with a more suitable description (ie Resource address). Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Tejun Heo <tj@kernel.org>
| * | ARM: Implement pci_remap_cfgspace() interfaceLorenzo Pieralisi2017-04-243-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and Posting") defines rules for PCI configuration space transactions ordering and posting, that state that configuration writes have to be non-posted transactions. Current ioremap interface on ARM provides mapping functions that provide "bufferable" writes transactions (ie ioremap uses MT_DEVICE memory type) aka posted writes, so PCI host controller drivers have no arch interface to remap PCI configuration space with memory attributes that comply with the PCI specifications for configuration space. Implement an ARM specific pci_remap_cfgspace() interface that allows to map PCI config memory regions with MT_UNCACHED memory type (ie strongly ordered - non-posted writes), providing a remap function that complies with PCI specifications for config space transactions. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@armlinux.org.uk>
| * | ARM64: Implement pci_remap_cfgspace() interfaceLorenzo Pieralisi2017-04-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and Posting") defines rules for PCI configuration space transactions ordering and posting, that state that configuration writes are non-posted transactions. This rule is reinforced by the ARM v8 architecture reference manual (issue A.k, Early Write Acknowledgment) that explicitly recommends that No Early Write Acknowledgment attribute should be used to map PCI configuration (write) transactions. Current ioremap interface on ARM64 implements mapping functions where the Early Write Acknowledgment hint is enabled, so they cannot be used to map PCI configuration space in a PCI specs compliant way. Implement an ARM64 specific pci_remap_cfgspace() interface that allows to map PCI config region with nGnRnE attributes, providing a remap function that complies with PCI specifications and the ARMv8 architecture reference manual recommendations. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com>
| * | linux/io.h: Add pci_remap_cfgspace() interfaceLorenzo Pieralisi2017-04-191-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Current DT and ACPI host bridge controllers map PCI configuration space (ECAM and ECAM-derivative) into the virtual address space through ioremap() calls, that are non-cacheable device accesses on most architectures, but may provide "bufferable" or "posted" write semantics in architecture like eg ARM/ARM64 that allow ioremap'ed regions writes to be buffered in the bus connecting the host CPU to the PCI fabric; this behaviour, as underlined in the PCIe specifications, may trigger transactions ordering rules and must be prevented. Introduce a new generic and explicit API to create a memory mapping for ECAM and ECAM-derivative config space area that defaults to ioremap_nocache() (which should provide a sane default behaviour) but still allowing architectures on which ioremap_nocache() results in posted write transactions to override the function call with an arch specific implementation that complies with the PCI specifications for configuration transactions. [bhelgaas: fold in #ifdef CONFIG_PCI wrapper] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com>
| * | PCI: Remove __weak tag from pci_remap_iospace()Lorenzo Pieralisi2017-04-191-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | pci_remap_iospace() is marked as a weak symbol even though no architecture is currently overriding it; given that its implementation internals have already code paths that are arch specific (ie PCI_IOBASE and ioremap_page_range() attributes) there is no need to leave the weak symbol in the kernel since the same functionality can be achieved by customizing per-arch the corresponding functionality. Remove the __weak symbol from pci_remap_iospace(). Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* | Merge branch 'pci/iommu' into nextBjorn Helgaas2017-04-281-0/+2
|\ \ | | | | | | | | | | | | * pci/iommu: PCI: Add bridge DMA alias quirk for ITE 8893 bridge
| * | PCI: Add bridge DMA alias quirk for ITE 8893 bridgeJarod Wilson2017-04-121-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | The ITE 8893 bridge has the same problems as the ITE 8892, which were resulting in crippling an older PCI 1Gbps NIC down to 45Mbps throughput with IOMMU and VT-d enabled. With the patch, this old e1000 goes back up to ~900Mbps. Suggested-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
* | Merge branch 'pci/enumeration' into nextBjorn Helgaas2017-04-288-29/+100
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/enumeration: PCI: Include PCI-to-PCIe bridges as "Downstream Ports" PCI: Improve __pci_read_base() robustness PCI: Short-circuit pci_device_is_present() for disconnected devices PCI/MSI: Skip disabling disconnected devices PCI: Don't attempt config access to disconnected devices PCI: Add device disconnected state PCI: Export PCI device config accessors
| * | PCI: Include PCI-to-PCIe bridges as "Downstream Ports"Bjorn Helgaas2017-04-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A PCI/PCI-X to PCI Express bridge, sometimes referred to as a "reverse bridge", is a bridge with conventional PCI or PCI-X on its primary side and a PCI Express Port on its secondary (downstream) side. That PCIe Port is a Downstream Port and could be connected to a slot, just like a Root Port or a Switch Downstream Port. Make pcie_downstream_port() return true for them, so we can access the Slot registers in the PCIe capability. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Improve __pci_read_base() robustnessMarc Gonzalez2017-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Local variables 'l' and 'sz' are uninitialized. Normally, they would be initialized by pci_read_config_dword() but when an error occurs, some drivers immediately return an error code, which leaves the argument uninitialized. Provide a safe initial value to make the code more robust. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Short-circuit pci_device_is_present() for disconnected devicesKeith Busch2017-03-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the PCI device is disconnected, return false immediately from pci_device_is_present(). pci_device_is_present() uses the bus accessors, so the early return in the device accessors doesn't help here. Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Wei Zhang <wzhang@fb.com>
| * | PCI/MSI: Skip disabling disconnected devicesKeith Busch2017-03-301-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check the device connected state prior to executing device shutdown operations or writing MSI messages so that tear down on disconnected devices completes quicker. Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Wei Zhang <wzhang@fb.com>
| * | PCI: Don't attempt config access to disconnected devicesKeith Busch2017-03-301-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we've detected the PCI device is disconnected, there is no need to attempt to access its config space since we know the operation will fail. Make all the config reads and writes return -ENODEV error immediately when in such a state. If a caller requests a config read to a disconnected device, return a data value of all 1's. This is the same as what hardware is expected to return when accessing a removed device, but software can do this faster without relying on hardware. Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Wei Zhang <wzhang@fb.com>
| * | PCI: Add device disconnected stateKeith Busch2017-03-304-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new state to pci_dev to be set when it is unexpectedly disconnected. The PCI driver tear down functions can observe this new device state so they may skip operations that will fail. The pciehp and pcie-dpc drivers are aware when the link is down, so these set the flag when their handlers detect the device is disconnected. Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Wei Zhang <wzhang@fb.com>
| * | PCI: Export PCI device config accessorsKeith Busch2017-03-302-26/+44
| |/ | | | | | | | | | | | | | | | | | | | | Replace the inline PCI device config read and write accessors with exported functions. This is preparing for these functions to make use of private data. Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Wei Zhang <wzhang@fb.com>
* | Merge branch 'pci/switchtec' into nextBjorn Helgaas2017-04-2810-0/+1936
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/switchtec: switchtec: Add IOCTLs to the Switchtec driver switchtec: Add sysfs attributes to the Switchtec driver switchtec: Add user interface documentation MicroSemi Switchtec management interface driver Conflicts: drivers/pci/Kconfig
| * | switchtec: Add IOCTLs to the Switchtec driverLogan Gunthorpe2017-04-125-0/+642
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a couple of special IOCTLs to: * Inform userspace of firmware partition locations * Pass event counts and allow userspace to wait on events * Translate PFF numbers used by the switch to port numbers [Dan Carpenter <dan.carpenter@oracle.com>: fix off-by-one in ioctl_event_ctl()] Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Stephen Bates <stephen.bates@microsemi.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Wei Zhang <wzhang@fb.com> Reviewed-by: Jens Axboe <axboe@fb.com>
| * | switchtec: Add sysfs attributes to the Switchtec driverLogan Gunthorpe2017-04-123-0/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a few read-only sysfs attributes which provide some device information that is exposed from the devices, primarily component and device names and versions. These are documented in Documentation/ABI/testing/sysfs-class-switchtec. Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Stephen Bates <stephen.bates@microsemi.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Wei Zhang <wzhang@fb.com> Reviewed-by: Jens Axboe <axboe@fb.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | switchtec: Add user interface documentationLogan Gunthorpe2017-04-122-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add standard documentation for the sysfs switchtec attributes and a RST formatted text file which documents the char device interface. Jonathan Corbet has indicated he will move this to a new user-space developer documentation book once it's created. Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Stephen Bates <stephen.bates@microsemi.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Wei Zhang <wzhang@fb.com> Reviewed-by: Jens Axboe <axboe@fb.com>
| * | MicroSemi Switchtec management interface driverLogan Gunthorpe2017-03-076-0/+1030
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microsemi's "Switchtec" line of PCI switch devices is already well supported by the kernel with standard PCI switch drivers. However, the Switchtec device advertises a special management endpoint with a separate PCI function address and class code. This endpoint enables some additional functionality which includes: * Packet and Byte Counters * Switch Firmware Upgrades * Event and Error logs * Querying port link status * Custom user firmware commands Add a switchtec kernel module which provides PCI driver that exposes a char device. The char device provides userspace access to this interface through read, write and (optionally) poll calls. A userspace tool and library which utilizes this interface is available at [1]. This tool takes inspiration (and borrows some code) from nvme-cli [2]. The tool is largely complete at this time but additional features may be added in the future. [1] https://github.com/sbates130272/switchtec-user [2] https://github.com/linux-nvme/nvme-cli [Dan Carpenter <dan.carpenter@oracle.com>: don't invert error codes] [Christophe JAILLET <christophe.jaillet@wanadoo.fr>: fix switchtec_dev_open() error handling] Tested-by: Krishna Dhulipala <krishnad@fb.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Stephen Bates <stephen.bates@microsemi.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Wei Zhang <wzhang@fb.com> Reviewed-by: Jens Axboe <axboe@fb.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | Merge branch 'pci/host-thunder' into nextBjorn Helgaas2017-04-284-3/+34
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-thunder: PCI/ACPI: Add ThunderX pass2.x 2nd node MCFG quirk PCI/ACPI: Tidy up MCFG quirk whitespace PCI: Avoid generating invalid ThunderX2 DMA aliases PCI: Add device flag PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT PCI: Apply Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices
| * | PCI/ACPI: Add ThunderX pass2.x 2nd node MCFG quirkTomasz Nowicki2017-04-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently SoCs pass2.x do not emulate EA headers for ACPI boot method at all. However, for pass2.x some devices (like EDAC) advertise incorrect base addresses in their BARs which results in driver probe failure during resource request. Since all problematic blocks are on 2nd NUMA node under domain 10 add necessary quirk entry to obtain BAR addresses correction using EA header emulation. Fixes: 44f22bd91e88 ("PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller") Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Robert Richter <rrichter@cavium.com> CC: stable@vger.kernel.org # v4.10+
| * | PCI/ACPI: Tidy up MCFG quirk whitespaceBjorn Helgaas2017-04-211-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | With no blank lines, it's not obvious where the macro definitions end and the uses begin. Add some blank lines and reorder the ThunderX definitions. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.10+
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