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* Merge branch 'pci/virtualization' into nextBjorn Helgaas2017-04-2813-86/+134
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/virtualization: ixgbe: Use pcie_flr() instead of duplicating it IB/hfi1: Use pcie_flr() instead of duplicating it PCI: Call pcie_flr() from reset_chelsio_generic_dev() PCI: Call pcie_flr() from reset_intel_82599_sfp_virtfn() PCI: Export pcie_flr() PCI: Add sysfs sriov_drivers_autoprobe to control VF driver binding PCI: Avoid FLR for Intel 82579 NICs Conflicts: include/linux/pci.h
| * ixgbe: Use pcie_flr() instead of duplicating itChristoph Hellwig2017-04-271-14/+2Star
| | | | | | | | | | Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * IB/hfi1: Use pcie_flr() instead of duplicating itChristoph Hellwig2017-04-253-33/+2Star
| | | | | | | | | | | | | | Tested-by: Jakub Byczkowski <jakub.byczkowski@intel.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Doug Ledford <dledford@redhat.com>
| * PCI: Call pcie_flr() from reset_chelsio_generic_dev()Christoph Hellwig2017-04-201-14/+1Star
| | | | | | | | | | | | Instead of copy & pasting and old version of the code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: Call pcie_flr() from reset_intel_82599_sfp_virtfn()Christoph Hellwig2017-04-201-12/+4Star
| | | | | | | | | | | | The 82599 quirk contained an outdated copy of the FLR code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: Export pcie_flr()Christoph Hellwig2017-04-202-11/+29
| | | | | | | | | | | | | | | | | | | | | | | | Currently we opencode the FLR sequence in lots of place; export a core helper instead. We split out the probing for FLR support as all the non-core callers already know their hardware. Note that in the new pci_has_flr() function the quirk check has been moved before the capability check as there is no point in reading the capability in this case. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: Add sysfs sriov_drivers_autoprobe to control VF driver bindingBodong Wang2017-04-206-4/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes it is not desirable to bind SR-IOV VFs to drivers. This can save host side resource usage by VF instances that will be assigned to VMs. Add a new PCI sysfs interface "sriov_drivers_autoprobe" to control that from the PF. To modify it, echo 0/n/N (disable probe) or 1/y/Y (enable probe) to: /sys/bus/pci/devices/<DOMAIN:BUS:DEVICE.FUNCTION>/sriov_drivers_autoprobe Note that this must be done before enabling VFs. The change will not take effect if VFs are already enabled. Simply, one can disable VFs by setting sriov_numvfs to 0, choose whether to probe or not, and then re-enable the VFs by restoring sriov_numvfs. [bhelgaas: changelog, ABI doc] Signed-off-by: Bodong Wang <bodong@mellanox.com> Signed-off-by: Eli Cohen <eli@mellanox.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
| * PCI: Avoid FLR for Intel 82579 NICsSasha Neftin2017-04-033-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per Intel Specification Update 335553-002 (see link below), some 82579 network adapters advertise a Function Level Reset (FLR) capability, but they can hang when an FLR is triggered. To reproduce the problem, attach the device to a VM, then detach and try to attach again. Add a quirk to prevent the use of FLR on these devices. [bhelgaas: changelog, comments] Link: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/82579lm-82579v-gigabit-network-connection-spec-update.pdf Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/resource-mmap' into nextBjorn Helgaas2017-04-2834-385/+238Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/resource-mmap: ia64: Use generic pci_mmap_resource_range() ia64: Remove redundant checks for WC in pci_mmap_page_range() ia64: Remove redundant valid_mmap_phys_addr_range() from pci_mmap_page_range() PCI: Add I/O BAR support to generic pci_mmap_resource_range() x86/PCI: Use generic pci_mmap_resource_range() unicore32/PCI: Use generic pci_mmap_resource_range() sh/PCI: Use generic pci_mmap_resource_range() parisc: Use generic pci_mmap_resource_range() mn10300/PCI: Use generic pci_mmap_resource_range() MIPS: PCI: Use generic pci_mmap_resource_range() cris/PCI: Use generic pci_mmap_resource_range() ARM/PCI: Use generic pci_mmap_resource_range() PCI: Add pci_mmap_resource_range() and use it for ARM64 PCI: Add BAR index argument to pci_mmap_page_range() PCI: Use BAR index in sysfs attr->private instead of resource pointer PCI: Add arch_can_pci_mmap_io() on architectures which can mmap() I/O space PCI: Move multiple declarations of pci_mmap_page_range() to <linux/pci.h> PCI: Add arch_can_pci_mmap_wc() macro xtensa/PCI: Do not mmap PCI BARs to userspace as write-through PCI: Only allow WC mmap on prefetchable resources PCI: Fix another sanity check bug in /proc/pci mmap PCI: Fix pci_mmap_fits() for HAVE_PCI_RESOURCE_TO_USER platforms
| * | ia64: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-30/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | Now that we eliminated the different behaviour in separately-reviewable commits, we can switch IA64 to the generic implementation. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Tested-by: Tony Luck <tony.luck@intel.com>
| * | ia64: Remove redundant checks for WC in pci_mmap_page_range()David Woodhouse2017-04-201-16/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | For a PCI MMIO BAR, phys_mem_access_prot() should always return UC or WC. And while a mixture of cached and uncached mappings is forbidden, we were already mixing WC and UC, which is OK. Just do as we're asked. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Tested-by: Tony Luck <tony.luck@intel.com>
| * | ia64: Remove redundant valid_mmap_phys_addr_range() from pci_mmap_page_range()David Woodhouse2017-04-201-3/+0Star
| | | | | | | | | | | | | | | | | | | | | We know we are within a valid MMIO BAR by the time this function gets called; there's no need to check. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Tested-by: Tony Luck <tony.luck@intel.com>
| * | PCI: Add I/O BAR support to generic pci_mmap_resource_range()David Woodhouse2017-04-202-4/+12
| | | | | | | | | | | | | | | | | | This will need to call into an arch-provided pci_iobar_pfn() function. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | x86/PCI: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-48/+1Star
| | | | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | unicore32/PCI: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-24/+1Star
| | | | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | sh/PCI: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-22/+1Star
| | | | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | parisc: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-29/+1Star
| | | | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | mn10300/PCI: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-24/+1Star
| | | | | | | | | | | | | | | | | | | | | This was setting vma->vm_flags |= VM_LOCKED. Not sure why... Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: David Howells <dhowells@redhat.com>
| * | MIPS: PCI: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-26/+1Star
| | | | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | cris/PCI: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-23/+1Star
| | | | | | | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
| * | ARM/PCI: Use generic pci_mmap_resource_range()David Woodhouse2017-04-202-20/+1Star
| | | | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add pci_mmap_resource_range() and use it for ARM64David Woodhouse2017-04-207-20/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting to leave behind the legacy of the pci_mmap_page_range() interface which takes "user-visible" BAR addresses. This takes just the resource and offset. For now, both APIs coexist and depending on the platform, one is implemented as a wrapper around the other. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add BAR index argument to pci_mmap_page_range()David Woodhouse2017-04-2016-18/+30
| | | | | | | | | | | | | | | | | | | | | In all cases we know which BAR it is. Passing it in means that arch code (or generic code; watch this space) won't have to go looking for it again. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Use BAR index in sysfs attr->private instead of resource pointerDavid Woodhouse2017-04-201-24/+14Star
| | | | | | | | | | | | | | | | | | | | | We store the pointer, and then on *every* use of it we loop over the device's resources to find out the index. That's kind of silly. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add arch_can_pci_mmap_io() on architectures which can mmap() I/O spaceDavid Woodhouse2017-04-188-12/+26
| | | | | | | | | | | | | | | | | | | | | | | | This is relatively esoteric, and knowing that we don't have it makes life easier in some cases rather than just an eventual -EINVAL from pci_mmap_page_range(). Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Move multiple declarations of pci_mmap_page_range() to <linux/pci.h>David Woodhouse2017-04-1814-38/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | We can declare it <linux/pci.h> even on platforms where it isn't going to be defined. There's no need to have it littered through the various <asm/pci.h> files. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add arch_can_pci_mmap_wc() macroDavid Woodhouse2017-04-187-11/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the almost-identical versions of pci_mmap_page_range() silently ignore the 'write_combine' argument and give uncached mappings. Yet we allow the PCIIOC_WRITE_COMBINE ioctl in /proc/bus/pci, expose the 'resourceX_wc' file in sysfs, and allow an attempted mapping to apparently succeed. To fix this, introduce a macro arch_can_pci_mmap_wc() which indicates whether the platform can do a write-combining mapping. On x86 this ends up being pat_enabled(), while the few other platforms that support it can just set it to a literal '1'. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | xtensa/PCI: Do not mmap PCI BARs to userspace as write-throughDavid Woodhouse2017-04-181-20/+1Star
| | | | | | | | | | | | | | | | | | These should be uncached, not write-through. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Only allow WC mmap on prefetchable resourcesDavid Woodhouse2017-04-181-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | The /proc/bus/pci mmap interface allows the user to specify whether they want WC or not. Don't let them do so on non-prefetchable BARs. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
| * | PCI: Fix another sanity check bug in /proc/pci mmapDavid Woodhouse2017-04-181-2/+8
| | | | | | | | | | | | | | | | | | | | | Don't match MMIO maps with I/O BARs and vice versa. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
| * | PCI: Fix pci_mmap_fits() for HAVE_PCI_RESOURCE_TO_USER platformsDavid Woodhouse2017-04-121-3/+7
| |/ | | | | | | | | | | | | | | | | In the PCI_MMAP_PROCFS case when the address being passed by the user is a 'user visible' resource address based on the bus window, and not the actual contents of the resource, that's what we need to be checking it against. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
* | Merge branch 'pci/resource' into nextBjorn Helgaas2017-04-288-31/+104
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/resource: PCI: Don't resize resources when realigning all devices in system PCI: Don't reassign resources that are already aligned PCI: Factor pci_reassigndev_resource_alignment() powerpc/powernv: Override pcibios_default_alignment() to force PCI devices to be page aligned PCI: Add pcibios_default_alignment() for arch-specific alignment control PCI: Fix calculation of bridge window's size and alignment PCI: Ignore requested alignment for IOV BARs PCI: Make PCI_ROM_ADDRESS_MASK a 32-bit constant
| * | PCI: Don't resize resources when realigning all devices in systemYongji Xie2017-04-191-16/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "pci=resource_alignment" argument aligns BARs of designated devices by artificially increasing their size. Increasing the size increases the alignment and prevents other resources from being assigned in the same alignment region, e.g., in the same page, but it can break drivers that use the BAR size to locate things, e.g., ilo_map_device() does this: off = pci_resource_len(pdev, bar) - 0x2000; The new pcibios_default_alignment() interface allows an arch to request that *all* BARs in the system be aligned to a larger size. In this case, we don't need to artificially increase the resource size because we know every BAR of every device will be realigned, so nothing will share the same alignment region. Use IORESOURCE_STARTALIGN to request realignment of PCI BARs when we know we're realigning all BARs in the system. [bhelgaas: comment, changelog] Signed-off-by: Yongji Xie <elohimes@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Don't reassign resources that are already alignedBjorn Helgaas2017-04-191-21/+19Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "pci=resource_alignment=" kernel argument designates devices for which we want alignment greater than is required by the PCI specs. Previously we set IORESOURCE_UNSET for every MEM resource of those devices, even if the resource was *already* sufficiently aligned. If a resource is already sufficiently aligned, leave it alone and don't try to reassign it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Factor pci_reassigndev_resource_alignment()Bjorn Helgaas2017-04-191-22/+47
| | | | | | | | | | | | | | | | | | | | | Pull the BAR size adjustment out into a new function, pci_request_resource_alignment(), and add a comment about how and why we increase the resource size and alignment. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | powerpc/powernv: Override pcibios_default_alignment() to force PCI devices ↵Yongji Xie2017-04-193-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to be page aligned Override pcibios_default_alignment() to set default alignment to PAGE_SIZE for all PCI devices on PowerNV platform. Thus sub-page BARs would not share a page and could be mapped into guest when VFIO passthrough them. Signed-off-by: Yongji Xie <elohimes@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add pcibios_default_alignment() for arch-specific alignment controlYongji Xie2017-04-191-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When VFIO passes through a PCI device to a guest, it does not allow the guest to mmap BARs that are smaller than PAGE_SIZE unless it can reserve the rest of the page (see vfio_pci_probe_mmaps()). This is because a page might contain several small BARs for unrelated devices and a guest should not be able to access all of them. VFIO emulates guest accesses to non-mappable BARs, which is functional but slow. On systems with large page sizes, e.g., PowerNV with 64K pages, BARs are more likely to share a page and performance is more likely to be a problem. Add a weak function to set default alignment for all PCI devices. An arch can override it to force the PCI core to place memory BARs on their own pages. Signed-off-by: Yongji Xie <elohimes@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Fix calculation of bridge window's size and alignmentYongji Xie2017-04-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | In case that one device's alignment is greater than its size, we may get an incorrect size and alignment for its bus's memory window in pbus_size_mem(). Fix this case. Signed-off-by: Yongji Xie <elohimes@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Ignore requested alignment for IOV BARsYongji Xie2017-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We would call pci_reassigndev_resource_alignment() before pci_init_capabilities(). So the requested alignment would never work for IOV BARs. Furthermore, it's meaningless to request additional alignment for IOV BARs, the IOV BAR alignment is only determined by the VF BAR size. Signed-off-by: Yongji Xie <xyjxie@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
| * | PCI: Make PCI_ROM_ADDRESS_MASK a 32-bit constantMatthias Kaehlcke2017-04-183-3/+3
| |/ | | | | | | | | | | | | | | | | | | | | A 64-bit value is not needed since a PCI ROM address consists in 32 bits. This fixes a clang warning about "implicit conversion from 'unsigned long' to 'u32'". Also remove now unnecessary casts to u32 from __pci_read_base() and pci_std_update_resource(). Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/pm' into nextBjorn Helgaas2017-04-281-6/+9
|\ \ | | | | | | | | | | | | | | | * pci/pm: PCI: Freeze PME scan before suspending devices PCI/PM: Don't sleep at all when d3_delay or d3cold_delay is zero
| * | PCI: Freeze PME scan before suspending devicesLukas Wunner2017-04-181-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Laurent Pinchart reported that the Renesas R-Car H2 Lager board (r8a7790) crashes during suspend tests. Geert Uytterhoeven managed to reproduce the issue on an M2-W Koelsch board (r8a7791): It occurs when the PME scan runs, once per second. During PME scan, the PCI host bridge (rcar-pci) registers are accessed while its module clock has already been disabled, leading to the crash. One reproducer is to configure s2ram to use "s2idle" instead of "deep" suspend: # echo 0 > /sys/module/printk/parameters/console_suspend # echo s2idle > /sys/power/mem_sleep # echo mem > /sys/power/state Another reproducer is to write either "platform" or "processors" to /sys/power/pm_test. It does not (or is less likely) to happen during full system suspend ("core" or "none") because system suspend also disables timers, and thus the workqueue handling PME scans no longer runs. Geert believes the issue may still happen in the small window between disabling module clocks and disabling timers: # echo 0 > /sys/module/printk/parameters/console_suspend # echo platform > /sys/power/pm_test # Or "processors" # echo mem > /sys/power/state (Make sure CONFIG_PCI_RCAR_GEN2 and CONFIG_USB_OHCI_HCD_PCI are enabled.) Rafael Wysocki agrees that PME scans should be suspended before the host bridge registers become inaccessible. To that end, queue the task on a workqueue that gets frozen before devices suspend. Rafael notes however that as a result, some wakeup events may be missed if they are delivered via PME from a device without working IRQ (which hence must be polled) and occur after the workqueue has been frozen. If that turns out to be an issue in practice, it may be possible to solve it by calling pci_pme_list_scan() once directly from one of the host bridge's pm_ops callbacks. Stacktrace for posterity: PM: Syncing filesystems ... [ 38.566237] done. PM: Preparing system for sleep (mem) Freezing user space processes ... [ 38.579813] (elapsed 0.001 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. PM: Suspending system (mem) PM: suspend of devices complete after 152.456 msecs PM: late suspend of devices complete after 2.809 msecs PM: noirq suspend of devices complete after 29.863 msecs suspend debug: Waiting for 5 second(s). Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 pgd = c0003000 [00000000] *pgd=80000040004003, *pmd=00000000 Internal error: : 1211 [#1] SMP ARM Modules linked in: CPU: 1 PID: 20 Comm: kworker/1:1 Not tainted 4.9.0-rc1-koelsch-00011-g68db9bc814362e7f #3383 Hardware name: Generic R8A7791 (Flattened Device Tree) Workqueue: events pci_pme_list_scan task: eb56e140 task.stack: eb58e000 PC is at pci_generic_config_read+0x64/0x6c LR is at rcar_pci_cfg_base+0x64/0x84 pc : [<c041d7b4>] lr : [<c04309a0>] psr: 600d0093 sp : eb58fe98 ip : c041d750 fp : 00000008 r10: c0e2283c r9 : 00000000 r8 : 600d0013 r7 : 00000008 r6 : eb58fed6 r5 : 00000002 r4 : eb58feb4 r3 : 00000000 r2 : 00000044 r1 : 00000008 r0 : 00000000 Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user Control: 30c5387d Table: 6a9f6c80 DAC: 55555555 Process kworker/1:1 (pid: 20, stack limit = 0xeb58e210) Stack: (0xeb58fe98 to 0xeb590000) fe80: 00000002 00000044 fea0: eb6f5800 c041d9b0 eb58feb4 00000008 00000044 00000000 eb78a000 eb78a000 fec0: 00000044 00000000 eb9aff00 c0424bf0 eb78a000 00000000 eb78a000 c0e22830 fee0: ea8a6fc0 c0424c5c eaae79c0 c0424ce0 eb55f380 c0e22838 eb9a9800 c0235fbc ff00: eb55f380 c0e22838 eb55f380 eb9a9800 eb9a9800 eb58e000 eb9a9824 c0e02100 ff20: eb55f398 c02366c4 eb56e140 eb5631c0 00000000 eb55f380 c023641c 00000000 ff40: 00000000 00000000 00000000 c023a928 cd105598 00000000 40506a34 eb55f380 ff60: 00000000 00000000 dead4ead ffffffff ffffffff eb58ff74 eb58ff74 00000000 ff80: 00000000 dead4ead ffffffff ffffffff eb58ff90 eb58ff90 eb58ffac eb5631c0 ffa0: c023a844 00000000 00000000 c0206d68 00000000 00000000 00000000 00000000 ffc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ffe0: 00000000 00000000 00000000 00000000 00000013 00000000 3a81336c 10ccd1dd [<c041d7b4>] (pci_generic_config_read) from [<c041d9b0>] (pci_bus_read_config_word+0x58/0x80) [<c041d9b0>] (pci_bus_read_config_word) from [<c0424bf0>] (pci_check_pme_status+0x34/0x78) [<c0424bf0>] (pci_check_pme_status) from [<c0424c5c>] (pci_pme_wakeup+0x28/0x54) [<c0424c5c>] (pci_pme_wakeup) from [<c0424ce0>] (pci_pme_list_scan+0x58/0xb4) [<c0424ce0>] (pci_pme_list_scan) from [<c0235fbc>] (process_one_work+0x1bc/0x308) [<c0235fbc>] (process_one_work) from [<c02366c4>] (worker_thread+0x2a8/0x3e0) [<c02366c4>] (worker_thread) from [<c023a928>] (kthread+0xe4/0xfc) [<c023a928>] (kthread) from [<c0206d68>] (ret_from_fork+0x14/0x2c) Code: ea000000 e5903000 f57ff04f e3a00000 (e5843000) ---[ end trace 667d43ba3aa9e589 ]--- Fixes: df17e62e5bff ("PCI: Add support for polling PME state on suspended legacy PCI devices") Reported-and-tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reported-and-tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: stable@vger.kernel.org # 2.6.37+ Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Cc: Simon Horman <horms+renesas@verge.net.au> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Matthew Garrett <mjg59@srcf.ucam.org>
| * | PCI/PM: Don't sleep at all when d3_delay or d3cold_delay is zeroAdrian Hunter2017-03-141-2/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | msleep() still sleeps 1 jiffy even when told to sleep for zero milliseconds. That can end up being 1-2 milliseconds or more. In the cases of d3_delay and d3cold_delay, that unnecessarily increases suspend and/or resume latencies. Do not sleep at all for the respective cases if d3_delay is zero or d3cold_delay is zero. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | Merge branch 'pci/msi' into nextBjorn Helgaas2017-04-287-189/+73Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/msi: PCI/MSI: Use dev_printk() when possible of/pci: Remove unused MSI controller helpers PCI: mvebu: Remove useless MSI enabling code PCI: aardvark: Move to MSI handling using generic MSI support PCI/MSI: Make pci_msi_shutdown() and pci_msix_shutdown() static PCI/MSI: Stop disabling MSI/MSI-X in pci_device_shutdown()
| * | PCI/MSI: Use dev_printk() when possibleBjorn Helgaas2017-03-231-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use dev_printk() when possible. This makes messages more consistent with other device-related messages and, in some cases, adds useful information. This changes messages like this: Unable to allocate affinity masks, ignoring to this: pci 0000:01:00.0: can't allocate MSI affinity masks for 4 vectors Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | of/pci: Remove unused MSI controller helpersThomas Petazzoni2017-03-142-56/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All users of the small MSI controller API have been migrated to use the generic MSI infrastructure instead. We no longer need a global chained list of msi_controller. Instead, MSI controllers are now represented as IRQ domains attached to OF nodes, and the resolution between a device requesting an MSI and the corresponding MSI controller is done by the generic interrupt resolution logic. Therefore, this API is now completely useless, and can be removed from the kernel. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org>
| * | PCI: mvebu: Remove useless MSI enabling codeThomas Petazzoni2017-03-141-17/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit fcc392d501bd2 ("irqchip/armada-370-xp: Use the generic MSI infrastructure"), the irqchip driver used on Armada 370, XP, 375, 38x, 39x for the MPIC interrupt controller has been converted to use the generic MSI infrastructure. Since this commit, it is no longer registering an msi_controller structure with the of_pci_msi_chip_add() function. Therefore, having the PCI driver used on the same platform calling of_pci_find_msi_chip_by_node() is pretty useless. The MSI resolution is now done in the generic interrupt resolution code, since the MSI controller is an irq domain attached to the interrupt controller node, which is pointed to by the msi-parent DT property in the PCIe controller node. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
| * | PCI: aardvark: Move to MSI handling using generic MSI supportThomas Petazzoni2017-03-141-106/+67Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MSI support introduced with the initial Aardvark driver was based on the msi_controller structure and the of_pci_msi_chip_add() / of_pci_find_msi_chip_by_node() API, which are being deprecated in favor of the generic MSI support. Update the Aardvark driver to use the generic MSI support. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
| * | PCI/MSI: Make pci_msi_shutdown() and pci_msix_shutdown() staticBjorn Helgaas2017-03-092-6/+2Star
| | | | | | | | | | | | | | | | | | pci_msi_shutdown() and pci_msix_shutdown() are used only in drivers/pci/msi.c, so make them static. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/MSI: Stop disabling MSI/MSI-X in pci_device_shutdown()Prarit Bhargava2017-03-091-2/+0Star
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_bus_type .shutdown method, pci_device_shutdown(), is called from device_shutdown() in the kernel restart and shutdown paths. Previously, pci_device_shutdown() called pci_msi_shutdown() and pci_msix_shutdown(). This disables MSI and MSI-X, which causes the device to fall back to raising interrupts via INTx. But the driver is still bound to the device, it doesn't know about this change, and it likely doesn't have an INTx handler, so these INTx interrupts cause "nobody cared" warnings like this: irq 16: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.8.2-1.el7_UNSUPPORTED.x86_64 #1 Hardware name: Hewlett-Packard HP Z820 Workstation/158B, BIOS J63 v03.90 06/ ... The MSI disabling code was added by d52877c7b1af ("pci/irq: let pci_device_shutdown to call pci_msi_shutdown v2") because a driver left MSI enabled and kdump failed because the kexeced kernel wasn't prepared to receive the MSI interrupts. Subsequent commits 1851617cd2da ("PCI/MSI: Disable MSI at enumeration even if kernel doesn't support MSI") and e80e7edc55ba ("PCI/MSI: Initialize MSI capability for all architectures") changed the kexeced kernel to disable all MSIs itself so it no longer depends on the crashed kernel to clean up after itself. Stop disabling MSI/MSI-X in pci_device_shutdown(). This resolves the "nobody cared" unhandled IRQ issue above. It also allows PCI serial devices, which may rely on the MSI interrupts, to continue outputting messages during reboot/shutdown. [bhelgaas: changelog, drop pci_msi_shutdown() and pci_msix_shutdown() calls altogether] Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=187351 Signed-off-by: Prarit Bhargava <prarit@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Alex Williamson <alex.williamson@redhat.com> CC: David Arcari <darcari@redhat.com> CC: Myron Stowe <mstowe@redhat.com> CC: Lukas Wunner <lukas@wunner.de> CC: Keith Busch <keith.busch@intel.com> CC: Mika Westerberg <mika.westerberg@linux.intel.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-08 03:42:30 +0200