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* ARC: Support for single cycle Close Coupled Mem (CCM)Vineet Gupta2013-02-151-3/+2Star
| | | | | | | | | * Includes mapping of CCMs in address space * Annotations to move arbitrary code/data into CCM * Moving some of the critical code/data into CCM * Runtime detection/reporting Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Boot #2: Verbose Boot reporting / feature verificationVineet Gupta2013-02-152-0/+84
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: SMP supportVineet Gupta2013-02-152-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARC common code to enable a SMP system + ISS provided SMP extensions. ARC700 natively lacks SMP support, hence some of the core features are are only enabled if SoCs have the necessary h/w pixie-dust. This includes: -Inter Processor Interrupts (IPI) -Cache coherency -load-locked/store-conditional ... The low level exception handling would be completely broken in SMP because we don't have hardware assisted stack switching. Thus a fair bit of this code is repurposing the MMU_SCRATCH reg for event handler prologues to keep them re-entrant. Many thanks to Rajeshwar Ranga for his initial "major" contributions to SMP Port (back in 2008), and to Noam Camus and Gilad Ben-Yossef for help with resurrecting that in 3.2 kernel (2012). Note that this platform code is again singleton design pattern - so multiple SMP platforms won't build at the moment - this deficiency is addressed in subsequent patches within this series. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rajeshwar Ranga <rajeshwar.ranga@gmail.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Gilad Ben-Yossef <gilad@benyossef.com>
* ARC: Diagnostics: show_regs() etcVineet Gupta2013-02-151-0/+20
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: [DeviceTree] Convert some Kconfig items to runtime valuesVineet Gupta2013-02-151-3/+6
| | | | | | | | | * mem size now runtime configured (prev CONFIG_ARC_PLAT_SDRAM_SIZE) * core cpu clk runtime configured (prev CONFIG_ARC_PLAT_CLK) Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@secretlab.ca>
* ARC: [DeviceTree] Basic supportVineet Gupta2013-02-151-0/+13
| | | | | | | | | | | | | | | | | | | | This is minimal infrastructure needed for devicetree work. It uses an a sample "skeleton" devicetree - embedded in kernel image - to print the board, manufacturer by parsing the top-level "compatible" string. As of now we don't need any additional "board" specific "machine_desc". TODO: support interpreting the command line as boot-loader passed dtb Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring <rob.herring@calxeda.com> Cc: James Hogan <james.hogan@imgtec.com> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: James Hogan <james.hogan@imgtec.com>
* ARC: Boot #1: low-level, setup_arch(), /proc/cpuinfo, mem initVineet Gupta2013-02-151-0/+171
| | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARC: I/O and DMA MappingsVineet Gupta2013-02-152-0/+161
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Page Fault handlingVineet Gupta2013-02-151-0/+228
| | | | | | | | | | | | | | This includes recent changes to make handler "retry" and/or "killable" The killable (early exit) logic is loosely based on how SH implements it return if SIGKILL + either of VM_FAULT_OOM or VM_FAULT_RETRY which is different from Hexagon implementation which would NOT early exit for SIGKILL + VM_FAULT_OOM + !VM_FAULT_RETRY credits: Non executable stack support from Simon Spooner Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: TLB flush HandlingVineet Gupta2013-02-151-0/+311
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: MMU Exception HandlingVineet Gupta2013-02-152-0/+618
| | | | | | | | | * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: MMU Context ManagementVineet Gupta2013-02-151-0/+23
| | | | | | | | | | | | ARC700 MMU provides for tagging TLB entries with a 8-bit ASID to avoid having to flush the TLB every task switch. It also allows for a quick way to invalidate all the TLB entries for task useful for: * COW sementics during fork() * task exit()ing Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Cache Flush ManagementVineet Gupta2013-02-151-0/+725
| | | | | | | | | * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: uaccess friendsVineet Gupta2013-02-111-0/+63
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Build system: Makefiles, Kconfig, Linker scriptVineet Gupta2013-02-111-0/+10
Arnd in his review pointed out that arch Kconfig organisation has several deficiencies: * Build time entries for things which can be runtime extracted from DT (e.g. SDRAM size, core clk frequency..) * Not multi-platform-image-build friendly (choice .. endchoice constructs) * cpu variants support (750/770) is exclusive. The first 2 have been fixed in subsequent patches. Due to the nature of the 750 and 770, it is not possible to build for both together, w/o special runtime glue code which would hurt performance. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Sam Ravnborg <sam@ravnborg.org> Acked-by: Sam Ravnborg <sam@ravnborg.org>
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