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| * | ARC: [tlb-miss] Fix bug with CONFIG_ARC_DBG_TLB_MISS_COUNTVineet Gupta2013-06-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LOAD_FAULT_PTE macro is expected to set r2 with faulting vaddr. However in case of CONFIG_ARC_DBG_TLB_MISS_COUNT, it was getting clobbered with statistics collection code. Fix latter by using a different register. Note that only I-TLB Miss handler was potentially affected. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [tlb-miss] Extraneous PTE bit testing/settingVineet Gupta2013-06-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * No need to check for READ access in I-TLB Miss handler * Redundant PAGE_PRESENT update in PTE Post TLB entry installation, in updating PTE for software accessed/dity bits, no need to update PAGE_PRESENT since it will already be set. Infact the entry won't have installed if !PAGE_PRESENT. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Adjustments for gcc 4.8Vineet Gupta2013-06-275-19/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * DWARF unwinder related + Force DWARF2 compliant .debug_frame (gcc 4.8 defaults to DWARF4 which kernel unwinder can't grok). + Discard the additional .eh_frame generated + Discard the dwarf4 debug info generated by -gdwarf-2 for normal no debug case * 4.8 already uses arc600 multilibs for -mno-mpy * switch to using uclibc compiler (to get -mmedium-calls and -mno-sdata) and also since buildroot can only use 1 toolchain Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Setup Vector Table Base in early bootVineet Gupta2013-06-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Otherwise early boot exceptions such as instructions errors due to configuration mismatch between kernel and hardware go off to la-la land, as opposed to hitting the handler and panic()'ing properly. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Remove explicit passing around of ECRVineet Gupta2013-06-2613-78/+59Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With ECR now part of pt_regs * No need to propagate from lowest asm handlers as arg * No need to save it in tsk->thread.cause_code * Avoid bit chopping to access the bit-fields More code consolidation, cleanup Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth valuesVineet Gupta2013-06-268-57/+53Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pt_regs->event was set with artificial values to identify the low level system event (syscall trap / breakpoint trap / exceptions / interrupts) With r8 saving out of the way, the full word can be used to save real ECR (Exception Cause Register) which helps idenify the event naturally, including additional info such as cause code, param. Only for Interrupts, where ECR is not applicable, do we resort to synthetic non ECR values. SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with different runtime values. The ptrace helpers now use the sub-fields of ECR to distinguish the events (e.g. vector 0x25 is trap, param 0 is syscall...) The following benefits will follow: (1) This centralizes the location of where ECR is saved and will allow the cleanup of task->thread.cause_code ECR placeholder which is set in non-uniform way. Then ARC VM code can safely rely on it being there for purpose of finer grained VM_EXEC dcache flush (based on exec fault: I-TLB Miss) (2) Further, ECR being passed around from low level handlers as arg can be eliminated as it is part of standard reg-file in pt_regs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: stop using pt_regs->orig_r8Vineet Gupta2013-06-223-16/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, pt_regs have had orig_r8, an overloaded container for (1) backup copy of r8 (syscall number Trap Exceptions) (2) additional system state: (syscall/Exception/Interrupt) There is no point in keeping (1) since syscall number is never clobbered in-place, in pt_regs, unlike r0 which duals as first syscall arg as well as syscall return value and in case of syscall restart, the orig arg0 needs restoring (from orig_r0) after having been updated in-place with syscall ret value. This further paves way to convert (2) to contain ECR itself (rather than current madeup values) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: pt_regs update #4: r25 saved/restored unconditionallyVineet Gupta2013-06-226-40/+24Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (This is a VERY IMP change for low level interrupt/exception handling) ----------------------------------------------------------------------- WHAT ----------------------------------------------------------------------- * User 25 now saved in pt_regs->user_r25 (vs. tsk->thread_info.user_r25) * This allows Low level interrupt code to unconditionally save r25 (vs. the prev version which would only do it for U->K transition). Ofcourse for nested interrupts, only the pt_regs->user_r25 of bottom-most frame is useful. * simplifies the interrupt prologue/epilogue * Needed for ARCv2 ISA code and done here to keep design similar with ARCompact event handling ----------------------------------------------------------------------- WHY ------------------------------------------------------------------------- With CONFIG_ARC_CURR_IN_REG, r25 is used to cache "current" task pointer in kernel mode. So when entering kernel mode from User Mode - user r25 is specially safe-kept (it being a callee reg is NOT part of pt_regs which are saved by default on each interrupt/trap/exception) - r25 loaded with current task pointer. Further, if interrupt was taken in kernel mode, this is skipped since we know that r25 already has valid "current" pointer. With 2 level of interrupts in ARCompact ISA, detecting this is difficult but still possible, since we could be in kernel mode but r25 not already saved (in fact the stack itself might not have been switched). A. User mode B. L1 IRQ taken C. L2 IRQ taken (while on 1st line of L1 ISR) So in #C, although in kernel mode, r25 not saved (infact SP not switched at all) Given that ARcompact has manual stack switching, we could use a bit of trickey - The low level code would make sure that SP is only set to kernel mode value at the very end (after saving r25). So a non kernel mode SP, even if in kernel mode, meant r25 was NOT saved. The same paradigm won't work in ARCv2 ISA since SP is auto-switched so it's setting can't be delayed/constrained. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: K/U SP saved from one location in stack switching macroVineet Gupta2013-06-221-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This paves way for further simplifications. There's an overhead of 1 insn for the non-common case of interrupt taken from kernel mode. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Entry Handler tweaks: Simplify branch for in-kernel preemptionVineet Gupta2013-06-221-6/+2Star
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR valuesVineet Gupta2013-06-222-6/+14
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Increase readability of entry handlersVineet Gupta2013-06-222-212/+186Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | * use artificial PUSH/POP contructs for CORE Reg save/restore to stack * use artificial PUSHAX/POPAX contructs for Auxiliary Space regs * macro'ize multiple copies of callee-reg-save/restore (SAVE_R13_TO_R24) * use BIC insn for inverse-and operation Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: pt_regs update #3: Remove unused gutter at start of callee_regsVineet Gupta2013-06-229-31/+24Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is trickier than prev two: * context switching code saves kernel mode callee regs in the format of struct callee_regs thus needs adjustment. This also reduces the height of topmost kernel stack frame by 1 word. * Since kernel stack unwinder is sensitive to height of topmost kernel stack frame, that needs a word of adjustment too. ptrace needs a bit of updating since pt_regs now diverges from user_regs_struct. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: pt_regs update #2: Remove unused gutter at start of pt_regsVineet Gupta2013-06-224-26/+15Star
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: pt_regs update #1: Align pt_regs end with end of kernel stack pageVineet Gupta2013-06-224-5/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, pt_regs would end at offset of 1 word from end of stack page. ----------------- -> START of page (task->stack) | | | thread_info | ----------------- | | ^ ~ ~ | ~ ~ | | | | | | <---- pt_regs used to END here ----------------- | 1 word GUTTER | ----------------- -> End of page (START of kernel stack) This required special "one-off" considerations in low level code. The root cause is very likely assumption of "empty" SP by the original ARC kernel hackers, despite ARC700 always been "full" SP. So finally RIP one word gutter ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: pt_regs update #0: remove kernel stack canaryVineet Gupta2013-06-221-18/+0Star
| | | | | | | | | | | | | | | | | | This stack slot is going to be used in subsequent commits Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [mm] Remove @write argument to do_page_fault()Vineet Gupta2013-06-223-23/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can be ascertained within do_page_fault() since it gets the full ECR (Exception Cause Register). Further, for both the callers of do_page_fault(): Prot-V / D-TLB-Miss, the cause sub-fields in ECR are same for same type of access, making the code much more simpler. D-TLB-Miss [LD] 0x00_21_01_00 Prot-V [LD] 0x00_23_01_00 ^^ D-TLB-Miss [ST] 0x00_21_02_00 Prot-V [ST] 0x00_23_02_00 ^^ D-TLB-Miss [EX] 0x00_21_03_00 Prot-V [EX] 0x00_23_03_00 ^^ This helps code consolidation, which is even better when moving code from assembler to "C". Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [mm] Make stack/heap Non-executable by defaultVineet Gupta2013-06-222-13/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. For VM_EXEC based delayed dcache/icache flush, reduces the number of flushes. 2. Makes this security feature ON by default rather than OFF before. 3. Applications can use mprotect() to selectively override this. 4. ELF binaries have a GNU_STACK segment which can easily override the kernel default permissions. For nested-functions/trampolines, gcc already auto-enables executable stack in elf. Others needing this can use -Wl,-z,execstack option. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [mm] Assume pagecache page dirty by defaultVineet Gupta2013-06-223-7/+14
| | | | | | | | | | | | | | | | | | Similar to ARM/SH Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [mm] optimise VIPT dcache aliasing 2/xVineet Gupta2013-06-221-0/+1
| | | | | | | | | | | | | | | | | | | | | Non-congruent SRC page in copy_user_page() is dcache clean in the end - so record that fact, to avoid a subsequent extraneous flush. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [mm] optimise VIPT dcache aliasing 1/xVineet Gupta2013-06-221-1/+6
| | | | | | | | | | | | | | | | | | flush_cache_page() - kills icache only if page is executable Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [mm] Zero page optimizationVineet Gupta2013-06-221-1/+5
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: make dcache VIPT aliasing support dependant on dcacheAlexey Brodkin2013-06-221-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: No-op full icache flush if !CONFIG_ARC_HAS_ICACHEVineet Gupta2013-06-221-19/+9Star
| | | | | | | | | | | | | | | | | | Also remove extraneous irq disabling in flush_cache_all() callstack Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: cache detection code bitrotVineet Gupta2013-06-224-37/+13Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Number of (i|d)cache ways can be retrieved from BCRs and hence no need to cross check with with built-in constants * Use of IS_ENABLED() to check for a Kconfig option * is_not_cache_aligned() not used anymore Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Reduce Code for ECR printingVineet Gupta2013-06-221-9/+7Star
| | | | | | | | | | | | | | | | | | Cause codes are same for D-TLB-Miss and Prot-V Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Disintegrate arcregs.hVineet Gupta2013-06-2212-162/+139Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Move the various sub-system defines/types into relevant files/functions (reduces compilation time) * move CPU specific stuff out of asm/tlb.h into asm/mmu.h Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: More code beautification with IS_ENABLED()Vineet Gupta2013-06-221-9/+3Star
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Use kconfig helper IS_ENABLED() to get rid of defines.hVineet Gupta2013-06-228-68/+23Star
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [plat-arcfpga] Fix build breakage when !CONFIG_ARC_SERIALMischa Jonker2013-06-221-3/+9
| |/ | | | | | | | | | | | | | | | | | | | | | | This fixes the following: - CONFIG_ARC_SERIAL_BAUD is only defined when CONFIG_SERIAL_ARC is defined. Make sure that it isn't referenced otherwise. - There is no use for initializing arc_uart_info[] when CONFIG_SERIAL_ARC is not defined. [vgupta: tweaked changelog title, used IS_ENABLED() kconfig helper] Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* | more open-coded file_inode() callsAl Viro2013-06-291-1/+1
| | | | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | consolidate io_remap_pfn_range definitionsAl Viro2013-06-291-3/+0Star
|/ | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* ARC: lazy dcache flush broke gdb in non-aliasing configsVineet Gupta2013-05-252-19/+11Star
| | | | | | | | | | | | | gdbserver inserting a breakpoint ends up calling copy_user_page() for a code page. The generic version of which (non-aliasing config) didn't set the PG_arch_1 bit hence update_mmu_cache() didn't sync dcache/icache for corresponding dynamic loader code page - causing garbade to be executed. So now aliasing versions of copy_user_highpage()/clear_page() are made default. There is no significant overhead since all of special alias handling code is compiled out for non-aliasing build Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Use enough bits for determining page's cache colorVineet Gupta2013-05-231-1/+1
| | | | | | | | | The current code uses 2 bits for determining page's dcache color, thus sorting pages into 4 bins, whereas the aliasing dcache really has 2 bins (8k page, 64k dcache - 4 way-set-assoc). This can cause extraneous flushes - e.g. color 0 and 2. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Brown paper bag bug in macro for checking cache colorVineet Gupta2013-05-232-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | The VM_EXEC check in update_mmu_cache() was getting optimized away because of a stupid error in definition of macro addr_not_cache_congruent() The intention was to have the equivalent of following: if (a || (1 ? b : 0)) but we ended up with following: if (a || 1 ? b : 0) And because precedence of '||' is more that that of '?', gcc was optimizing away evaluation of <a> Nasty Repercussions: 1. For non-aliasing configs it would mean some extraneous dcache flushes for non-code pages if U/K mappings were not congruent. 2. For aliasing config, some needed dcache flush for code pages might be missed if U/K mappings were congruent. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: copy_(to|from)_user() to honor usermode-access permissionsVineet Gupta2013-05-233-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This manifested as grep failing psuedo-randomly: -------------->8--------------------- [ARCLinux]$ ip address show lo | grep inet [ARCLinux]$ ip address show lo | grep inet [ARCLinux]$ ip address show lo | grep inet [ARCLinux]$ [ARCLinux]$ ip address show lo | grep inet inet 127.0.0.1/8 scope host lo -------------->8--------------------- ARC700 MMU provides fully orthogonal permission bits per page: Ur, Uw, Ux, Kr, Kw, Kx The user mode page permission templates used to have all Kernel mode access bits enabled. This caused a tricky race condition observed with uClibc buffered file read and UNIX pipes. 1. Read access to an anon mapped page in libc .bss: write-protected zero_page mapped: TLB Entry installed with Ur + K[rwx] 2. grep calls libc:getc() -> buffered read layer calls read(2) with the internal read buffer in same .bss page. The read() call is on STDIN which has been redirected to a pipe. read(2) => sys_read() => pipe_read() => copy_to_user() 3. Since page has Kernel-write permission (despite being user-mode write-protected), copy_to_user() suceeds w/o taking a MMU TLB-Miss Exception (page-fault for ARC). core-MM is unaware that kernel erroneously wrote to the reserved read-only zero-page (BUG #1) 4. Control returns to userspace which now does a write to same .bss page Since Linux MM is not aware that page has been modified by kernel, it simply reassigns a new writable zero-init page to mapping, loosing the prior write by kernel - effectively zero'ing out the libc read buffer under the hood - hence grep doesn't see right data (BUG #2) The fix is to make all kernel-mode access permissions mirror the user-mode ones. Note that the kernel still has full access to pages, when accessed directly (w/o MMU) - this fix ensures that kernel-mode access in copy_to_from() path uses the same faulting access model as for pure user accesses to keep MM fully aware of page state. The issue is peudo-random because it only shows up if the TLB entry installed in #1 is present at the time of #3. If it is evicted out, due to TLB pressure or some-such, then copy_to_user() does take a TLB Miss Exception, with a routine write-to-anon COW processing installing a fresh page for kernel writes and also usable as it is in userspace. Further the issue was dormant for so long as it depends on where the libc internal read buffer (in .bss) is mapped at runtime. If it happens to reside in file-backed data mapping of libc (in the page-aligned slack space trailing the file backed data), loader zero padding the slack space, does the early cow page replacement, setting things up at the very beginning itself. With gcc 4.8 based builds, the libc buffer got pushed out to a real anon mapping which triggers the issue. Reported-by: Anton Kolesov <akolesov@synopsys.com> Cc: <stable@vger.kernel.org> # 3.9 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: [mm] Prevent stray dcache lines after__sync_icache_dcach()Vineet Gupta2013-05-231-1/+1
| | | | | | | | | | | Flush and INVALIDATE the dcache page. This helper is only used for writeback of CODE pages to memory. So there's no value in keeping the dcache lines around. Infact it is risky as a writeback on natural eviction under pressure can cause un-needed writeback with weird issues on aliasing dcache configurations. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: [TB10x] Remove redundant abilis,simple-pinctrl mechanismChristian Ruppert2013-05-154-32/+4Star
| | | | | | | | | | | | | | | | The TB10x platform port includes a custom mechanism using to set up default pin controller configurations using abilis,simple-default pin configurations of nodes compatible with abilis,simple-pinctrl. This mechanism is redundant with the Linux standard "default" pin configuration, see commit ab78029ecc347debbd737f06688d788bd9d60c1d "drivers/pinctrl: grab default handles from device core". This patch removes the TB10x custom mechanism in favour of the Linux standard. Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* Merge tag 'arc-v3.10-rc1-part2' of ↵Linus Torvalds2013-05-1013-74/+377
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull second set of arc arch updates from Vineet Gupta: "Aliasing VIPT dcache support for ARC I'm satisified with testing, specially with fuse which has historically given grief to VIPT arches (ARM/PARISC...)" * tag 'arc-v3.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [TB10x] Remove GENERIC_GPIO ARC: [mm] Aliasing VIPT dcache support 4/4 ARC: [mm] Aliasing VIPT dcache support 3/4 ARC: [mm] Aliasing VIPT dcache support 2/4 ARC: [mm] Aliasing VIPT dcache support 1/4 ARC: [mm] refactor the core (i|d)cache line ops loops ARC: [mm] serious bug in vaddr based icache flush
| * ARC: [TB10x] Remove GENERIC_GPIOVineet Gupta2013-05-101-7/+0Star
| | | | | | | | | | | | | | This tracks Alexandre Courbot's mainline GPIO rework Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Alexandre Courbot <acourbot@nvidia.com>
| * ARC: [mm] Aliasing VIPT dcache support 4/4Vineet Gupta2013-05-097-5/+101
| | | | | | | | | | | | Enforce congruency of userspace shared mappings Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: [mm] Aliasing VIPT dcache support 3/4Vineet Gupta2013-05-092-2/+4
| | | | | | | | | | | | Fix the one zillion warnings Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: [mm] Aliasing VIPT dcache support 2/4Vineet Gupta2013-05-096-22/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the meat of the series which prevents any dcache alias creation by always keeping the U and K mapping of a page congruent. If a mapping already exists, and other tries to access the page, prev one is flushed to physical page (wback+inv) Essentially flush_dcache_page()/copy_user_highpage() create K-mapping of a page, but try to defer flushing, unless U-mapping exist. When page is actually mapped to userspace, update_mmu_cache() flushes the K-mapping (in certain cases this can be optimised out) Additonally flush_cache_mm(), flush_cache_range(), flush_cache_page() handle the puring of stale userspace mappings on exit/munmap... flush_anon_page() handles the existing U-mapping for anon page before kernel reads it via the GUP path. Note that while not complete, this is enough to boot a simple dynamically linked Busybox based rootfs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: [mm] Aliasing VIPT dcache support 1/4Vineet Gupta2013-05-093-18/+34
| | | | | | | | | | | | | | This preps the low level dcache flush helpers to take vaddr argument in addition to the existing paddr to properly flush the VIPT dcache Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: [mm] refactor the core (i|d)cache line ops loopsVineet Gupta2013-05-091-29/+24Star
| | | | | | | | | | | | | | | | Nothing semantical * simplify the alignement code by using & operation only * rename variables clearly as paddr Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: [mm] serious bug in vaddr based icache flushVineet Gupta2013-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | vaddr used to index the cache was clipped from the wrong end, and thus would potentially fail to flush the correct lines. The problem was dorment for so long because up until the recent optimizations it was only used for ptrace break-point only flushes. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* | Merge tag 'arc-v3.10-rc1-part1' of ↵Linus Torvalds2013-05-0938-342/+1840
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC port updates from Vineet Gupta: "Support for two new platforms based on ARC700: - Abilis TB10x SoC [Chritisian/Pierrick] - Simulator only System-C Model [Mischa] ARC specific MM improvements: - Avoid full TLB flush (ASID increment) on munmap (even single page) - VIPT Cache Flushing improvements + Delayed dcache flush for non-aliasing dcache (big performance boost) + icache flush aliasing agnostic (no need to kill all possible aliases) Others: - Avoid needless rebuild of DTB files for every kernel build - Remove builtin cmdline as that is already provided by DeviceTree/bootargs - Fixing unaligned access emulation corner case - checkpatch fixes [Sachin] - Various fixlets [Noam] - Minor build failures/cleanups" * tag 'arc-v3.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (35 commits) ARC: [mm] Lazy D-cache flush (non aliasing VIPT) ARC: [mm] micro-optimize page size icache invalidate ARC: [mm] remove the pessimistic all-alias-invalidate icache helpers ARC: [mm] consolidate icache/dcache sync code ARC: [mm] optimise icache flush for kernel mappings ARC: [mm] optimise icache flush for user mappings ARC: [mm] optimize needless full mm TLB flush on munmap ARC: Add support for nSIM OSCI System C model ARC: [TB10x] Adapt device tree to new compatible string ARC: [TB10x] Add support for TB10x platform ARC: [TB10x] Device tree of TB100 and TB101 Development Kits ARC: Prepare interrupt code for external controllers ARC: Allow embedded arc-intc to be properly placed in DT intc hierarchy ARC: [cmdline] Don't overwrite u-boot provided bootargs ARC: [cmdline] Remove CONFIG_CMDLINE ARC: [plat-arcfpga] defconfig update ARC: unaligned access emulation broken if callee-reg dest of LD/ST ARC: unaligned access emulation error handling consolidation ARC: Debug/crash-printing Improvements ARC: fix typo with clock speed ...
| * ARC: [mm] Lazy D-cache flush (non aliasing VIPT)Vineet Gupta2013-05-073-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flush_dcache_page( ) is MM hook to ensure that a page has consistent views between kernel and userspace. Thus it is called when * kernel writes to a page which at some later point could get mapped to userspace (so kernel mapping needs to be flushed-n-inv) * kernel is about to read from a page with possible userspace mappings (so userspace mappings needs to be made coherent with kernel ones) However for Non aliasing VIPT dcache, any userspace mapping will always be congruent to kernel mapping. Thus d-cache need need not be flushed at all (or delayed indefinitely). The only reason it does need to be flushed is when mapping code pages. Since icache doesn't snoop dcache, those dirty dcache lines need to be written back to memory and icache line invalidated so that icache lines fetch will get the right data. Decent gains on LMBench fork/exec/sh and File I/O micro-benchmarks. (1) FPGA @ 80 MHZ Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 3.9-rc6-a Linux 3.9.0-r 80 4.79 8.72 66.7 116. 239. 8.39 30.4 4798 14.K 34.K 3.9-rc6-b Linux 3.9.0-r 80 4.79 8.62 65.4 111. 239. 8.35 29.0 3995 12.K 30.K 3.9-rc7-c Linux 3.9.0-r 80 4.79 9.00 66.1 106. 239. 8.61 30.4 2858 10.K 24.K ^^^^ ^^^^ ^^^ File & VM system latencies in microseconds - smaller is better ------------------------------------------------------------------------------- Host OS 0K File 10K File Mmap Prot Page 100fd Create Delete Create Delete Latency Fault Fault selct --------- ------------- ------ ------ ------ ------ ------- ----- ------- ----- 3.9-rc6-a Linux 3.9.0-r 317.8 204.2 1122.3 375.1 3522.0 4.288 20.7 126.8 3.9-rc6-b Linux 3.9.0-r 298.7 223.0 1141.6 367.8 3531.0 4.866 20.9 126.4 3.9-rc7-c Linux 3.9.0-r 278.4 179.2 862.1 339.3 3705.0 3.223 20.3 126.6 ^^^^^ ^^^^^ ^^^^^ ^^^^ (2) Customer Silicon @ 500 MHz (166 MHz mem) ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- abilis-ba Linux 3.9.0-r 497 0.71 1.38 4.58 12.0 35.5 1.40 3.89 2070 5525 13.K abilis-ca Linux 3.9.0-r 497 0.71 1.40 4.61 11.8 35.6 1.37 3.92 1411 4317 10.K ^^^^ ^^^^ ^^^ Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: [mm] micro-optimize page size icache invalidateVineet Gupta2013-05-071-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | start address is already page aligned and size is const PAGE_SIZE, thus fixups for alignment not needed in generated code. bloat-o-meter vmlinux-mm5 vmlinux add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-32 (-32) function old new delta __inv_icache_page 82 50 -32 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: [mm] remove the pessimistic all-alias-invalidate icache helpersVineet Gupta2013-05-071-184/+17Star
| | | | | | | | | | | | No users of this code anymore - so RIP ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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