openslx/kernel-qcow2-linux.git - In-kernel qcow2 (Kernel part)

	Commit message (Collapse)	Author	Age	Files	Lines
*	ARM: dts: gr-peach: Enable ostm0 and ostm1 timers	Jacopo Mondi	2017-10-12	1	-0/+8
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Enable ostm0 and ostm1 timers to be used as clock source and clockevent source. The timers provides greater accuracy than the already enabled mtu2 one. With these enabled: clocksource: ostm: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 57352151442 ns sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns ostm: used for clocksource ostm: used for clock events Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Suggested-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
*	ARM: dts: gr-peach: Add ETHER pin group	Jacopo Mondi	2017-10-12	1	-0/+39
\| \| \| \| \| \| \| \|	Add pin configuration subnode for ETHER pin group. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
*	ARM: dts: gr-peach: Enable MTU2 timer pulse unit	Jacopo Mondi	2017-10-05	1	-0/+4
\| \| \| \| \| \| \| \| \| \| \|	MTU2 multi-function/multi-channel timer/counter is not enabled for GR-Peach board. The timer is used as clock event source to schedule wake-ups, and without this enabled all sleeps not performed through busy waiting hang the board. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
*	ARM: dts: gr-peach: Fix 'leds' node name indent	Jacopo Mondi	2017-10-05	1	-1/+1
\| \| \| \| \| \| \|	Fix 'leds' node name indent as it was wrongly aligned. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
*	ARM: dts: gr-peach: Add user led device nodes	Jacopo Mondi	2017-09-19	1	-0/+10
\| \| \| \| \| \| \| \|	Add device nodes for user leds on gr-peach board. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
*	ARM: dts: gr-peach: Add SCIF2 pin group	Jacopo Mondi	2017-09-19	1	-0/+11
\| \| \| \| \| \| \| \|	Add pin configuration subnode for SCIF2 serial debug interface. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
*	ARM: dts: gr-peach: Remove empty line	Jacopo Mondi	2017-09-19	1	-1/+0
\| \| \| \| \| \| \| \|	Remove an empty line in gr-peach device tree source file. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
*	ARM: dts: r7s72100: Add support for GR-Peach	Jacopo Mondi	2017-06-12	1	-0/+66
	Add device tree source for Renesas GR-Peach board. GR-Peach is an RZ/A1H based board with 10MB of on-chip SRAM and 8MB QSPI flash storage. Add support for the board, and create a 2MB partition to use as rootfs. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>