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* ARM: dts: sun8i: v3s: Remove skeleton and memory to avoid warningsMaxime Ripard2018-11-281-5/+0Star
| | | | | | | | | | Our memory node will generate a warning in DTC since the unit address is not matching the reg property. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun8i: a83t: Add support for the cir interfacePhilipp Rossak2018-08-271-0/+13
| | | | | | | | | The cir interface is like on the H3 located at 0x01f02000 and is exactly the same. This patch adds support for the ir interface on the A83T. Signed-off-by: Philipp Rossak <embed3d@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun8i: a83t: Add the cir pin for the A83TPhilipp Rossak2018-08-271-0/+5
| | | | | | | | The CIR Pin of the A83T is located at PL12. Signed-off-by: Philipp Rossak <embed3d@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun8i: a83t: Remove unused address-cells/size-cells of dwmac-sun8iCorentin Labbe2018-07-191-2/+0Star
| | | | | | | | | | | | ddress-cells/size-cells is unnecessary for dwmac-sun8i node. It was in early days, but since a mdio node is used, it could be removed. This patch fix the following DT warning: Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoCMylène Josserand2018-05-091-0/+8
| | | | | | | | | | Add the use of enable-method property for SMP support which allows to handle the SMP support for this specific SoC. This commit adds enable-method properties to all CPU nodes. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: a83t: Add CCI-400 nodeMylène Josserand2018-05-091-0/+41
| | | | | | | | Add CCI-400 node and control-port on CPUs needed by SMP bringup. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsiMylène Josserand2018-05-091-0/+5
| | | | | | | | | | | The R_CPUCFG is a collection of registers needed for SMP bringup on clusters and cluster's reset. For the moment, documentation about this register is found in Allwinner's code only. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: Add CPUCFG device node for A83T dtsiMylène Josserand2018-05-091-0/+5
| | | | | | | | | | | | As we found in sun9i-a80, CPUCFG is a collection of registers that are mapped to the SoC's signals from each individual processor core and associated peripherals. These registers are used for SMP bringup and CPU hotplugging. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: Add sid for a83tkevans@FreeBSD.org2018-04-191-0/+5
| | | | | | | | | | | Allwinner a83t has a 1 KB sid block with efuse for security rootkey and thermal calibration data, add node to describe it. a83t-sid is not currently supported by nvmem/sunxi-sid, but it is supported in an external driver for FreeBSD. Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: a83t: add stable OPP tables and CPUfreqQuentin Schulz2018-02-281-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A83T is an octacore A7 divided in two clusters of 4 A7, each cluster having its own regulator and clock. The operating points were found in Allwinner BSP and fex files. Note that there are a few OPPs that are missing: 1608000000Hz with 920000mV 1800000000Hz with 1000000mV 2016000000Hz with 1080000mV These OPPs are pretty unstable but it might be due to the SoC quickly overheating (till the board completely shuts down). It seems impossible to reach those frequencies with none or passive cooling, so better leave them out by default. It's still possible to add those OPPs on a per-board basis though. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> [maxime: Reordered the nodes alphabetically] Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: a83t: add cpu0 and cpu100 labelsQuentin Schulz2018-02-281-2/+2
| | | | | | | | | | | | The Allwinner A83T is a SoC with two clusters of 4 A7, each cluster having its own regulator and clock. The regulators are board-specific, thus we need labels for cpu0 and cpu100 so that we can use references to these nodes from the board header file. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: a83t: Add HDMI display pipelineJernej Skrabec2018-02-161-1/+107
| | | | | | | | This commit adds all bits necessary for HDMI on A83T - mixer1, tcon1, hdmi, hdmi phy and hdmi pinctrl entries. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: a83t: Add LVDS pins groupMaxime Ripard2018-01-041-0/+6
| | | | | | | | The A83T has an LVDS bus that can be connected to a panel or a bridge. Add the pinctrl group for it. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Enable the PWMMaxime Ripard2018-01-041-0/+14
| | | | | | | The A83T has the same PWM block than the H3. Add it to our DT. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Add display pipelineMaxime Ripard2018-01-041-0/+79
| | | | | | | | | | | | The display pipeline on the A83T is mainly composed of the mixers and TCONs, plus various encoders. Let's add the first mixer and TCON to the DTSI since the only board I have can use only the LVDS output on the first TCON. The other parts will be added eventually. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Add I2C device nodes and pinmux settingsChen-Yu Tsai2017-12-151-0/+55
| | | | | | | | | | | | | | | | | The A83T has 3 I2C controllers under the standard bus. There is one more in the R_ block section. The pin functions for the 3 controllers are on PH 0~6. I2C2 can also be used on pins PE14 and PE15, but these pins can also mux the CSI (camera sensor interface) controller's embedded I2C controller. The latter seems to be preferred in the reference designs for I2C camera sensor access, freeing I2C2 for other uses. This patch adds device nodes for the three standard I2C controllers, as well as pinmux settings for the PH pins. For I2C0 and I2C1, since they only have one possible setting, just set them by default. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Add I2S controller device nodesChen-Yu Tsai2017-12-151-0/+47
| | | | | | | | | | | | | | The A83T has 3 I2S controllers. The first is multiplexed with the TDM controller. The pins are generally connected to the codec side of the AXP81x PMIC/codec/RTC chip. The second is free for other uses. The third only supports output, and is connected internally to the HDMI controller for HDMI audio output. This patch adds device nodes for the controllers, and a default pinmux setting for the second controller. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: add dwmac-sun8i device nodeCorentin LABBE2017-12-081-0/+33
| | | | | | | | | | | | The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch add support for it on the Allwinner a83t SoC Device-tree. This patch add the emac device node and the related RGMII pins node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi fileChen-Yu Tsai2017-11-021-0/+2
| | | | | | | | | mmc1 only has 1 possible pinmux setting. Move any settings to the dtsi file and set it by default. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Fix simple-bus unit address format errorCorentin LABBE2017-09-271-3/+3
| | | | | | | | | This patch remove leading 0 of unit address and so remove lots of warning when building DT with W=1. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* arm: dts: sun8i: a83t: Add the UART1 controllerMaxime Ripard2017-09-171-0/+21
| | | | | | | | The A83T has an UART1 controller, with the RTS and CTS pins routed so it can be used for devices with hardware flow control, like a bluetooth chip. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* arm: dts: sun8i: a83t: Add MMC1 pinsMaxime Ripard2017-09-171-0/+8
| | | | | | | Add the pinctrl definitions for the A83t MMC1 controller. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* arm: dts: sun8i: a83t: Remove useless, empty nodesMaxime Ripard2017-09-171-6/+0Star
| | | | | | | Those nodes are useless, remove them. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Add device node for USB OTG controllerChen-Yu Tsai2017-08-181-0/+14
| | | | | | | | | The USB OTG controller found on the A83T is compatible with the one found on the A33. Add a device node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun8i: a83t: Add USB PHY and host device nodesChen-Yu Tsai2017-08-181-0/+62
| | | | | | | | | The A83T has 3 USB PHYs, 1 for USB OTG, 1 for standard USB 2.0, 1 for USB HSIC. EHCI0/OHCI0 are the standard USB host pair, while EHCI1 is the host controller for HSIC. OTG is not added yet. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Add device node and pinmux setting for RSB controllerChen-Yu Tsai2017-08-081-0/+23
| | | | | | | | | The A83T has an RSB controller for talking to the PMIC and audio codec. Add a device node for it. Since there is only one usable pinmux setting, for it, add that as well. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Add pingroup for 8-bit eMMC on mmc2Chen-Yu Tsai2017-08-051-0/+9
| | | | | | | mmc2 can support 8-bit eMMC chips, with a dedicated reset line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Add MMC controller device nodesChen-Yu Tsai2017-08-051-0/+59
| | | | | | | | The A83T has 3 MMC controllers. The third one is a bit special, as it supports a wider 8-bit bus, and a "new timing mode". Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Add device node for R_INTC interrupt controllerChen-Yu Tsai2017-08-051-0/+9
| | | | | | | | | | | | | | | | | | | The R_INTC interrupt controller handles the NMI interrupt pin for the SoC. While there is no documentation or code from the vendor for this device on the A83T, existing mainline kernel drivers and bindings show this to be similar to the old Allwinner interrupt controller found on the A10 SoC, but with only the NMI interrupt wired. Register poking experiments confirm this. The device seems to be the same across all recent Allwinner SoCs, apart from the A20 and A80, which have a separate set of registers to handle the NMI interrupt. We already have a set of bindings supporting this on the A31. Add a device node for it, with an SoC specific compatible. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: a83t: Switch to CCU device tree binding macrosChen-Yu Tsai2017-07-271-7/+9
| | | | | | | | | Now that the CCU device tree binding headers have been merged, we can use the properly named macros in the device tree, instead of raw numbers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Add dt node for the syscon control moduleCorentin Labbe2017-06-141-0/+6
| | | | | | | | | This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Add device node for R_PIOChen-Yu Tsai2017-06-091-0/+15
| | | | | | | | | The A83T has 1 pingroup with 13 pins belonging to the R_PIO or special pin controller. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sun8i: a83t: Add device node for PRCMChen-Yu Tsai2017-06-031-0/+10
| | | | | | | | | | | | The A83T's PRCM has the same set of clocks and resets as the A64. However, a few dividers are different. And due to the lack of a low speed 32.768 kHz oscillator, a few of the clock parents are different. The PRCM also has controls for various power domains. These are not supported yet, neither in software nor in the device tree binding. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Add device node for SPDIF transmitterChen-Yu Tsai2017-05-221-0/+21
| | | | | | | | | | The A83T SoC has an SPDIF transmitter block. According to the vendor BSP kernel, it is compatible with the one found on the H3 SoC. Add a device node and pinmux setting for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Add device node for DMA controllerChen-Yu Tsai2017-05-221-0/+9
| | | | | | | | | | The A83T SoC has a DMA controller that supports 8 DMA channels to and from various peripherals. Add a device node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillatorChen-Yu Tsai2017-05-191-0/+1
| | | | | | | | | The datasheets for Allwinner SoCs set strict requirements on the stability of the external crystal oscillators. Add the accuracy for the main 24MHz oscillator to the device tree. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Add CCU device nodesChen-Yu Tsai2017-05-191-2/+13
| | | | | | | | | Now that we have support for the A83T CCU, add a device node for it, and replace any existing placeholder clock phandles with the correct ones. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Replace underscores with hyphens in pinmux node namesChen-Yu Tsai2017-05-141-3/+3
| | | | | | | | | We should use hyphens and not underscores in device node names. Replace the ones that were just added. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Drop leading zeroes from device node addressesChen-Yu Tsai2017-05-141-4/+4
| | | | | | | | | | | | | Kbuild now complains about leading zeroes in the address portion of device node names. Get rid of them all, except for the uart device node. U-boot currently hard codes the device node path. We can remove the leading zero for the uart once we teach U-boot to use the aliases or stdout-path property. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Rename pinmux setting namesChen-Yu Tsai2017-05-141-5/+5
| | | | | | | | | | | | | The pinmux setting nodes all have an address element in their node names, however the pinctrl node does not have #address-cells. Rename the existing pinmux setting nodes and labels in sun8i-a83t.dtsi, dropping identifiers for functions that only have one possible setting, and using the pingroup name if the function is identically available on different pingroups. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun8i: a83t: Drop skeleton.dtsiChen-Yu Tsai2017-05-141-3/+13
| | | | | | | | | | | skeleton.dtsi is deprecated. Remove it from sun8i-a83t.dtsi and add the needed device nodes directly. Also drop an extra, non-style-conforming line in the copyright license header. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai2017-03-271-2/+0Star
| | | | | | | | | | | | | | | | | All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm/boot/dts/sun?i*.* arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra empty line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'sunxi-dt-for-4.11' of ↵Arnd Bergmann2017-02-071-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt Pull "Allwinner DT changes for 4.11" from Maxime Ripard: The usual chunk of DT changes, most notably: - Support for the H2+ and the V3s - CPUFreq support for the A33 - SPDIF support for the A31 and H3 - New boards: Beelink X2, Lichee Pi One, Lichee Pi Zero, Orange Pi Zero * tag 'sunxi-dt-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (42 commits) ARM: dts: sun8i-h3: Add SPDIF to the Beelink X2 ARM: dts: sun8i-h3: Add the SPDIF block to the H3 ARM: dts: sun8i-h3: Add SPDIF TX pin to the H3 ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB ARM: sun8i: sina33: Enable display ARM: sun8i: a23/a33: Add the oscillators accuracy ARM: sun8i: a23/a33: Enable the real LOSC and use it ARM: dts: sunxi: add support for Lichee Pi Zero board ARM: dts: sunxi: add dtsi file for V3s SoC ARM: dts: sun6i: sina31s: Enable USB OTG controller in peripheral mode ARM: dts: sun8i: reference-design: use AXP223 DTSI ARM: dts: sun8i: parrot: use AXP223 DTSI ARM: dts: sun8i: sina33: use AXP223 DTSI ARM: dts: sun8i: a33-olinuxino: use AXP223 DTSI ARM: dts: add DTSI for AXP223 dt-bindings: power: axp20x-usb: add axp223 compatible ARM: dts: sun7i: Add wifi dt node on Banana Pro ARM: dts: sun6i: Add SPDIF to the Mele I7 devicetree: bindings: Add vendor prefix for Shenzhen Xunlong Software ARM: dts: sun8i-h3: orange-pi-pc: Enable audio codec ...
| * ARM: dts: sunxi: Explicitly enable pull-ups for MMC pinsChen-Yu Tsai2017-01-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the past, all the MMC pins had allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; which was actually a no-op. We were relying on U-boot to set the bias pull up for us. These properties were removed as part of the fix up to actually support no bias on the pins. During the transition some boards experienced regular MMC time-outs during normal operation, while others completely failed to initialize the SD card. Given that MMC starts in open-drain mode and the pull-ups are required, it's best to enable it for all the pin settings. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: DTS: Fix register map for virt-capable GICMarc Zyngier2017-02-071-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: sunxi: Convert pinctrl nodes to generic bindingsMaxime Ripard2016-12-261-8/+8
| | | | | | | | Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Remove useless allwinner,pull propertyMaxime Ripard2016-12-261-3/+0Star
| | | | | | | | | | | | The allwinner,pull property set to NO_PULL was really considered our default (and wasn't even changing the default value in the code). Remove these properties to make it obvious that we do not set anything in such a case. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Remove useless allwinner,drive propertyMaxime Ripard2016-12-261-2/+0Star
| | | | | | | | | The allwinner,drive property set to 10mA was really considered as our default. Remove all those properties entirely to make that obvious. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: dts: sun8i-a83t: Correct low speed oscillator clocksChen-Yu Tsai2016-02-041-3/+18
| | | | | | | | | | | The A83T does not have a 32.768 kHz low speed oscillator, either as an external crystal or input. It has a 16 MHz RC-based (inaccurate) internal oscillator, which is then divided by 512 for a clock close to 32 kHz. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: Add watchdog device node for A83TChen-Yu Tsai2016-01-251-0/+7
| | | | | | | | The A83T, like previous Allwinner SoCs, has a watchdog as part of its timer block. Add a device node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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