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* [ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory typePaul Walmsley2009-03-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a Non-cacheable Normal ARM executable memory type, MT_MEMORY_NONCACHED. On OMAP3, this is used for rapid dynamic voltage/frequency scaling in the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the VDD2 voltage domain, and its clock frequency must change along with voltage. The SDRC clock change code cannot run from SDRAM itself, since SDRAM accesses are paused during the clock change. So the current implementation of the DVFS code executes from OMAP on-chip SRAM, aka "OCM RAM." If the OCM RAM pages are marked as Cacheable, the ARM cache controller will attempt to flush dirty cache lines to the SDRC, so it can fill those lines with OCM RAM instruction code. The problem is that the SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU subsystem to hang. TI's original solution to this problem was to mark the OCM RAM sections as Strongly Ordered memory, thus preventing caching. This is overkill: since the memory is marked as non-bufferable, OCM RAM writes become needlessly slow. The idea of "Strongly Ordered SRAM" is also conceptually disturbing. Previous LAKML list discussion is here: http://www.spinics.net/lists/arm-kernel/msg54312.html This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future patch. Cc: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'dma' into develRussell King2009-02-211-19/+16Star
|\ | | | | | | | | | | Conflicts: arch/arm/plat-mxc/dma-mx1-mx2.c
| * [ARM] dma: move IOMD and floppy DMA structures to RiscPC DMA codeRussell King2009-02-211-13/+0Star
| | | | | | | | | | | | | | There's no point these being in a generic include file when they're only used in arch/arm/mach-rpc/dma.c. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: remove dmamode_t typedefRussell King2009-01-021-1/+1
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: constify dma controller name and dma opsRussell King2008-12-111-2/+2
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: move RiscPC specific DMA data out of dma_structRussell King2008-12-111-5/+13
| | | | | | | | | | | | | | Separate the RiscPC specific (IOMD and floppy FIQ) data out of the core DMA structure by making the IOMD and floppy DMA supersets. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: rejig DMA initializationRussell King2008-12-111-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than having the central DMA multiplexer call the architecture specific DMA initialization function, have each architecture DMA initialization function use core_initcall(), and register each DMA channel separately with the multiplexer. This removes the array of dma structures in the central multiplexer, replacing it with an array of pointers instead; this is more flexible since it allows the drivers to wrap the DMA structure (eventually allowing us to transition non-ISA DMA drivers away.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: remove dmach_t typedefRussell King2008-12-081-6/+6
| | | | | | | | | | | | Remove a pointless integer typedef. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | PCI: arm: use generic INTx swizzle from PCI coreBjorn Helgaas2009-01-071-1/+1
|/ | | | | | | Use the generic pci_common_swizzle() instead of arch-specific code. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* [ARM] iop: iop3xx needs registers mapped uncached+unbufferedRussell King2008-11-091-6/+7
| | | | | | | | | | | | | | | | | | | | | Mikael Pettersson reported: The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0 (the first ethernet port) on my Thecus n2100 XScale box. There is however still a strange "ghost" device that gets partially detected in 2.6.28-rc2 vanilla. The IOP321 manual says: The user designates the memory region containing the OCCDR as non-cacheable and non-bufferable from the IntelR XScaleTM core. This guarantees that all load/stores to the OCCDR are only of DWORD quantities. Ensure that the OCCDR is so mapped. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'pxa-all' into develRussell King2008-10-091-2/+1Star
|\ | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-pxa/Kconfig arch/arm/mach-pxa/corgi.c arch/arm/mach-pxa/include/mach/hardware.h arch/arm/mach-pxa/spitz.c
| * Merge branches 'pxa-core' and 'pxa-machines' into pxa-allRussell King2008-10-071-7/+7
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-pxa/Kconfig arch/arm/mach-pxa/pxa25x.c arch/arm/mach-pxa/pxa27x.c
| * | [ARM] pxa: remove references to pxa_gpio_mode() in commentsRussell King2008-09-251-2/+1Star
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] Remove MT_NONSHARED_DEVICE aliasRussell King2008-10-011-2/+0Star
| | | | | | | | | | | | | | | | | | Use MT_DEVICE_NONSHARED instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] Remove MT_DEVICE_IXP2000 and associated definitionsRussell King2008-10-011-8/+7Star
| |/ |/| | | | | | | | | | | | | As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5241/1: provide ioremap_wc()Lennert Buytenhek2008-09-061-7/+7
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides an ARM implementation of ioremap_wc(). We use different page table attributes depending on which CPU we are running on: - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four possible mapping types (CB=00/01/10/11). We can't use any of the cached memory types (CB=10/11), since that breaks coherency with peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and CB=01 (Uncached/Buffered) allows the hardware more freedom than CB=00, so we'll use that. (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores but isn't allowed to merge them, but there is no other mapping type we can use that allows the hardware to delay and merge stores, so we'll go with CB=01.) - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight difference that on these platforms, CB=01 actually _does_ allow merging stores. (If you want noncoalescing bufferable behavior on Xscale v1/v2, you need to use XCB=101.) - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100 mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal in ARMv6 parlance). The ARMv6 ARM explicitly says that any accesses to Normal memory can be merged, which makes Normal memory more suitable for _wc mappings than Device or Strongly Ordered memory, as the latter two mapping types are guaranteed to maintain transaction number, size and order. We use the Uncached variety of Normal mappings for the same reason that we can't use C=1 mappings on ARMv5. The xsc3 Architecture Specification documents TEXCB=00100 as being Uncacheable and allowing coalescing of writes, which is also just what we need. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix circular include dependency with IRQ headersRussell King2008-08-071-20/+0Star
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] move include/asm-arm to arch/arm/include/asmRussell King2008-08-0213-0/+540
Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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