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* Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-10-021-1/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM soc device tree updates from Olof Johansson: "Device tree conversion and enablement branch. Mostly a bunch of new bindings and setup for various platforms, but the Via/Winchip VT8500 platform is also converted over from being 100% legacy to now use device tree for probing. More of that will come for 3.8." Trivial conflicts due to removal of vt8500 files, and one documentation file that was added with slightly different contents both here and in the USb tree. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (212 commits) arm: vt8500: Fixup for missing gpio.h ARM: LPC32xx: LED fix in PHY3250 DTS file ARM: dt: mmp-dma: add binding file arm: vt8500: Update arch-vt8500 to devicetree support. arm: vt8500: gpio: Devicetree support for arch-vt8500 arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices arm: vt8500: clk: Add Common Clock Framework support video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb serial: vt8500: Add devicetree support for vt8500-serial rtc: vt8500: Add devicetree support for vt8500-rtc arm: vt8500: Add device tree files for VIA/Wondermedia SoC's ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support ARM: tegra: Add Avionic Design Medcom-Wide support ARM: tegra: Add Avionic Design Plutux support ARM: tegra: Add Avionic Design Tamonten support ARM: tegra: dts: Add pwm label ARM: ux500: Fix SSP register address format ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT ARM: ux500: Add all encompassing sound node to the HREF Device Tree ...
| * Merge tag 'omap-cleanup-sparseirq-for-v3.7' into devel-dtTony Lindgren2012-09-171-6/+4Star
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This branch contains changes needed to make omap2+ work properly with sparse IRQ. It also removes dependencies to mach/hardware.h. These help moving things towards ARM single zImage support. This branch is based on a commit in tty-next branch with omap-devel-gpmc-fixed-for-v3.7 and cleanup-omap-tags-for-v3.7 merged in to keep things compiling and sort out some merge conflicts. Conflicts: arch/arm/mach-omap2/omap4-common.c drivers/gpio/gpio-twl4030.c
| * | ARM: OMAP4: Add L2 Cache Controller in Device TreeSantosh Shilimkar2012-09-071-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Provide PL310 Level 2 Cache Controller Device Tree support for OMAP4 based devices. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
* | | ARM: OMAP2+: Make omap-wakeupgen.h localTony Lindgren2012-09-211-1/+1
| |/ |/| | | | | | | | | This can be local to mach-omap2. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP: Split plat/hardware.h, use local soc.h for omap2+Tony Lindgren2012-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the plat and mach includes need to disappear for single zImage work, we need to remove plat/hardware.h. Do this by splitting plat/hardware.h into omap1 and omap2+ specific files. The old plat/hardware.h already has omap1 only defines, so it gets moved to mach/hardware.h for omap1. For omap2+, we use the local soc.h that for now just includes the related SoC headers to keep this patch more readable. Note that the local soc.h still includes plat/cpu.h that can be dealt with in later patches. Let's also include plat/serial.h from common.h for all the board-*.c files. This allows making the include files local later on without patching these files again. Note that only minimal changes are done in this patch for the drivers/watchdog/omap_wdt.c driver to keep things compiling. Further patches are needed to eventually remove cpu_is_omap usage in the drivers. Also only minimal changes are done to sound/soc/omap/* to remove the unneeded includes and to define OMAP44XX_MCPDM_L3_BASE locally so there's no need to include omap44xx.h. While at it, also sort some of the includes in the standard way. Cc: linux-watchdog@vger.kernel.org Cc: alsa-devel@alsa-project.org Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jarkko Nikula <jarkko.nikula@bitmer.com> Cc: Liam Girdwood <lrg@ti.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2+: Prepare for irqs.h removalTony Lindgren2012-09-131-4/+3Star
|/ | | | | | | | | | | | | | | | | | | | | | | As the interrupts should only be defined in the platform_data, and eventually coming from device tree, there's no need to define them in header files. Let's remove the hardcoded references to irqs.h and fix up the includes so we don't rely on headers included in irqs.h. Note that we're defining OMAP_INTC_START as 0 to the interrupts. This will be needed when we enable SPARSE_IRQ. For some drivers we need to add #include <plat/cpu.h> for now until these drivers are fixed to remove cpu_is_omapxxxx() usage. While at it, sort som of the includes the standard way, and add the trailing commas where they are missing in the related data structures. Note that for drivers/staging/tidspbridge we just define things locally. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP5: board-generic: Add device tree supportR Sricharan2012-07-091-0/+1
| | | | | | | | | Adding the minimal support for OMAP5 evm board with device tree. Reviewed-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: omap2+: board-generic: clean up the irq data from board fileR Sricharan2012-07-091-0/+13
| | | | | | | | | | | | | Move the irq_match arrays and the irq init functions of OMAP 2,3 and 4 based boards out of board-generic.c file and also rename the irq init function to match the interrupt controller present in the SOCs. This is a preparatory patch to add the OMAP5 evm board's irq init support with device tree. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: OMAP4: hsmmc: check for null pointerBalaji T K2012-05-091-0/+58
| | | | | | | | | | | | | | | | | | | | | | platform_device pdev can be NULL if CONFIG_MMC_OMAP_HS is not set. Add check for NULL pointer. while at it move the duplicated functions to omap4-common.c Fixes the following boot crash seen with omap4sdp and omap4panda when MMC is disabled. Unable to handle kernel NULL pointer dereference at virtual address 0000008c pgd = c0004000 [0000008c] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: CPU: 0 Not tainted (3.4.0-rc1-05971-ga4dfa82 #4) PC is at omap_4430sdp_init+0x184/0x410 LR is at device_add+0x1a0/0x664 Signed-off-by: Balaji T K <balajitk@ti.com> Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2+: Fix module build errors with CONFIG_OMAP4_ERRATA_I688R Sricharan2012-03-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | While building modules with randconfig the below errors are observed. ERROR: "omap_bus_sync" [drivers/watchdog/sp805_wdt.ko] undefined! ERROR: "omap_bus_sync" [drivers/watchdog/dw_wdt.ko] undefined! ERROR: "omap_bus_sync" [drivers/virtio/virtio_ring.ko] undefined! ERROR: "omap_bus_sync" [drivers/video/sm501fb.ko] undefined! ERROR: "omap_bus_sync" [drivers/usb/mon/usbmon.ko] undefined! ERROR: "omap_bus_sync" [drivers/usb/host/sl811-hcd.ko] undefined! ERROR: "omap_bus_sync" [drivers/usb/host/ohci-hcd.ko] undefined! ERROR: "omap_bus_sync" [drivers/usb/host/isp1760.ko] undefined! ERROR: "omap_bus_sync" [drivers/usb/host/isp1362-hcd.ko] undefined! ERROR: "omap_bus_sync" [drivers/usb/host/isp116x-hcd.ko] undefined! ERROR: "omap_bus_sync" [drivers/usb/core/usbcore.ko] undefined! ERROR: "omap_bus_sync" [drivers/tty/serial/altera_uart.ko] undefined! ERROR: "omap_bus_sync" [drivers/tty/serial/altera_jtaguart.ko] undefined! ERROR: "omap_bus_sync" [drivers/tty/serial/8250/8250_dw.ko] undefined! ERROR: "omap_bus_sync" [drivers/ssb/ssb.ko] undefined! ERROR: "omap_bus_sync" [drivers/rtc/rtc-cmos.ko] undefined! ERROR: "omap_bus_sync" [drivers/rtc/rtc-bq4802.ko] undefined! ERROR: "omap_bus_sync" [drivers/mtd/nand/tmio_nand.ko] undefined! ERROR: "omap_bus_sync" [drivers/mtd/nand/omap2.ko] undefined! Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP4: Move the barrier memboclk_steal() as part of reserve callbackSantosh Shilimkar2012-02-141-9/+16
| | | | | | | | | | | arm_memblock_steal() is not suppose to be used outside ->reserve callback. OMAP barrier errata code was using it outside reserve callback and hence it was broken. Move the allocation as part of ->reserve callback to fix the it. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: Add arm_memblock_steal() to allocate memory away from the kernelRussell King2012-01-131-7/+3Star
| | | | | | | | | | | | | | | | | | | | | | Several platforms are now using the memblock_alloc+memblock_free+ memblock_remove trick to obtain memory which won't be mapped in the kernel's page tables. Most platforms do this (correctly) in the ->reserve callback. However, OMAP has started to call these functions outside of this callback, and this is extremely unsafe - memory will not be unmapped, and could well be given out after memblock is no longer responsible for its management. So, provide arm_memblock_steal() to perform this function, and ensure that it panic()s if it is used inappropriately. Convert everyone over, including OMAP. As a result, OMAP with OMAP4_ERRATA_I688 enabled will panic on boot with this change. Mark this option as BROKEN and make it depend on BROKEN. OMAP needs to be fixed, or 137d105d50 (ARM: OMAP4: Fix errata i688 with MPU interconnect barriers.) reverted until such time it can be fixed correctly. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP4: Fix errata i688 with MPU interconnect barriers.Santosh Shilimkar2011-12-081-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4 SOC, intecronnects has many write buffers in the async bridges and they need to be drained before CPU enters into standby state. Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support but OMAP errata i688 (Async Bridge Corruption) needs to be taken care to avoid issues like system freeze, CPU deadlocks, random crashes with register accesses, synchronisation loss on initiators operating on both interconnect port simultaneously. As per the errata, if a data is stalled inside asynchronous bridge because of back pressure, it may be accepted multiple times, creating pointer misalignment that will corrupt next transfers on that data path until next reset of the system (No recovery procedure once the issue is hit, the path remains consistently broken). Async bridge can be found on path between MPU to EMIF and MPU to L3 interconnect. This situation can happen only when the idle is initiated by a Master Request Disconnection (which is trigged by software when executing WFI on CPU). The work-around for this errata needs all the initiators connected through async bridge must ensure that data path is properly drained before issuing WFI. This condition will be met if one Strongly ordered access is performed to the target right before executing the WFI. In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. IO barrier ensure that there is no synchronisation loss on initiators operating on both interconnect port simultaneously. Thanks to Russell for a tip to conver assembly function to C fuction there by reducing 40 odd lines of code from the patch. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: PM: Add WakeupGen module as OMAP gic_arch_extnSantosh Shilimkar2011-12-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | OMAP WakeupGen is the interrupt controller extension used along with ARM GIC to wake the CPU out from low power states on external interrupts. The WakeupGen unit is responsible for generating the wakeup event from the incoming interrupts and enable bits. It is implemented in the MPU always ON power domain. During normal operation, WakeupGen delivers the external interrupts directly to the GIC. WakeupGen specification has one restriction as per Veyron version 1.6. It is SW responsibility to program interrupt enabling/disabling coherently in the GIC and in the WakeupGen enable registers. That is, a given interrupt for a given CPU is either enable at both GIC and WakeupGen, or disable at both, but no mix. That's the reason the WakeupGen is implemented as an extension of GIC. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: PM: Add SAR RAM supportSantosh Shilimkar2011-12-081-0/+30
| | | | | | | | | | | This patch adds SAR RAM support on OMAP4430. SAR RAM used to save and restore the HW context in low power modes. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: Export omap4_get_base*() rather than global address pointersSantosh Shilimkar2011-12-081-1/+6
| | | | | | | | | | | | | | | This patch exports APIs to get base address for GIC distributor, CPU interface, SCU and PL310 L2 Cache which are used in OMAP4 PM code. This was suggested by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exitSantosh Shilimkar2011-12-081-1/+2
| | | | | | | | | | | | | | | | OMAP4 L2X0 initialisation code uses BUG_ON() for the ioremap() failure scenarios. Use WARN_ON() instead and allow graceful function exits. This was suggsted by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* Merge branch 'irqchip-consolidation' of ↵Russell King2011-11-211-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into devel-stable Conflicts: arch/arm/mach-omap2/board-4430sdp.c arch/arm/mach-omap2/board-omap4panda.c arch/arm/mach-omap2/include/mach/omap4-common.h arch/arm/plat-omap/include/plat/irqs.h The changes to omap4-common.h were moved to arch/arm/mach-omap2/common.h and the other trivial conflicts resolved. The now empty ifdef in irqs.h was also eliminated.
| * ARM: omap2plus: remove irq-related global base addressesMarc Zyngier2011-11-151-3/+3
| | | | | | | | | | | | | | After the MULTI_IRQ_HANDLER conversion, a couple of global variables can be removed. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | ARM: 7159/1: OMAP: Introduce local common.h filesTony Lindgren2011-11-171-1/+2
|/ | | | | | | | | | | As suggested by Russell King - ARM Linux <linux@arm.linux.org.uk>, there's no need to keep local prototypes in non-local headers. Add mach-omap1/common.h and mach-omap2/common.h and move the local prototypes there from plat/common.h and mach/omap4-common.h. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* omap: Use separate init_irq functions to avoid cpu_is_omap tests earlyTony Lindgren2011-06-161-5/+5
| | | | | | | | | | | | | This allows us to remove cpu_is_omap calls from init_irq functions. There should not be any need for cpu_is_omap calls as at this point. During the timer init we only care about SoC generation, and not about subrevisions. The main reason for the patch is that we want to initialize only minimal omap specific code from the init_early call. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
* ARM: 6755/1: omap4: l2x0: Populate set_debug() function and enable Errata 727915Santosh Shilimkar2011-03-091-0/+7
| | | | | | | | | | | | | Populate the l2x0 set_debug function pointer with OMAP secure call and enable the PL310 Errata 727915 This patch has dependency on the earlier patch ARM: l2x0: Errata fix for flush by Way operation can cause data corruption Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'omap-for-linus' of ↵Linus Torvalds2011-01-071-7/+23
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (243 commits) omap2: Make OMAP2PLUS select OMAP_DM_TIMER OMAP4: hwmod data: Fix alignment and end of line in structurefields OMAP4: hwmod data: Move the DMA structures OMAP4: hwmod data: Move the smartreflex structures OMAP4: hwmod data: Fix missing SIDLE_SMART_WKUP in smartreflexsysc arm: omap: tusb6010: add name for MUSB IRQ arm: omap: craneboard: Add USB EHCI support omap2+: Initialize serial port for dynamic remuxing for n8x0 omap2+: Add struct omap_board_data and use it for platform level serial init omap2+: Allow hwmod state changes to mux pads based on the state changes omap2+: Add support for hwmod specific muxing of devices omap2+: Add omap_mux_get_by_name OMAP2: PM: fix compile error when !CONFIG_SUSPEND MAINTAINERS: OMAP: hwmod: update hwmod code, data maintainership OMAP4: Smartreflex framework extensions OMAP4: hwmod: Add inital data for smartreflex modules. OMAP4: PM: Program correct init voltages for scalable VDDs OMAP4: Adding voltage driver support OMAP4: Register voltage PMIC parameters with the voltage layer OMAP3: PM: Program correct init voltages for VDD1 and VDD2 ... Fix up trivial conflict in arch/arm/plat-omap/Kconfig
| * omap4: l2x0: Enable early BRESP bitSantosh Shilimkar2010-12-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AXI protocol specifies that the write response can only be sent back to an AXI master when the last write data has been accepted. This optimization enables the PL310 to send the write response of certain write transactions as soon as the store buffer accepts the write address. This behavior is not compatible with the AXI protocol and is disabled by default. You enable this optimization by setting the Early BRESP Enable bit in the Auxiliary Control Register (bit [30]). Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mans Rullgard <mans@mansr.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * omap4: l2x0: Set share override bitSantosh Shilimkar2010-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * omap4: l2x0: enable instruction and data prefetchingMans Rullgard2010-12-181-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling L2 prefetching improves performance as shown on Panda ES2.1 board with mem test, and it has measurable impact on performances. I think we should consider it, even though it damages "writes" a bit. (rebased to k.org) Usually the prefetch is used at both levels together L1 + L2, however, to enable the CP15 prefetch engines, these are under security, and on GP devices, we cannot enable it(e.g. on PandaBoard). However, just enabling PL310 prefetch seems to provide performance improvement, as shown in the data below (from Ubuntu) and would be a great thing to pull in. What prefetch does is enable automatic next line prefetching. With this enabled, whenever the PL310 receives a cachable read request, it automatically prefetches the following cache line as well. Measurement Data: == STOCK 10.10 WITHOUT PATCH ======================== ~# ./memspeed size 8388608 8192k 8M offset 8388608, 0 buffers 0x2aaad000 0x2b2ad000 copy libc 133 MB/s copy Android v5 273 MB/s copy Android NEON 235 MB/s copy INT32 116 MB/s copy ASM ARM 187 MB/s copy ASM VLDM 64 204 MB/s copy ASM VLDM 128 173 MB/s copy ASM VLD1 216 MB/s read ASM ARM 286 MB/s read ASM VLDM 242 MB/s read ASM VLD1 286 MB/s write libc 1947 MB/s write ASM ARM 1943 MB/s write ASM VSTM 1942 MB/s write ASM VST1 1935 MB/s 10.10 + PATCH ============= ~# ./memspeed size 8388608 8192k 8M offset 8388608, 0 buffers 0x2ab17000 0x2b317000 copy libc 129 MB/s copy Android v5 256 MB/s copy Android NEON 356 MB/s copy INT32 127 MB/s copy ASM ARM 321 MB/s copy ASM VLDM 64 337 MB/s copy ASM VLDM 128 321 MB/s copy ASM VLD1 350 MB/s read ASM ARM 496 MB/s read ASM VLDM 470 MB/s read ASM VLD1 488 MB/s write libc 1701 MB/s write ASM ARM 1682 MB/s write ASM VSTM 1693 MB/s write ASM VST1 1681 MB/s Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * omap4: l2x0: Construct the AUXCTRL value using definesSantosh Shilimkar2010-12-181-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | This patch removes the hardcoded value of auxctrl value and construct it using bitfields Bit 25 is reserved and is always set to 1. Same value of this bit is retained in this patch Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: GIC: consolidate gic_cpu_base_addr to common GIC codeRussell King2010-12-141-4/+5
| | | | | | | | | | | | | | | | | | | | Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: GIC: provide a single initialization function for boot CPURussell King2010-12-141-2/+2
|/ | | | | | | | | Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'l2x0-pull-rmk' of ↵Russell King2010-10-281-0/+13
|\ | | | | | | git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into devel-stable
| * omap4: l2x0: Override the default l2x0_disableSantosh Shilimkar2010-10-261-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | The machine_kexec() calls outer_disable which can crash on OMAP4 becasue of trustzone restrictions. This patch overrides the default l2x0_disable with a OMAP4 specific implementation taking care of trustzone Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
* | omap4: l2x0: Fix init parameter for es2.0Santosh Shilimkar2010-09-241-3/+7
|/ | | | | | | | | | On ES2.0 the L2 cache init parameter ineeds to be changed to take care of cache size. The cache size is 1MB on ES2.0 vs 512KB on ES1.0 This patch fixes the init parameter to update the same using dynamic cpu version check Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* omap4: Move SOC specific code from board fileSantosh Shilimkar2010-05-201-0/+72
This patch moves OMAP4 soc specific code from 4430sdp board file. The change is necessary so that newer board support can be added with minimal changes. This will be also problematic for multi-board, multi-omap builds. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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