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The patch enables the HiSi LPC node for hip07, with
the IPMI child device.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in
D05 board.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Enable the NIC and SAS nodes for the hip07-d05 board
to support related functions.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.
Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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