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* arm64: dts: h3ulcb: Provide sd0_uhs nodeSimon Horman2016-12-081-1/+1
| | | | | | | | | Provide separaate sd0 and sd0_uhs nodes rather than duplicate sd0 nodes. Cc: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Fixes: 93373c309a70 ("arm64: dts: h3ulcb: rename SDHI0 pins") Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7796: Add device node for PRRGeert Uytterhoeven2016-11-211-0/+5
| | | | | | | | Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7795: Add device node for PRRGeert Uytterhoeven2016-11-211-0/+5
| | | | | | | | Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: h3ulcb: rename SDHI0 pinsVladimir Barinov2016-11-211-4/+4
| | | | | | | This changes SDHI0 pin names for H3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: h3ulcb: enable SDHI2Vladimir Barinov2016-11-211-0/+43
| | | | | | | This supports SDHI2 for H3ULCB onboard eMMC Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: m3ulcb: enable SDHI2Vladimir Barinov2016-11-211-0/+43
| | | | | | | This supports SDHI2 for M3ULCB onboard eMMC Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: m3ulcb: enable SDHI0Vladimir Barinov2016-11-211-0/+49
| | | | | | | This supports SDHI0 on M3ULCB board SD card slot Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: m3ulcb: enable WDTVladimir Barinov2016-11-211-0/+5
| | | | | | | This supports watchdog timer for M3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: m3ulcb: enable EXTALR clkVladimir Barinov2016-11-211-0/+4
| | | | | | | This enables EXTALR clock that can be used for the watchdog. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: m3ulcb: enable GPIO keysVladimir Barinov2016-11-211-0/+13
| | | | | | | This supports GPIO keys on M3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: m3ulcb: enable GPIO ledsVladimir Barinov2016-11-211-0/+11
| | | | | | | This supports GPIO leds on M3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: m3ulcb: enable SCIF clk and pinsVladimir Barinov2016-11-211-0/+13
| | | | | | | | This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: m3ulcb: initial device treeVladimir Barinov2016-11-212-1/+52
| | | | | | | | | | | Add the initial device tree for the R8A7796 SoC based M3ULCB low cost board (R-Car Starter Kit Pro) This commit supports the following peripherals: - SCIF (console) Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: h3ulcb: update headerVladimir Barinov2016-11-211-1/+1
| | | | | | | This updates H3ULCB device tree header with official board name Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7796: salvator-x: enable I2CUlrich Hecht2016-11-211-0/+12
| | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7796: Enable I2C DMAUlrich Hecht2016-11-211-0/+17
| | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7796: add I2C supportUlrich Hecht2016-11-211-0/+94
| | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: renesas: r8a7796: add SYS-DMAC controller nodesUlrich Hecht2016-11-041-0/+99
| | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7795: salvator-x: add bias setting for usb1_pinsYoshihiro Shimoda2016-11-041-2/+14
| | | | | | | | | Since this board doesn't mount pull-up/down registers for USB1_{OVC,PWEN} pins, we should enable bias setting to pull these pins up/down. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7796: salvator: enable on board eMMCWolfram Sang2016-11-041-1/+43
| | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7795: salvator: enable on-board eMMCWolfram Sang2016-11-041-0/+43
| | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7796: salvator-x: enable UHS for SDHI 0 & 3Simon Horman2016-11-041-2/+20
| | | | | | | Based on work for the r8a7796 by Wolfram Sang. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
* arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3Simon Horman2016-11-041-0/+84
| | | | | | | | | Enable the exposed SD card slots in the DT of the r8a7796/salvator-x. Based on work for the r8a7795/salvator-x by Ai Kyuse. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* arm64: dts: r8a7796: add SDHI nodesSimon Horman2016-10-271-0/+40
| | | | | | | | | | Add SDHI nodes to the DT of the r8a7796 SoC. Based on the DT of the r8a7795 SoC. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* arm64: dts: r8a7795: Remove FCP SoC-specific compatible stringsLaurent Pinchart2016-10-271-12/+12
| | | | | | | | | The SoC-specific compatible strings have been removed from the FCP DT bindings, removed them from the device tree. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7795: salvator-x: Add DU LVDS output endpointLaurent Pinchart2016-10-171-0/+4
| | | | | | | | Declaring the endpoint makes LVDS enablement easier by just including the corresponding panel's dtsi file. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7796: salvator-x: Populate EXTALRGeert Uytterhoeven2016-10-171-0/+4
| | | | | | | | | It can be used for the watchdog. Based on similar work for r8a7795/salvator-x by Wolfram Sang. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* arm64: dts: r8a7795: salvator-x: enable UHS for SDHI 0 & 3Wolfram Sang2016-10-171-2/+20
| | | | | | Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* Merge branch 'for-4.9' of ↵Linus Torvalds2016-10-142-1/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata Pull libata updates from Tejun Heo: - Write same support added - Minor ahci MSIX irq handling updates - Non-critical SCSI command translation fixes - Controller specific changes * 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC" libata: remove <asm-generic/libata-portmap.h> libata: remove unused definitions from <asm/libata-portmap.h> pata_at91: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR ata: Replace BUG() with BUG_ON(). ata: sata_mv: Replacing dma_pool_alloc and memset with a single call dma_pool_zalloc. libata: Some drives failing on SCT Write Same ahci: use pci_alloc_irq_vectors libata: SCT Write Same handle ATA_DFLAG_PIO libata: SCT Write Same / DSM Trim libata: Add support for SCT Write Same libata: Safely overwrite attached page in WRITE SAME xlat ahci: also use a per-port lock for the multi-MSIX case ARM: dts: STiH407-family: Add ports-implemented property in sata nodes ahci: st: Add ports-implemented property in support ahci: qoriq: enable snoopable sata read and write ahci: qoriq: adjust sata parameter libata-scsi: fix MODE SELECT translation for Control mode page libata-scsi: use u8 array to store mode page copy
| * Merge branch 'master' into for-4.9Tejun Heo2016-09-062-0/+5
| |\
| * | ahci: qoriq: enable snoopable sata read and writeTang Yuantian2016-08-102-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the SATA IP on the qoriq SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
* | | Merge branch 'next' of ↵Linus Torvalds2016-10-122-2/+244
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux Pull thermal managament updates from Zhang Rui: - Enhance thermal "userspace" governor to export the reason when a thermal event is triggered and delivered to user space. From Srinivas Pandruvada - Introduce a single TSENS thermal driver for the different versions of the TSENS IP that exist, on different qcom msm/apq SoCs'. Support for msm8916, msm8960, msm8974 and msm8996 families is also added. From Rajendra Nayak - Introduce hardware-tracked trip points support to the device tree thermal sensor framework. The framework supports an arbitrary number of trip points. Whenever the current temperature is changed, the trip points immediately below and above the current temperature are found, driver callback is invoked to program the hardware to get notified when either of the two trip points are triggered. Hardware-tracked trip points support for rockchip thermal driver is also added at the same time. From Sascha Hauer, Caesar Wang - Introduce a new thermal driver, which enables TMU (Thermal Monitor Unit) on QorIQ platform. From Jia Hongtao - Introduce a new thermal driver for Maxim MAX77620. From Laxman Dewangan - Introduce a new thermal driver for Intel platforms using WhiskeyCove PMIC. From Bin Gao - Add mt2701 chip support to MTK thermal driver. From Dawei Chien - Enhance Tegra thermal driver to enable soctherm node and set "critical", "hot" trips, for Tegra124, Tegra132, Tegra210. From Wei Ni - Add resume support for tango thermal driver. From Marc Gonzalez - several small fixes and improvements for rockchip, qcom, imx, rcar, mtk thermal drivers and thermal core code. From Caesar Wang, Keerthy, Rocky Hao, Wei Yongjun, Peter Robinson, Bui Duc Phuc, Axel Lin, Hugh Kang * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (48 commits) thermal: int3403: Process trip change notification thermal: int340x: New Interface to read trip and notify thermal: user_space gov: Add additional information in uevent thermal: Enhance thermal_zone_device_update for events arm64: tegra: set hot trips for Tegra210 arm64: tegra: set critical trips for Tegra210 arm64: tegra: add soctherm node for Tegra210 arm64: tegra: set hot trips for Tegra132 arm64: tegra: set critical trips for Tegra132 arm64: tegra: use tegra132-soctherm for Tegra132 arm: tegra: set hot trips for Tegra124 arm: tegra: set critical trips for Tegra124 thermal: tegra: add hw-throttle for Tegra132 thermal: tegra: add hw-throttle function of: Add bindings of hw throttle for Tegra soctherm thermal: mtk_thermal: Check return value of devm_thermal_zone_of_sensor_register thermal: Add Mediatek thermal driver for mt2701. dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: max77620: Add thermal driver for reporting junction temp thermal: max77620: Add DT binding doc for thermal driver ...
| * | | arm64: tegra: set hot trips for Tegra210Wei Ni2016-09-271-9/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: set critical trips for Tegra210Wei Ni2016-09-271-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: add soctherm node for Tegra210Wei Ni2016-09-271-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: set hot trips for Tegra132Wei Ni2016-09-271-9/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: set critical trips for Tegra132Wei Ni2016-09-271-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra132, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: use tegra132-soctherm for Tegra132Wei Ni2016-09-271-2/+34
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | The Tegra132 has the specific settings for soctherm, so change to use campatible "nvidia,tegra132-soctherm" for it. And adds cpu, gpu, mem and pllx thermal zones. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
* | | Merge tag 'armsoc-late' of ↵Linus Torvalds2016-10-0811-8/+1241
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an automotive SoC similar to the ⅹ8a7795 chip we already support, but the dts changes rely on a clock driver change that has been merged for v4.9 through the clk tree. - The Amlogic meson-gxbb (S905) platform gains support for a few drivers merged through our tree, in particular the network and usb driver changes are required and included here, and also the clk tree changes. - The Allwinner platforms have seen a large-scale change to their clk drivers and the dts file updates must come after that. This includes the newly added Nextthing GR8 platform, which is derived from sun5i/A13. - Some integrator (arm32) changes rely on clk driver changes. - A single patch for lpc32xx has no such dependency but wasn't added until just before the merge window" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) ARM: dts: lpc32xx: add device node for IRAM on-chip memory ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03 ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board ARM: dts: sun8i: add pinmux for UART1 at PG dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC dts: sun8i-h3: add pinmux definitions for I2C0-2 dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux dts: sun8i-h3: add pinmux definitions for UART2-3 ARM: dts: sun9i: a80-optimus: Disable EHCI1 ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04 ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03 ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes ...
| * \ \ Merge tag 'amlogic-dt64-2' of ↵Arnd Bergmann2016-09-195-3/+273
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late Pull "Amlogic 64-bit DT changes for v4.9, round 2" from Kevin Hilman: Primarily adding support for newly added drivers - USB host - I2C - SPI flash controller - PWM - mailbox, MHU - pinctrl: add pins for SPI, I2C, SDIO and then enabling these drivers on various boards. * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes ARM64: dts: meson-gxbb-p20x: Enable USB Nodes ARM64: dts: meson-gxbb: add USB Nodes ARM64: dts: gxbb: add i2c bus ARM64: dts: meson-gxbb: add I2C nodes ARM64: dts: meson-gxbb: add pins for I2C ARM64: dts: meson-gxbb: Add SPIFC node ARM64: dts: meson-gxbb: add the SDIO pins ARM64: dts: amlogic: add spi nor pins ARM64: dts: meson-gxbb: use the new GXBB DWMAC glue driver ARM64: dts: meson-gxbb: Add Meson GXBB PWM Controller nodes ARM64: dts: meson-gxbb: Add Meson MHU Node ARM64: dts: amlogic: enable ethernet on all Tronsmart Vega S95 devices
| | * | | ARM64: dts: meson-gxbb-vega-s95: Enable USB NodesMartin Blumenstingl2016-09-161-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb-p20x: Enable USB NodesJerome Brunet2016-09-161-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [khilman: rename vbus node to match P200 schematics] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: add USB NodesMartin Blumenstingl2016-09-141-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the nodes for the dwc2 USB controller and the related USB PHYs. Currently we force usb0 to host mode because OTG is currently not working in our PHY driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: gxbb: add i2c busJerome Brunet2016-09-142-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nodes for i2c bus on gxbb based platforms. On the OdroidC2 (I2C A) and P200 (I2C B), the pull-up resistor are present directly on the board. This indicates that these pins are dedicated to i2c. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: add I2C nodesNeil Armstrong2016-09-141-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: add pins for I2CJerome Brunet2016-09-141-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: Add SPIFC nodeNeil Armstrong2016-09-141-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: add the SDIO pinsNeil Armstrong2016-09-141-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is used to configure the pins of the sd_emmc_a controller to which an SDIO module is connected (when available). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: amlogic: add spi nor pinsJerome Brunet2016-09-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: use the new GXBB DWMAC glue driverMartin Blumenstingl2016-09-141-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amlogic reference driver uses the "mc_val" devicetree property to configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic values for this configuration. According to the datasheet the PRG_ETHERNET_ADDR0 register is at address 0xc8834108. However, the reference driver uses 0xc8834540 instead. According to my tests, the value from the reference driver is correct. No changes are required to the board dts files because the only required configuration option is the phy-mode, which had to be configured correctly before as well. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-09-15 01:43:23 +0200