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* ASoC: fsi: PortA/B information was controlled by sh_fsi_port_infoKuninori Morimoto2012-02-032-29/+19Star
| | | | | | | | | | | Current FSI got each PortA/B parameter by porta_flags/portb_flags from platform. And .set_rate function was shared for PortA/B. This structure was not readable and not flexible. This patch adds sh_fsi_port_info, and its own settings was added on each platform. it is preparation for DMAEngine support Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* Merge tag 'v3.3-rc2' into for-3.4Mark Brown2012-02-01127-1152/+761Star
|\ | | | | | | | | | | | | | | | | | | | | A reasonable amount of new development is causing fiddly merge conflicts between different resource management changes (mostly fixing bugs in resource management due to noticing things while doing enhancements in the same area). Linux 3.3-rc2 .. several days delayed. No reason, I just didn't think of it.
| * Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2012-01-2858-378/+208Star
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: (31 commits) ARM: 7304/1: ioremap: fix boundary check when reusing static mapping ARM: 7301/1: Rename the T() macro to TUSER() to avoid namespace conflicts ARM: 7299/1: ftrace: clear zero bit in reported IPs for Thumb-2 ARM: 7298/1: realview: fix mapping of MPCore private memory region PCMCIA: fix sa1111 oops on remove ARM: 7288/1: mach-sa1100: add missing module_init() call ARM: 7297/1: smp_twd: make sure timer is stopped before registering it ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards ARM: 7295/1: cortex-a7: move proc_info out of !CONFIG_ARM_LPAE block ARM: 7293/1: logical_cpu_map: decouple CPU mapping from SMP ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs ARM: 7290/1: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary ARM: 7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes MFD: ucb1x00-ts: fix resume failure MFD: ucb1x00-core: fix gpiolib direction_output handling MFD: ucb1x00-core: fix missing restore of io output data on resume MFD: mcp-core: fix mcp_priv() to be more type safe MFD: mcp-core: fix complaints from the genirq layer Revert "ARM: sa11x0: Implement autoloading of codec and codec pdata for mcp bus." Revert "ARM: sa1100: Refactor mcp-sa11x0 to use platform resources." ... Fix up conflict due to arch/arm/mach-mx5/Kconfig having been merged into mach-imx5 (commit 784a90c0a7d8: "ARM i.MX: Merge i.MX5 support into mach-imx"), but the ARM_L1_CACHE_SHIFT_6 entry was moved to be driven by the CPU_V7 logic from it in the old location in rmk's branch (commit a092f2b15399: "ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs").
| | * ARM: 7304/1: ioremap: fix boundary check when reusing static mappingPawel Moll2012-01-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 576d2f2525612ecb5af029a76f21f22a3b82563d "ARM: add generic ioremap optimization by reusing static mappings" ioremap() is trying to reuse existing static mapping when possible. The condition checking boundaries of the requested and existing mappings didn't take in-page offset into consideration though, which lead to obscure and hard to debug problems when requested mapping crossed end of the static one. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * Merge branch 'sa11x0-mcp-fixes' into fixesRussell King2012-01-268-86/+3Star
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| | | * Revert "ARM: sa11x0: Implement autoloading of codec and codec pdata for mcp ↵Russell King2012-01-207-20/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bus." This reverts commit 5dd7bf59e0e8563265b3e5b33276099ef628fcc7. Conflicts: scripts/mod/file2alias.c This change is wrong on many levels. First and foremost, it causes a regression. On boot on Assabet, which this patch gives a codec id of 'ucb1x00', it gives: ucb1x00 ID not found: 1005 0x1005 is a valid ID for the UCB1300 device. Secondly, this patch is way over the top in terms of complexity. The only device which has been seen to be connected with this MCP code is the UCB1x00 (UCB1200, UCB1300 etc) devices, and they all use the same driver. Adding a match table, requiring the codec string to match the hardware ID read out of the ID register, etc is completely over the top when we can just read the hardware ID register.
| | | * Revert "ARM: sa1100: Refactor mcp-sa11x0 to use platform resources."Russell King2012-01-207-66/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit af9081ae64b941d32239b947882cd59ba855c5db. This revert is necessary to revert 5dd7bf59e0e8563265b3e5b33276099ef628fcc7.
| | * | ARM: 7301/1: Rename the T() macro to TUSER() to avoid namespace conflictsCatalin Marinas2012-01-257-79/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This macro is used to generate unprivileged accesses (LDRT/STRT) to user space. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7299/1: ftrace: clear zero bit in reported IPs for Thumb-2Rabin Vincent2012-01-251-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dynamic ftrace ops startup test currently fails on Thumb-2 kernels: Testing tracer function: PASSED Testing dynamic ftrace: PASSED Testing dynamic ftrace ops #1: (0 0 0 0 0) FAILED! This is because while the addresses in the mcount records do not have the zero bit set, the IP reported by the mcount call does have it set (because it is copied from the LR). This mismatch causes the ops filtering in ftrace_ops_list_func() to not call the relevant tracers. Fix this by clearing the zero bit before adjusting the LR for the mcount instruction size. Also, combine the mov+sub into a single sub instruction. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7298/1: realview: fix mapping of MPCore private memory regionMarc Zyngier2012-01-254-25/+19Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 0536bdf33faf (ARM: move iotable mappings within the vmalloc region), the RealView PB11MP cannot boot anymore. This is caused by the way the mappings are described on this platform (define replaced by hex values for clarity): { /* GIC CPU interface mapping */ .virtual = IO_ADDRESS(0x1F000100), .pfn = __phys_to_pfn(0x1F000100), .length = SZ_4K, .type = MT_DEVICE, }, { /* GIC distributor mapping */ .virtual = IO_ADDRESS(0x1F001000), .pfn = __phys_to_pfn(0x1F001000), .length = SZ_4K, .type = MT_DEVICE, } The first mapping ends up reserving two pages, and clashes with the second one, which triggers a BUG_ON in vm_area_add_early(). In order to solve this problem, treat the MPCore private memory region (containing the SCU, the GIC and the TWD) as a single region, as described in the TRM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/CACGDJJC.html The EB11MP is converted the same way, even if it manages to avoid the problem. Tested on both PB11MP and EB11MP. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7288/1: mach-sa1100: add missing module_init() callLinus Walleij2012-01-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Jornada SSP driver is supposed to be initialized by a module_init() call, but it was missed at some merge point. Since the driver mostly pass calls through it magically works anyway, but needs to be rectified. Cc: Kristoffer Ericson <kristoffer.ericson@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7297/1: smp_twd: make sure timer is stopped before registering itMarc Zyngier2012-01-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On secondary CPUs, the Timer Control Register is not reset to a sane value before the timer is registered, and the TRM doesn't seem to indicate any reset value either. In some cases, the kernel will take an interrupt too early, depending on what junk was present in the registers at reset time. The fix is to set the Timer Control Register to 0 before registering the clock_event_device and enabling the interrupt. Problem seen on VE (Cortex A5) and Tegra. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guardsWill Deacon2012-01-231-6/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On v7, we use the same cache maintenance instructions for data lines as for unified lines. This was not the case for v6, where HARVARD_CACHE was defined to indicate the L1 cache topology. This patch removes the erroneous compile-time check for HARVARD_CACHE in proc-v7.S, ensuring that we perform I-side invalidation at boot. Reported-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: stable <stable@vger.kernel.org> Acked-by: Catalin Marinas <Catalin.Marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7295/1: cortex-a7: move proc_info out of !CONFIG_ARM_LPAE blockWill Deacon2012-01-231-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The merging of commits 1b6ba46b ("ARM: LPAE: MMU setup for the 3-level page table format") and b4244738 ("ARM: 7202/1: Add Cortex-A7 proc info") during the merge window ended up putting the Cortex-A7 proc_info into a code block guarded by !CONFIG_ARM_LPAE. This makes Cortex-A7 platforms unbootable when LPAE is enabled. This patch moves the proc_info structure for Cortex-A7 outside of the guarded block. Cc: Pawel Moll <pawel.moll@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7293/1: logical_cpu_map: decouple CPU mapping from SMPWill Deacon2012-01-2318-31/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that the logical CPU mapping is useful even when !CONFIG_SMP for manipulation of devices like interrupt and power controllers when running a UP kernel on a CPU other than 0. This can happen when kexecing a UP image from an SMP kernel. In the future, multi-cluster systems running AMP configurations will require something similar for mapping cluster IDs, so it makes sense to decouple this logic in preparation for this support. Acked-by: Yang Bai <hamo.by@gmail.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reported-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUsWill Deacon2012-01-234-6/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To ensure correct alignment of cacheline-aligned data, the maximum cacheline size needs to be known at compile time. Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely that there will be future ARMv7 implementations with the same line size) then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline size. For CPUs with smaller caches, this will result in some harmless padding but will help with single zImage work and avoid hitting subtle bugs with misaligned data structures. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7290/1: vmlinux.lds.S: align the exception fixup table to a 4-byte boundaryWill Deacon2012-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exception fixup table is currently aligned to a 32-byte boundary. Whilst this won't cause any problems, the exception_table_entry structures contain only a pair of unsigned longs, so 4-byte alignment is all that is required. If the table was walked from start to end, cacheline alignment may bring some performance benefits, but since a binary search is used, the access pattern is random and will not benefit from a stricter alignment. Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytesWill Deacon2012-01-231-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The linker script assumes a cacheline size of 32 bytes when aligning the .data..cacheline_aligned and .data..percpu sections. This patch updates the script to use L1_CACHE_BYTES, which should be set to 64 on platforms that require it. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7277/1: setup.c: Fix build warning by removing unneeded header fileFabio Estevam2012-01-191-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build warning: CC arch/arm/kernel/setup.o In file included from arch/arm/kernel/setup.c:39: arch/arm/include/asm/elf.h:102:1: warning: "vmcore_elf64_check_arch" redefined In file included from arch/arm/kernel/setup.c:24: include/linux/crash_dump.h:30:1: warning: this is the location of the previous definition Since commit 93a72052 (crash_dump: export is_kdump_kernel to modules, consolidate elfcorehdr_addr, setup_elfcorehdr and saved_max_pfn) the inclusion of <linux/crash_dump.h> is no longer needed. Remove the inclusion of <linux/crash_dump.h> and the build warning is fixed. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7279/1: standardize /proc/iomem "Kernel code" nameKees Cook2012-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All other ports use "Kernel code" to identify the Kernel text segment in /proc/iomem. Change the ARM resources to do the same. Signed-off-by: Kees Cook <keescook@chromium.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: fix rcu stalls on SMP platformsRussell King2012-01-191-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can stall RCU processing on SMP platforms if a CPU sits in its idle loop for a long time. This happens because we don't call irq_enter() and irq_exit() around generic_smp_call_function_interrupt() and friends. Add the necessary calls, and remove the one from within ipi_timer(), so that they're all in a common place. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: vexpress: fix two section mismatch warningsRussell King2012-01-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WARNING: vmlinux.o(.text+0x1bc9c): Section mismatch in reference from the function ct_ca9x4_init_cpu_map() to the function .init.text:scu_get_core_count() The function ct_ca9x4_init_cpu_map() references the function __init scu_get_core_count(). WARNING: vmlinux.o(.text+0x1bce8): Section mismatch in reference from the function ct_ca9x4_init_cpu_map() to the function .init.text:set_smp_cross_call() The function ct_ca9x4_init_cpu_map() references the function __init set_smp_cross_call(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: fix a section mismatch warning with our use of memblockRussell King2012-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 716a3dc2008 (ARM: Add arm_memblock_steal() to allocate memory away from the kernel) added a function which calls memblock_alloc(). This causes a section conflict: WARNING: vmlinux.o(.text+0xc614): Section mismatch in reference from the function arm_memblock_steal() to the function .init.text:memblock_alloc() The function arm_memblock_steal() references the function __init memblock_alloc(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: sa11x0: fix section mismatch in cpu-sa1100.cRussell King2012-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WARNING: arch/arm/mach-sa1100/built-in.o(.data+0x11b8): Section mismatch in reference from the variable sa1100_driver to the function .init.text:sa1100_cpu_init() The variable sa1100_driver references the function __init sa1100_cpu_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: sa11x0: fix collie build errorRussell King2012-01-191-3/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | f408c985cefc (GPIO: sa1100: implement proper gpiolib gpio_to_irq conversion) made gpio_to_irq() a function. This breaks collie where it's used to initialize some static data. Fix that by moving the initialization to the init code. arch/arm/mach-sa1100/collie.c:139: error: initializer element is not constant arch/arm/mach-sa1100/collie.c:139: error: (near initialization for 'collie_power_resource[0].start') arch/arm/mach-sa1100/collie.c:140: error: initializer element is not constant arch/arm/mach-sa1100/collie.c:140: error: (near initialization for 'collie_power_resource[0].end') Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | Revert "RTC: sa1100: support sa1100, pxa and mmp soc families"Russell King2012-01-192-40/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7cea00657dd4daef66ad95e976d5d67ed94cb97e. The sa1100 cleanups fatally broke the SA1100 RTC driver - the first hint that something is wrong are these compiler warnings: drivers/rtc/rtc-sa1100.c:42:1: warning: "RCNR" redefined In file included from arch/arm/mach-sa1100/include/mach/hardware.h:73, from drivers/rtc/rtc-sa1100.c:35: arch/arm/mach-sa1100/include/mach/SA-1100.h:877:1: warning: this is the location of the previous definition drivers/rtc/rtc-sa1100.c:43:1: warning: "RTAR" redefined arch/arm/mach-sa1100/include/mach/SA-1100.h:876:1: warning: this is the location of the previous definition drivers/rtc/rtc-sa1100.c:44:1: warning: "RTSR" redefined arch/arm/mach-sa1100/include/mach/SA-1100.h:879:1: warning: this is the location of the previous definition drivers/rtc/rtc-sa1100.c:45:1: warning: "RTTR" redefined arch/arm/mach-sa1100/include/mach/SA-1100.h:878:1: warning: this is the location of the previous definition drivers/rtc/rtc-sa1100.c:47:1: warning: "RTSR_HZE" redefined arch/arm/mach-sa1100/include/mach/SA-1100.h:891:1: warning: this is the location of the previous definition drivers/rtc/rtc-sa1100.c:48:1: warning: "RTSR_ALE" redefined arch/arm/mach-sa1100/include/mach/SA-1100.h:890:1: warning: this is the location of the previous definition drivers/rtc/rtc-sa1100.c:49:1: warning: "RTSR_HZ" redefined arch/arm/mach-sa1100/include/mach/SA-1100.h:889:1: warning: this is the location of the previous definition drivers/rtc/rtc-sa1100.c:50:1: warning: "RTSR_AL" redefined arch/arm/mach-sa1100/include/mach/SA-1100.h:888:1: warning: this is the location of the previous definition and the second problem, which is far more severe, are the different register layouts, resulting in the wrong registers being read on SA11x0 platforms. This patch adds: #define RCNR 0x00 /* RTC Count Register */ #define RTAR 0x04 /* RTC Alarm Register */ #define RTSR 0x08 /* RTC Status Register */ #define RTTR 0x0c /* RTC Timer Trim Register */ but the SA11x0 registers are: #define RTAR __REG(0x90010000) /* RTC Alarm Reg. */ #define RCNR __REG(0x90010004) /* RTC CouNt Reg. */ #define RTTR __REG(0x90010008) /* RTC Trim Reg. */ #define RTSR __REG(0x90010010) /* RTC Status Reg. */
| | * | Revert "ARM: pxa: add dummy clock for sa1100-rtc"Russell King2012-01-196-8/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7557c175f60d8d40baf16b22caf79beadef8f081. This revert is necessary to revert the broken "RTC: sa1100: support sa1100, pxa and mmp soc families" change.
| | * | Revert "ARM: sa1100: clean up of the clock support"Russell King2012-01-192-67/+26Star
| | |/ | | | | | | | | | | | | | | | | | | This reverts commit edf3ff5bac2582b57de4e7c6569fee5d7c1c0a42. This revert is necessary to revert the broken "RTC: sa1100: support sa1100, pxa and mmp soc families" change.
| * | Merge tag 'fixes-for-linus' of ↵Linus Torvalds2012-01-2832-216/+163Star
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc arm-soc fixes for 3.3-rc: AT91 needed reset fixes which resulted in some minor code refactoring, it also adds a feature-removal for one of their platforms for 3.4. The USB patches have been acked by Greg K-H. i.MX and ux500 both have some minor fixes, nothing controversial. * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arch/arm/mach-imx/mach-mx53_ard.c: add missing iounmap ARM: imx: iomux-v1.h: Fix build error due to __init annotation ARM: at91: Fix at91sam9g45 and at91cap9 reset ARM: at91: make rstc soc independent ARM: at91: introduce AT91_SAM9_ALT_RESET to select the at91sam9 alternative reset ARM: at91: merge at91cap9_ddrsdr.h in at91sam9_ddrsdr.h ARM: at91: fix cap9 ddrsdr register ARM/USB: at91/ohci-at91: rename vbus_pin_inverted to vbus_pin_active_low USB: at91: fix clk_get error handling ARM: at91: removal of CAP9 SoC family ARM: at91: fix at91rm9200 soc subtype handling mach-ux500: no MMC_CAP_SD_HIGHSPEED on Snowball mach-ux500: enable ARM errata 764369 mach-ux500: do not override outer.inv_all mach-ux500: musb: now musb is always in OTG mode ARM: imx6: add missing twd_clk for imx6q clock
| | * \ Merge branch 'imx-fixes' of git://git.pengutronix.de/git/imx/linux-2.6 into ↵Olof Johansson2012-01-272-2/+4
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes * 'imx-fixes' of git://git.pengutronix.de/git/imx/linux-2.6: arch/arm/mach-imx/mach-mx53_ard.c: add missing iounmap ARM: imx: iomux-v1.h: Fix build error due to __init annotation
| | | * | arch/arm/mach-imx/mach-mx53_ard.c: add missing iounmapJulia Lawall2012-01-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing iounmap in error handling code, in a case where the function already preforms iounmap on some other execution path. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e; statement S,S1; int ret; @@ e = \(ioremap\|ioremap_nocache\)(...) ... when != iounmap(e) if (<+...e...+>) S ... when any when != iounmap(e) *if (...) { ... when != iounmap(e) return ...; } ... when any iounmap(e); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | | * | ARM: imx: iomux-v1.h: Fix build error due to __init annotationFabio Estevam2012-01-261-1/+1
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build error found when building imx_v4_v5_defconfig: CC arch/arm/mach-imx/mach-imx27ipcam.o In file included from arch/arm/plat-mxc/include/mach/iomux-mx27.h:23, from arch/arm/mach-imx/mach-imx27ipcam.c:22: arch/arm/plat-mxc/include/mach/iomux-v1.h:99: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'imx_iomuxv1_init' Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * | Merge branch 'fixes-for-arm-soc' of ↵Olof Johansson2012-01-274-47/+10Star
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into fixes * 'fixes-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: mach-ux500: no MMC_CAP_SD_HIGHSPEED on Snowball mach-ux500: enable ARM errata 764369 mach-ux500: do not override outer.inv_all mach-ux500: musb: now musb is always in OTG mode
| | | * | mach-ux500: no MMC_CAP_SD_HIGHSPEED on SnowballPhilippe Langlais2012-01-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMC_CAP_SD_HIGHSPEED is not supported on Snowball board resulting on initialization errors. Cc: stable@kernel.org Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Fredrik Soderstedt <fredrik.soderstedt@stericsson.com> Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | | * | mach-ux500: enable ARM errata 764369Srinidhi KASAGAR2012-01-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This applies ARM errata 764369 for all ux500 platforms. Cc: stable@kernel.org Signed-off-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | | * | mach-ux500: do not override outer.inv_allsrinidhi kasagar2012-01-201-41/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Invalidating outer cache without disabling it is a big nono, and so, remove the machine specific outer.inv_all And at the same time it does not prevent us overriding outer.disable as we do not have any such secure SMI to handle the same while kexec disables the outer cache. Signed-off-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | | * | mach-ux500: musb: now musb is always in OTG modePhilippe Langlais2012-01-201-6/+0Star
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is needed after 622859634 "usb: musb: drop a gigantic amount of ifdeferry", where CONFIG_USB_MUSB_PERIPHERAL & CONFIG_USB_MUSB_HOST has been removed. Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | Merge branch 'imx6/fixes' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Olof Johansson2012-01-271-0/+11
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into fixes * 'imx6/fixes' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: imx6: add missing twd_clk for imx6q clock
| | | * | ARM: imx6: add missing twd_clk for imx6q clockShawn Guo2012-01-201-0/+11
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 5def51b (ARM: 7211/1: smp_twd: get the rate from a clock) hitting mainline, if we do not have a twd_clk for lookup, we will see the following error message in boot log. smp_twd: clock not found: -2 Actually we should add this clock regardless of the error message, so that we can: * Avoid the local timer calibrating at boot time * Make the local timer cpufreq aware on imx6q Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: at91: Fix at91sam9g45 and at91cap9 resetJean-Christophe PLAGNIOL-VILLARD2012-01-206-13/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As on the other sam9 we need to cleanly shutdown the DDRAM before rebooting. On those SoC the SDRAM/DDRAM controller is different. So, the assembly code ends up being not cleanly combined with previous at91sam9_alt_restart function. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | ARM: at91: make rstc soc independentJean-Christophe PLAGNIOL-VILLARD2012-01-2017-20/+42
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | ARM: at91: introduce AT91_SAM9_ALT_RESET to select the at91sam9 alternative ↵Jean-Christophe PLAGNIOL-VILLARD2012-01-202-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | reset Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | ARM: at91: merge at91cap9_ddrsdr.h in at91sam9_ddrsdr.hJean-Christophe PLAGNIOL-VILLARD2012-01-204-129/+26Star
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | ARM: at91: fix cap9 ddrsdr registerJean-Christophe PLAGNIOL-VILLARD2012-01-201-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix AT91_DDRSDRC_MODE it's 3bit add missing AT91_DDRSDRC_NR_14, AT91_DDRSDRC_DBW (16 and 32 bits support) Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | ARM/USB: at91/ohci-at91: rename vbus_pin_inverted to vbus_pin_active_lowJean-Christophe PLAGNIOL-VILLARD2012-01-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows to configure independently the vbus_pin associated with each port. Matches usual naming scheme. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Cc: linux-usb@vger.kernel.org
| | * | ARM: at91: fix at91rm9200 soc subtype handlingNicolas Ferre2012-01-201-2/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently setting it to PQFP changes subtype to BGA as subtypes are swapped in at91rm9200_set_type(). Wrong subtype causes GPIO bank D not to work at all. After this fix, subtype is still set as unknown. But board code should fill it in with proper value. Another information is thus printed. Bug discovery and first implementation made by Veli-Pekka Peltola. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: stable <stable@vger.kernel.org>
| * | Merge tag 'arm-soc-imx-move' of ↵Linus Torvalds2012-01-2339-559/+391Star
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Consolidate i.MX 5 platforms to be under the new shared i.MX 3/5/6 tree. * tag 'arm-soc-imx-move' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM i.MX: Update defconfig ARM i.MX: Merge i.MX5 support into mach-imx ARM i.MX5: remove unnecessary includes from board files Fix up fairly trivial conflicts due to various changes nearby in arch/arm/{mach,plat}-imx/{Kconfig,Makefile} Pull request had been sent to the wrong email address, but happened before the merge window closed. I'm merging the MX 5 consolidation, since it apparently will help the next development window and will avoid conflicts later as per Arnd.
| | * ARM i.MX: Update defconfigSascha Hauer2011-11-162-170/+35Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | This updates the defconfig for i.MX3, i.MX5 and i.MX6. - all these can be compiled together now, so remove mx3_defconfig and mx5_defconfig and introduce a imx_v6_v7_defconfig instead. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * ARM i.MX: Merge i.MX5 support into mach-imxSascha Hauer2011-11-1637-385/+356Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the contents of arch/arm/mach-mx5 to arch/arm/mach-imx and adjusts the Makefile/Kconfig entries in a way that it's possible to compile i.MX5 together with i.MX3/6. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
| | * ARM i.MX5: remove unnecessary includes from board filesSascha Hauer2011-11-104-4/+0Star
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-13 05:20:37 +0200