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| * MIPS: DEC: Only select the R4k clock event/source on R4k systemsMaciej W. Rozycki2014-05-301-2/+2
| | | | | | | | | | | | | | | | | | | | R3k systems have no R4k timer so there's no point in pulling code that's going to be dead. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Support upto 256 CPUsJayachandran C2014-05-301-2/+2
| | | | | | | | | | | | | | | | | | This is needed for two node XLP9xx configurations. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6860/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Enable the BPF_JIT symbol for MIPSMarkos Chandras2014-05-301-0/+1
| | | | | | | | | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6743/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into ↵Ralf Baechle2014-05-291-2/+13
| |\ | | | | | | | | | mips-for-linux-next
| | * MIPS: include cpuidle Kconfig menuPaul Burton2014-05-281-2/+6
| | | | | | | | | | | | | | | | | | | | | This patch simply includes the cpuidle Kconfig entries in preparation for cpuidle drivers used on MIPS systems. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * MIPS: smp-cps: hotplug supportPaul Burton2014-05-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for offlining CPUs via hotplug when using the CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2 things will happen: - If the CPU is part of a core which implements the MT ASE and there is at least one other VPE online within that core then the VPE will be halted by settings its TCHalt bit. - Otherwise if supported the core will be powered down via the CPC. - Otherwise the CPU will hang by executing an infinite loop. Bringing CPUs back online is then a process of either clearing the appropriate VPEs TCHalt bit or powering up the appropriate core via the CPC. Throughout the process the struct core_boot_config vpe_mask field must be maintained such that mips_cps_boot_vpes will start & stop the correct VPEs. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * MIPS: pm-cps: add PM state entry code for CPS systemsPaul Burton2014-05-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds code to generate entry & exit code for various low power states available on systems based around the MIPS Coherent Processing System architecture (ie. those with a Coherence Manager, Global Interrupt Controller & for >=CM2 a Cluster Power Controller). States supported are: - Non-coherent wait. This state first leaves the coherent domain and then executes a regular MIPS wait instruction. Power savings are found from the elimination of coherency interventions between the core and any other coherent requestors in the system. - Clock gated. This state leaves the coherent domain and then gates the clock input to the core. This removes all dynamic power from the core but leaves the core at the mercy of another to restart its clock. Register state is preserved, but the core can not service interrupts whilst its clock is gated. - Power gated. This deepest state removes all power input to the core. All register state is lost and the core will restart execution from its BEV when another core powers it back up. Because register state is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP implementation in order for the core to exit the state successfully. The code will detect which states are available on the current system during boot & generate the entry/exit code for those states. This will be used by cpuidle & hotplug implementations. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * MIPS: support for generic clockevents broadcastPaul Burton2014-05-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for generic clockevents broadcast using the a dummy clockevent device and the tick_broadcast function introduced by commit 12ad10004645 "clockevents: Add generic timer broadcast function". Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * MIPS: PM: Add CPU PM callbacks for general CPU contextJames Hogan2014-04-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CPU power management notifier callback for preserving general CPU context. The CPU PM callbacks will be triggered by the powering down of CPU cores, for example by cpuidle drivers & in the future by suspend to RAM implementations. The current state preserved is mostly related to the process context: - FPU - DSP - ASID - UserLocal - Watch registers Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: SNI: Remove USE_GENERIC_EARLY_PRINTK_8250Thomas Bogendoerfer2014-05-281-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SNI RM code has its own EARLY_PRINTK support no need for some generic 8250 stuff. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6715/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Kconfig: Make MIPS_MT_SMP a regular Kconfig symbolMarkos Chandras2014-05-241-14/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the removal of SMTC, MIPS_MT_SMP is the only available MT/SMP option so make it a regular Kconfig symbol. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6720/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: MT: Remove SMTC supportRalf Baechle2014-05-241-45/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Disable MIPS16/microMIPS crap for platforms not supporting these ASEs.Ralf Baechle2014-05-231-0/+17
| |/ | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* / MIPS: KVM: Override guest kernel timer frequency directlyJames Hogan2014-05-301-6/+6
|/ | | | | | | | | | | | | | | | | | | | | | | The KVM_HOST_FREQ Kconfig symbol was used by KVM guest kernels to override the timer frequency calculation to a value based on the host frequency. Now that the KVM timer emulation is implemented independent of the host timer frequency and defaults to 100MHz, adjust the working of CONFIG_KVM_HOST_FREQ to match. The Kconfig symbol now specifies the guest timer frequency directly, and has been renamed accordingly to KVM_GUEST_TIMER_FREQ. It now defaults to 100MHz too and the help text is updated to make it clear that a zero value will allow the normal timer frequency calculation to take place (based on the emulated RTC). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Sanjay Lal <sanjayl@kymasys.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Kconfig: rename HAS_IOPORT to HAS_IOPORT_MAPUwe Kleine-König2014-04-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | If the renamed symbol is defined lib/iomap.c implements ioport_map and ioport_unmap and currently (nearly) all platforms define the port accessor functions outb/inb and friend unconditionally. So HAS_IOPORT_MAP is the better name for this. Consequently NO_IOPORT is renamed to NO_IOPORT_MAP. The motivation for this change is to reintroduce a symbol HAS_IOPORT that signals if outb/int et al are available. I will address that at least one merge window later though to keep surprises to a minimum and catch new introductions of (HAS|NO)_IOPORT. The changes in this commit were done using: $ git grep -l -E '(NO|HAS)_IOPORT' | xargs perl -p -i -e 's/\b((?:CONFIG_)?(?:NO|HAS)_IOPORT)\b/$1_MAP/' Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'mips-for-linux-next' of ↵Linus Torvalds2014-04-021-10/+125
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linux-mips.org/pub/scm/ralf/upstream-sfr Pull MIPS updates from Ralf Baechle: - Support for Imgtec's Aptiv family of MIPS cores. - Improved detection of BCM47xx configurations. - Fix hiberation for certain configurations. - Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and systems. - Detection and support for the MIPS P5600 core. - A few more random fixes that didn't make 3.14. - Support for the EVA Extended Virtual Addressing - Switch Alchemy to the platform PATA driver - Complete unification of Alchemy support - Allow availability of I/O cache coherency to be runtime detected - Improvments to multiprocessing support for Imgtec platforms - A few microoptimizations - Cleanups of FPU support - Paul Gortmaker's fixes for the init stuff - Support for seccomp * 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits) MIPS: CPC: Use __raw_ memory access functions MIPS: CM: use __raw_ memory access functions MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n MIPS: Malta: GIC IPIs may be used without MT MIPS: smp-mt: Use common GIC IPI implementation MIPS: smp-cmp: Remove incorrect core number probe MIPS: Fix gigaton of warning building with microMIPS. MIPS: Fix core number detection for MT cores MIPS: MT: core_nvpes function to retrieve VPE count MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n MIPS: Lasat: Replace del_timer by del_timer_sync MIPS: Malta: Setup PM I/O region on boot MIPS: Loongson: Add a Loongson-3 default config file MIPS: Loongson 3: Add CPU hotplug support MIPS: Loongson 3: Add Loongson-3 SMP support MIPS: Loongson: Add Loongson-3 Kconfig options MIPS: Loongson: Add swiotlb to support All-Memory DMA MIPS: Loongson 3: Add serial port support MIPS: Loongson 3: Add IRQ init and dispatch support MIPS: Loongson 3: Add HT-linked PCI support ...
| * Merge branch '3.14-fixes' into mips-for-linux-nextRalf Baechle2014-03-311-11/+18
| |\
| | * MIPS: Fix build error due to multiple prom_putchar() definitions.Ralf Baechle2014-03-311-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | This can happen if both the generic 8250 and another early console driver are enable. Fixed by using an auxilliary kconfig symbol to restrict that choice. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: smp-mt: Use common GIC IPI implementationPaul Burton2014-03-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than duplicating the GIC IPI send function, share the one already used by CONFIG_MIPS_CPS & CONFIG_MIPS_CMP. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6653/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Loongson: Add Loongson-3 Kconfig optionsHuacai Chen2014-03-311-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added Kconfig options include: Loongson-3 CPU and machine definition, CPU cache features, UEFI-like firmware interface (LEFI), HT-linked PCI, and swiotlb support. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6637 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Octeon: Remove SYS_HAS_DMA_OPSRichard Weinberger2014-03-311-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The symbol is an orphan, get rid of it. Signed-off-by: Richard Weinberger <richard@nod.at> Cc: linux-mips@linux-mips.org (open list:MIPS) Cc: linux-kernel@vger.kernel.org (open list) Patchwork: https://patchwork.linux-mips.org/patch/6523/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: No need to select ARCH_SUPPORTS_MSIPaul Bolle2014-03-311-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c24a8a7a9988 ("MIPS: Netlogic: Add MSI support for XLP") added "select ARCH_SUPPORTS_MSI". But the Kconfig symbol ARCH_SUPPORTS_MSI was already removed in v3.12, so that select is a nop. Drop it. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: Jayachandran C <jchandra@broadcom.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6521/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: JZ4740: Don't select HAVE_PWMJingoo Han2014-03-261-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HAVE_PWM symbol is only for legacy platforms that provide the PWM API without using the generic framework. The jz4740 platform uses the generic PWM framework, after the commit "f6b8a57 pwm: Add Ingenic JZ4740 support". Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6525/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Alchemy: Determine cohereny at runtime based on cpu typeManuel Lauss2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All Alchemy chips have coherent DMA, but for example the USB or AC97 peripherals on the Au1000/1500/1100 are not. This patch uses DMA_MAYBE_COHERENT on Alchemy and sets coherentio based on CPU type. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6576/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Enable MIPS 3.5 features on MaltaMarkos Chandras2014-03-261-0/+1
| | | | | | | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | MIPS: Kconfig: Add Kconfig symbols for EVA supportLeonid Yegoshin2014-03-261-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | Add basic Kconfig support for EVA. Not selectable by any platform at this point. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | MIPS: Basic MSA context switching supportPaul Burton2014-03-261-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Detect the MSA ASEPaul Burton2014-03-261-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for probing the MSAP bit within the Config3 register in order to detect the presence of the MSA ASE. Presence of the ASE will be indicated in /proc/cpuinfo. The value of the MSA implementation register will be displayed at boot to aid debugging and verification of a correct setup, as is done for the FPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Select HAVE_ARCH_SECCOMP_FILTERMarkos Chandras2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6401/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Deprecate CONFIG_MIPS_CMPPaul Burton2014-03-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_MIPS_CPS is a better option for systems where it is supported, which as far as I am aware should be all systems where CONFIG_MIPS_CMP could provide any value (ie. where there are multiple cores for YAMON to bring up). This option is therefore deprecated, and marked as such. It is left intact for the time being in order to provide a fallback should someone find a system where CONFIG_MIPS_CPS will not function (ie. where the reset vector cannot be moved), and should be removed entirely in the future assuming that does not happen. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6369/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: MIPS_CMP should depend upon !SMTC, not upon SMVPPaul Burton2014-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f55afb0969cc "MIPS: Clean up MIPS MT and CMP configuration options." introduced a dependency upon MIPS_MT_SMP (ie. SMVP) for the MIPS_CMP (ie. CMP framework support) Kconfig option. It did not specify why, and that dependency is bogus. It is perfectly valid to have a multi-core system with the YAMON bootloader but without MT support - an example of this would be any multi-core proAptiv bitstream running on a Malta. Forcing MT support to be enabled in a kernel for such a system is incorrect. I suspect that the dependency was actually meant to reflect the fact that YAMON will only bind 1 TC per VPE on an MT system, and only describe those 1:1 TC:VPE pairs as CPUs through the AMON interface. Thus an SMTC kernel makes little sense on a system using MIPS_CMP, and the Kconfig dependencies should reflect that rather than introducing the bogus SMVP dependency. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6368/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: More helpful CONFIG_MIPS_CMP label, help textPaul Burton2014-03-261-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prior help text introduced in commit f55afb0969cc "MIPS: Clean up MIPS MT and CMP configuration options." reads as though this option enables the kernel to make use of the CM hardware, which is not true. What it actually does is allow the kernel to interact with the YAMON bootloader which actually interacts with the CM hardware to bring up secondary cores. Re-introduce the word "framework" which that commit removed to avoid misleading people. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6367/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Malta: Allow use of MIPS CPS SMP implementationPaul Burton2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch simply attempts to register the MIPS Coherent Processing System SMP implementation when it is enabled. If registering that fails for some reason (like the Kconfig option being disabled or a lack of hardware support) then we fall back to the same SMP implementations as before. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6365/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Malta: Make use of generic CM supportPaul Burton2014-03-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the Malta-specific CM probe code and instead make use of the newly added generic CM code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6364/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Coherent Processing System SMP implementationPaul Burton2014-03-261-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add CPC probe, access functionsPaul Burton2014-03-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces code to probe for a MIPS Cluster Power Controller & accessor functions to allow for easy register access. This support code will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6361/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add generic CM probe & access codePaul Burton2014-03-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel currently only probes for a MIPS Coherence Manager in the Malta interrupt code in order to detect & enable the GIC. However CM is not Malta-specific, so this should really be more generic. This patch introduces some non-Malta-specific code which probes for a CM and performs some basic initialisation. A new header, with temporarily duplicated register definitions, is introduced in order to: 1) Allow the new definitions to be correct with regards to the CM documentation, as many of those in gcmpregs.h aren't. 2) Allow switching away from the REG() macro used via a few layers of nested macros in order to access registers in gcmpregs.h. This patch instead introduced accessor functions akin to the {read,write}_c0_* functions used for cop0 registers. 3) Allow users of the CM to be migrated one by one. 4) Switch from the name 'GCMP' to 'CM' since the Coherence Manager is what this code is actually dealing with. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6360/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Move GIC IPI functions out of smp-cmp.cPaul Burton2014-03-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC IPI functions aren't necessarily specific to the "CMP framework" SMP implementation, and will be used elsewhere in a subsequent commit. This patch adds cleaned up GIC IPI functions to a separate file which is compiled when a new CONFIG_MIPS_GIC_IPI Kconfig symbol is selected, and selects that symbol for CONFIG_MIPS_CMP. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6359/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | Merge tag 'usb-3.15-rc1' of ↵Linus Torvalds2014-04-021-7/+0Star
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB patches from Greg KH: "Here's the big USB pull request for 3.15-rc1. The normal set of patches, lots of controller driver updates, and a smattering of individual USB driver updates as well. All have been in linux-next for a while" * tag 'usb-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (249 commits) xhci: Transition maintainership to Mathias Nyman. USB: disable reset-resume when USB_QUIRK_RESET is set USB: unbind all interfaces before rebinding any usb: phy: Add ulpi IDs for SMSC USB3320 and TI TUSB1210 usb: gadget: tcm_usb_gadget: stop format strings usb: gadget: f_fs: add missing spinlock and mutex unlock usb: gadget: composite: switch over to ERR_CAST() usb: gadget: inode: switch over to memdup_user() usb: gadget: f_subset: switch over to PTR_RET usb: gadget: lpc32xx_udc: fix wrong clk_put() sequence USB: keyspan: remove dead debugging code USB: serial: add missing newlines to dev_<level> messages. USB: serial: add missing braces USB: serial: continue to write on errors USB: serial: continue to read on errors USB: serial: make bulk_out_size a lower limit USB: cypress_m8: fix potential scheduling while atomic devicetree: bindings: document lsi,zevio-usb usb: chipidea: add support for USB OTG controller on LSI Zevio SoCs usb: chipidea: imx: Use dev_name() for ci_hdrc name to distinguish USBs ...
| * | usb: host: remove selects of USB_ARCH_HAS_?HCIPaul Bolle2014-02-181-7/+0Star
| |/ | | | | | | | | | | | | | | | | | | USB_ARCH_HAS_EHCI, USB_ARCH_HAS_OHCI, and USB_ARCH_HAS_XHCI were just removed. Selecting them is a nop. The select statements for these symbols can be removed too. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | MIPS: Fix possible build error with transparent hugepages enabledAlex Smith2014-03-181-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_TRANSPARENT_HUGEPAGE is enabled, but CONFIG_HUGETLB_PAGE is not, it is possible to end up with a configuration that fails to build with the following error: include/linux/huge_mm.h:125:2: error: #error "hugepages can't be allocated by the buddy allocator" This is due to CONFIG_FORCE_MAX_ZONEORDER defaulting to 11. It already has ranges that change the valid values when HUGETLB_PAGE is enabled, but this is not done for TRANSPARENT_HUGEPAGE. Fix by changing the HUGETLB_PAGE dependencies to MIPS_HUGE_TLB_SUPPORT, which includes both TRANSPARENT_HUGEPAGE and HUGETLB_PAGE. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6391/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: mark O32+FP64 experimental for nowPaul Burton2014-03-171-3/+9
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 597ce1723e0f "MIPS: Support for 64-bit FP with O32 binaries" introduced support for setting Status.FR=1 for O32 binaries with the EF_MIPS_FP64 ELF header flag set. Whilst this flag is currently supported by binutils it does introduce an ABI break within userland. Objects built with EF_MIPS_FP64 cannot be safely linked with those built without it since code in either object may assume behaviour specific to a value of FR. More recently there has been discussion around avoiding further fragmentation of the O32 ABI whilst still allowing the use of FR=1 and features such as MSA which depend upon it. Details of the plan to allow this are still being worked on, and whilst the kernel will need the ability to handle FR=1 with O32 tasks it is unclear what else it may need to provide to a userland which seeks to avoid another ABI break. In order to prevent the proliferation of userland which may rely upon the current EF_MIPS_FP64 behaviour this patch marks the kernel support for it experimental & disables it by default. Under current proposals it is likely that this support can simply be enabled again later, but possibly after the introduction of further interfaces with userland and support for the MIPS R5 UFR feature. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6549/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-01-311-88/+133
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "The most notable new addition inside this pull request is the support for MIPS's latest and greatest core called "inter/proAptiv". The patch series describes this core as follows. "The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit." The platform specific patches touch all 3 Broadcom families. It adds support for the new Broadcom/Netlogix XLP9xx Soc, building a common BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count and full gpio button/led descriptions for BCM47xx. The rest of the series are cleanups and bug fixes that are MIPS generic and consist largely of changes that Imgtec/MIPS had published in their linux-mti-3.10.git stable tree. Random other cleanups and patches preparing code to be merged in 3.15" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) mips: select ARCH_MIGHT_HAVE_PC_SERIO mips: delete non-required instances of include <linux/init.h> MIPS: KVM: remove shadow_tlb code MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI mips/ide: flush dcache also if icache does not snoop dcache MIPS: BCM47XX: fix position of cpu_wait disabling MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> MIPS: introduce MIPS_L1_CACHE_SHIFT_<N> MIPS: ZBOOT: gather string functions into string.c arch/mips/pci: don't check resource with devm_ioremap_resource arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource bcma: gpio: don't cast u32 to unsigned long ssb: gpio: add own IRQ domain MIPS: BCM47XX: fix sparse warnings in board.c MIPS: BCM47XX: add board detection for Linksys WRT54GS V1 MIPS: BCM47XX: fix detection for some boards MIPS: BCM47XX: Enable buttons support on SSB MIPS: BCM47XX: Convert WNDR4500 to new syntax MIPS: BCM47XX: Use "timer" trigger for status LEDs ...
| * mips: select ARCH_MIGHT_HAVE_PC_SERIOMark Salter2014-01-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | Architectures which might use an i8042 for serial IO to keyboard, mouse, etc should select ARCH_MIGHT_HAVE_PC_SERIO. Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> CC: linux-mips@linux-mips.org Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6232/
| * MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT valueFlorian Fainelli2014-01-241-0/+1
| | | | | | | | | | | | | | | | | | Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift value of 4) instead of the currently configured 32 bytes L1-cache line size. Reported-by: Daniel Gonzalez <dgcbueu@gmail.com> Signed-off-by: Florian Fainelli <florian@openwrt.org>
| * MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>Florian Fainelli2014-01-241-3/+4
| | | | | | | | | | | | | | | | | | All platforms that require a special MIPS_L1_CACHE_SHIFT value have been updated, such that we can now make MIPS_L1_CACHE_SHIFT default to the appropriate integer value based on the select MIPS_L1_CACHE_SHIFT_<N> variable. Signed-off-by: Florian Fainelli <florian@openwrt.org>
| * MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>Florian Fainelli2014-01-241-0/+19
| | | | | | | | | | | | | | | | | | In order to avoid keeping an ever growing list of chips which need to select a specific MIPS_L1_CACHE_SHIFT value introduce multiple internal and non-exposed Kconfig symbols for the various MIPS_L1_CACHE_SHIFT values out there and update the relevant Kconfig symbols to select them. Signed-off-by: Florian Fainelli <florian@openwrt.org>
| * MIPS: Netlogic: Add MSI support for XLPJayachandran C2014-01-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
| * MIPS: sead3: allow cmdline/env to change memory size using memsize paramQais Yousef2014-01-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | if the user sets memsize parameter in commandline or bootloader environment, we use it to modify the built-in dtb memory size Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6207/
| * MIPS: Malta: use generic 8250 early consolePaul Burton2014-01-231-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch switches Malta from using the MIPS implementation of early printk with Malta's prom_putchar to using the generic 8250_early implementation. This offers a couple of advantages: - We duplicate less generic code. - The UART can be initialised rather than being reliant upon inheriting a valid setup from the bootloader. The Malta console_config function is extended to initialise the early console if no earlycon= kernel parameter is provided, inheriting the modetty0 bootloader environment if present and falling back to a default 38400n8r setup if not. This matches the behaviour used for the regular console= parameter. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6183/
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