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| * MIPS: asm: spram: Add new symbol for MIPS scratch pad storageMarkos Chandras2015-02-171-0/+5
| | | | | | | | | | | | | | | | | | MIPS R6, just like MIPS R2, have scratch pad storage, so add a new symbol which is selected by MIPS R2 and R6. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00389.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * MIPS: Use generic checksum functions for MIPS R6Markos Chandras2015-02-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | The following instructions have been removed from MIPS R6 ulw, ulh, swl, lwr, lwl, swr. However, all of them are used in the MIPS specific checksum implementation. As a result of which, we will use the generic checksum on MIPS R6 Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * MIPS: Add build support for the MIPS R6 ISALeonid Yegoshin2015-02-161-4/+43
| | | | | | | | | | | | | | | | | | | | Add build support for the latest revision (R6) of the MIPS ISA. microMIPS is not yet supported. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00386.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * MIPS: mm: Add debug information for userland SIGSEGV signals.Markos Chandras2015-02-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 41c594ab65fc ("[MIPS] MT: Improved multithreading support.") removed useful debug information for userland segmentation faults. This patch bring this back along with the ability to determine the name of the object file where the EPC and RA registers point at. Furthermore, we select the SYSCTL_EXCEPTION_TRACE symbol for MIPS which is the de facto solution to turn userland exception logging on and off via the /proc/sys/debug/exception-trace file. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9089/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Kconfig: Fix recursive dependency.Ralf Baechle2015-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [...] HOSTCC scripts/kconfig/zconf.tab.o HOSTLD scripts/kconfig/conf arch/mips/Kconfig:2681:error: recursive dependency detected! arch/mips/Kconfig:2681: symbol MIPS32_N32 depends on MIPS32_COMPAT arch/mips/Kconfig:2658: symbol MIPS32_COMPAT is selected by MIPS32_N32 Introduced by d74473bdf7a4c1ef7ae2b75f585fe5649ac2dcea (MIPS: Compat: Fix build error if CONFIG_MIPS32_COMPAT but no compat ABI.) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Compat: Fix build error if CONFIG_MIPS32_COMPAT but no compat ABI.Ralf Baechle2015-01-131-12/+9Star
|/ | | | | | | | | | | | | | | | | | | | | | | | In that case nor __NR_seccomp_*_32 symbols will be defined in <asm/unistd.h> so the attempt to use it in kernel.seccomp.c will fail with: kernel/seccomp.c:565:2: error: '__NR_seccomp_read_32' undeclared here (not in a function) __NR_seccomp_read_32, __NR_seccomp_write_32, __NR_seccomp_exit_32, __NR_seccomp_sigreturn_32, ^ kernel/seccomp.c:565:24: error: '__NR_seccomp_write_32' undeclared here (not in a function) __NR_seccomp_read_32, __NR_seccomp_write_32, __NR_seccomp_exit_32, __NR_seccomp_sigreturn_32, ^ kernel/seccomp.c:565:47: error: '__NR_seccomp_exit_32' undeclared here (not in a function) __NR_seccomp_read_32, __NR_seccomp_write_32, __NR_seccomp_exit_32, __NR_seccomp_sigreturn_32, ^ kernel/seccomp.c:565:69: error: '__NR_seccomp_sigreturn_32' undeclared here (not in a function) __NR_seccomp_read_32, __NR_seccomp_write_32, __NR_seccomp_exit_32, __NR_seccomp_sigreturn_32, Solved by changing the compat ABIs in kconfig to select MIPS32_COMPAT directly. This also means the user no longer has to select MIPS32_COMPAT before being able to see the ABI options. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-12-121-36/+62
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is an unusually large pull request for MIPS - in parts because lots of patches missed the 3.18 deadline but primarily because some folks opened the flood gates. - Retire the MIPS-specific phys_t with the generic phys_addr_t. - Improvments for the backtrace code used by oprofile. - Better backtraces on SMP systems. - Cleanups for the Octeon platform code. - Cleanups and fixes for the Loongson platform code. - Cleanups and fixes to the firmware library. - Switch ATH79 platform to use the firmware library. - Grand overhault to the SEAD3 and Malta interrupt code. - Move the GIC interrupt code to drivers/irqchip - Lots of GIC cleanups and updates to the GIC code to use modern IRQ infrastructures and features of the kernel. - OF documentation updates for the GIC bindings - Move GIC clocksource driver to drivers/clocksource - Merge GIC clocksource driver with clockevent driver. - Further updates to bring the GIC clocksource driver up to date. - R3000 TLB code cleanups - Improvments to the Loongson 3 platform code. - Convert pr_warning to pr_warn. - Merge a bunch of small lantiq and ralink fixes that have been staged/lingering inside the openwrt tree for a while. - Update archhelp for IP22/IP32 - Fix a number of issues for Loongson 1B. - New clocksource and clockevent driver for Loongson 1B. - Further work on clk handling for Loongson 1B. - Platform work for Broadcom BMIPS. - Error handling cleanups for TurboChannel. - Fixes and optimization to the microMIPS support. - Option to disable the FTLB. - Dump more relevant information on machine check exception - Change binfmt to allow arch to examine PT_*PROC headers - Support for new style FPU register model in O32 - VDSO randomization. - BCM47xx cleanups - BCM47xx reimplement the way the kernel accesses NVRAM information. - Random cleanups - Add support for ATH25 platforms - Remove pointless locking code in some PCI platforms. - Some improvments to EVA support - Minor Alchemy cleanup" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits) MIPS: Add MFHC0 and MTHC0 instructions to uasm. MIPS: Cosmetic cleanups of page table headers. MIPS: Add CP0 macros for extended EntryLo registers MIPS: Remove now unused definition of phys_t. MIPS: Replace use of phys_t with phys_addr_t. MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig. MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO MIPS: <asm/types.h> fix indentation. MAINTAINERS: Add entry for BMIPS multiplatform kernel MIPS: Enable VDSO randomization MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration MIPS: Remove declaration of obsolete arch_init_clk_ops() MIPS: atomic.h: Reformat to fit in 79 columns MIPS: Apply `.insn' to fixup labels throughout MIPS: Fix microMIPS LL/SC immediate offsets MIPS: Kconfig: Only allow 32-bit microMIPS builds MIPS: signal.c: Fix an invalid cast in ISA mode bit handling MIPS: mm: Only build one microassembler that is suitable ...
| * MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BITRalf Baechle2014-11-241-9/+6Star
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Kconfig: Only allow 32-bit microMIPS buildsMaciej W. Rozycki2014-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only allow 32-bit microMIPS builds, we're not ready yet for 64-bit microMIPS support. QEMU does have support for the 64-bit microMIPS ISA and with minor tweaks it is possible to have a 64-bit processor emulated there that runs microMIPS code, so despite the lack of actual 64-bit microMIPS hardware there is a way to run 64-bit microMIPS Linux, but it can all be considered early development and we are not there yet. Userland tools are lacking too, e.g. GCC produces bad code: {standard input}: Assembler messages: {standard input}:380: Warning: wrong size instruction in a 16-bit branch delay slot And our build fails early on, so disable the configuration, for the sake of automatic random config checkers if nothing else. Whoever needs to experiment with 64-bit microMIPS support can revert this change easily. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8481/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Kconfig: Enable microMIPS support for MaltaMaciej W. Rozycki2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing microMIPS support to Malta. Currently the kernel only enables support for the instruction set for the SEAD-3 board despite the fact processor features have nothing to do with the board a processor is installed in. In this case there is no way to run microMIPS software in a fully supported way under Linux on QEMU. QEMU supports the emulation of a Malta board, but does not emulate SEAD-3. Linux supports running microMIPS code on a SEAD-3 board, but hardcodes such support to off on an emulated Malta board even if the processor selected has the microMIPS instruction set implemented. Adding support for the SEAD-3 to QEMU is a major project. Flipping a bit in the kernel that shouldn't have been cleared in the first place is a trivial effort. Thus the answer is plain... Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: ath25: add early printk supportSergey Ryazanov2014-11-241-0/+1
| | | | | | | | | | | | | | Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8241/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: ath25: add interrupts handling routinesSergey Ryazanov2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | Add interrupts initialization and handling routines, also add AHB bus error interrupt handlers for both SoCs families. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8240/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: ath25: add basic AR5312 SoC supportSergey Ryazanov2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | Add basic support for Atheros AR5312/AR2312 SoCs: registers definition file and initial setup code. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8238/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: ath25: add common partsSergey Ryazanov2014-11-241-0/+12
| | | | | | | | | | | | | | | | | | Add common code for Atheros AR5312 and Atheros AR2315 SoCs families. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8237 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: add reset-controller api supportJohn Crispin2014-11-241-0/+2
| | | | | | | | | | | | | | | | | | Add a reset-controller binding for the reset registers found on the lantiq SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8043/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * clocksource: mips-gic: Combine with GIC clockevent driverAndrew Bresticker2014-11-241-13/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Combine the GIC clocksource driver with the GIC clockevent driver from arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate Kconfig symbol. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8132/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Move GIC clocksource driver to drivers/clocksource/Andrew Bresticker2014-11-241-6/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the GIC clocksource driver to drivers/clocksource/mips-gic-timer.c. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8133/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: bcm3384: Initial commit of bcm3384 platform supportKevin Cernekee2014-11-241-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This supports SMP Linux running on the BCM3384 Zephyr (BMIPS5000) application processor, with fully functional UART and USB 1.1/2.0. Device Tree is used to configure the following items: - All peripherals - Early console base address - SMP or UP mode - MIPS counter frequency - Memory size / regions - DMA offset - Kernel command line The DT-enabled bootloader and build instructions are posted at https://github.com/Broadcom/aeolus Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8170/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUsKevin Cernekee2014-11-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2 line size. If L1_CACHE_SHIFT is undersized, DMA buffers will not be cacheline-aligned and terrible things will happen. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizesKevin Cernekee2014-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c. However, it is currently hardwired to use an L1_SHIFT of 6 (64 bytes). Move the L1_SHIFT selection into the CPU or SoC section so that other SoCs can select different values. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8162/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Loongson1B: Some fixes/updates for LS1BKelvin Cheung2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data. (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1) - Add GMAC1 support and setup MUX in terms of PHY mode. - Add CPUFreq support. - Add MUX Register Definitions. - Add PWM Register Definitions. - Update clock register bitfields according to the latest spec. - Update clock related stuff. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8024/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: ELF: Set FP mode according to .MIPS.abiflagsPaul Burton2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reads the .MIPS.abiflags section when it is present, and sets the FP mode of the task accordingly. Any loaded ELF files which do not contain a .MIPS.abiflags section will continue to observe the previous behaviour, that is FR=1 if EF_MIPS_FP64 is set else FR=0. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7681/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Move GIC to drivers/irqchip/Andrew Bresticker2014-11-241-7/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7812/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: i8259: Use IRQ domainsAndrew Bresticker2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a legacy IRQ domain for the 16 i8259 interrupts. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Always use IRQ domains for CPU IRQsAndrew Bresticker2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7799/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Kconfig: Don't allow both microMIPS and SmartMIPS to be selected.Markos Chandras2014-11-241-2/+12
|/ | | | | | | | | | | | | | | microMIPS and SmartMIPS can't be used together. This fixes the following build problem: Warning: the 32-bit microMIPS architecture does not support the `smartmips' extension arch/mips/kernel/entry.S:90: Error: unrecognized opcode `mtlhx $24' [...] arch/mips/kernel/entry.S:109: Error: unrecognized opcode `mtlhx $24' Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7421/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig: Add missing MIPS_CPS dependencies to PM and cpuidleMarkos Chandras2014-10-231-0/+1
| | | | | | | | | | | | | | | | The MIPS_CPS_PM and MIPS_CPS_CPUIDLE implementation should depend on the MIPS_CPS symbol to avoid the following build problem arch/mips/kernel/pm-cps.c: In function 'cps_pm_enter_state': arch/mips/kernel/pm-cps.c:164:26: error: 'cpu_coherent_mask' undeclared (first use in this function) cpumask_clear_cpu(cpu, &cpu_coherent_mask); ^ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/7798/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: DMA: Add cma supportZubair Lutfullah Kakakhel2014-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds cma support to the MIPS architecture. cma uses memblock. However, mips uses bootmem. bootmem is informed about any regions reserved by memblock dma api is modified to use cma reserved memory regions when available Tested using cma_test. cma_test is a simple driver that assigns blocks of memory from cma reserved sections. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Acked-by: Michal Nazarewicz <mina86@mina86.com> Cc: catalin.marinas@arm.com Cc: will.deacon@arm.com Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: arnd@arndb.de Cc: gregkh@linuxfoundation.org Cc: m.szyprowski@samsung.com Cc: x86@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-arch@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7360/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: sead3: Move device-trees to arch/mips/boot/dts/Andrew Bresticker2014-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move the SEAD-3 device-tree to arch/mips/boot/dts/ and update the Makefiles accordingly. Since SEAD-3 requires the device-tree to be built into the kernel, select BUILTIN_DTB when building for SEAD-3. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: David Daney <david.daney@cavium.com> Cc: John Crispin <blogic@openwrt.org> Cc: Jayachandran C <jchandra@broadcom.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7555/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Move device-trees to arch/mips/boot/dts/Andrew Bresticker2014-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move the Octeon device-trees to arch/mips/boot/dts/ and update the Makefiles accordingly. Since Octeon requires the device-tree to be built into the kernel, select BUILTIN_DTB as well. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: David Daney <david.daney@cavium.com> Cc: John Crispin <blogic@openwrt.org> Cc: Jayachandran C <jchandra@broadcom.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7556/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Create common infrastructure for building built-in device-treesAndrew Bresticker2014-09-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | In preparation for moving the device-trees to a common location, introduce the config option BUILTIN_DTB, which can be selected by platforms that use a device-tree built into the kernel image, and create a Makefile to build the device-trees in arch/mips/boot/dts/. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: David Daney <david.daney@cavium.com> Cc: John Crispin <blogic@openwrt.org> Cc: Jayachandran C <jchandra@broadcom.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7564/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-09-191-0/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS fixes from Ralf Baechle: "A fair number of build fixes for various configurations. Fixes to BPF, and the BCM47xx platform code, a preemption fix for the Loongson core, a syscall auditing fix, wire up the new getrandom and memfd_create. Several patches for EVA" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (30 commits) MIPS: SmartMIPS: Disable assembler warnings MIPS: Move CPU topology macros to topology.h MIPS: Wire up new syscalls getrandom and memfd_create. MIPS: Fix a warning for virt_to_page arch/mips/net/bpf_jit.c: fix failure check MIPS: COP2: CPP macro safety fixes. MIPS: Kconfig: Select SMP symbols for CMP MIPS: ZBOOT: add missing <linux/string.h> include MIPS: IP28: Fix/clean spaces.h MIPS: IP28: Select correct L1_CACHE_SHIFT MIPS: BCM63xx: delete double assignment MIPS: Spelling s/confugrations/configurations/ MIPS: OCTEON: make get_system_type() thread-safe MIPS: CPS: Initialize EVA before bringing up VPEs from secondary cores MIPS: Malta: EVA: Rename 'eva_entry' to 'platform_eva_init' MIPS: EVA: Add new EVA header MIPS: scall64-o32: Fix indirect syscall detection MIPS: syscall: Fix AUDIT value for O32 processes on MIPS64 MIPS: Loongson: Fix COP2 usage for preemptible kernel MIPS: NL: Fix nlm_xlp_defconfig build error ...
| * MIPS: Kconfig: Select SMP symbols for CMPMarkos Chandras2014-08-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CMP is an SMP implementation, and as a result of which, it needs to select the SYS_SUPPORTS_SMP and SMP symbols. This fixes the following build problem when CMP is enabled but SMP is not. In file included from arch/mips/kernel/smp-cmp.c:34:0: ./arch/mips/include/asm/smp.h:26:0: error: "raw_smp_processor_id" redefined [-Werror] #define raw_smp_processor_id() (current_thread_info()->cpu) [...] In file included from arch/mips/kernel/smp-cmp.c:34:0: ./arch/mips/include/asm/smp.h:59:20: error: redefinition of 'smp_send_reschedule' [...] ./arch/mips/include/asm/smp.h: In function 'smp_send_reschedule': ./arch/mips/include/asm/smp.h:63:8: error: dereferencing pointer to incomplete type Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7436/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: IP28: Select correct L1_CACHE_SHIFTThomas Bogendoerfer2014-08-261-0/+1
| | | | | | | | | | | | | | | | | | IP28 has 128 byte cache lines. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7548/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | kexec: remove CONFIG_KEXEC dependency on cryptoVivek Goyal2014-08-301-2/+0Star
|/ | | | | | | | | | | | | | | New system call depends on crypto. As it did not have a separate config option, CONFIG_KEXEC was modified to select CRYPTO and CRYPTO_SHA256. But now previous patch introduced a new config option for new syscall. So CONFIG_KEXEC does not require crypto. Remove that dependency. Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Cc: Eric Biederman <ebiederm@xmission.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Shaun Ruffell <sruffell@digium.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* kexec: load and relocate purgatory at kernel load timeVivek Goyal2014-08-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Load purgatory code in RAM and relocate it based on the location. Relocation code has been inspired by module relocation code and purgatory relocation code in kexec-tools. Also compute the checksums of loaded kexec segments and store them in purgatory. Arch independent code provides this functionality so that arch dependent bootloaders can make use of it. Helper functions are provided to get/set symbol values in purgatory which are used by bootloaders later to set things like stack and entry point of second kernel etc. Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Cc: Borislav Petkov <bp@suse.de> Cc: Michael Kerrisk <mtk.manpages@gmail.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Eric Biederman <ebiederm@xmission.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Greg Kroah-Hartman <greg@kroah.com> Cc: Dave Young <dyoung@redhat.com> Cc: WANG Chao <chaowang@redhat.com> Cc: Baoquan He <bhe@redhat.com> Cc: Andy Lutomirski <luto@amacapital.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-08-071-2/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is the main pull request for 3.17. It contains: - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates - MIPS ptrace updates and cleanups - various fixes that will also go to -stable - a number of cleanups and small non-critical fixes. - NUMA support for the Loongson 3. - more support for MSA - support for MAAR - various FP enhancements and fixes" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) MIPS: jz4740: remove unnecessary null test before debugfs_remove MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive MIPS: ZBOOT: implement stack protector in compressed boot phase MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT MIPS: Bonito64: remove a duplicate define MIPS: Malta: initialise MAARs MIPS: Initialise MAARs MIPS: detect presence of MAARs MIPS: define MAAR register accessors & bits MIPS: mark MSA experimental MIPS: Don't build MSA support unless it can be used MIPS: consistently clear MSA flags when starting & copying threads MIPS: 16 byte align MSA vector context MIPS: disable preemption whilst initialising MSA MIPS: ensure MSA gets disabled during boot MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains MIPS: fix MSA context for tasks which don't use FP first MIPS: init upper 64b of vector registers when MSA is first used MIPS: save/disable MSA in lose_fpu MIPS: preserve scalar FP CSR when switching vector context ...
| * MIPS: mark MSA experimentalPaul Burton2014-08-021-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In light of the commit 16f77de82f2d (Revert "MIPS: Save/restore MSA context around signals") the MSA support in the kernel is incomplete. Until the replacement for the former sigcontext changes is agreed upon and in tree, mark MSA experimental & disable it by default. MSA is only implemented by one CPU supported by the kernel, the P5600. The P5600 is a 32 bit core, and thus MSA can only be used when the experimental CONFIG_MIPS_O32_FP64_SUPPORT option is enabled. Therefore MSA is only being used in experimental settings anyway and this change doesn't actually make any difference beyond clarifying the state of MSA support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7311/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Don't build MSA support unless it can be usedPaul Burton2014-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | MSA requires that Status.FR == 1, so for MIPS32 tasks MSA can only be used if CONFIG_MIPS_O32_FP64_SUPPORT is enabled. If it is not & the kernel is 32bit, there's no point including support for MSA. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7310/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: BCM47XX: Move shared symbols to the config BCM47XXRafał Miłecki2014-07-301-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7100/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: pm-cps: Select CONFIG_MIPS_CPCPaul Burton2014-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The pm-cps code can run without a CPC, although will be limited to using only the 2 wait idle states. However the code does check for CPC presence, and in order to work optimally the CPC support is needed. So select it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7279/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: BCM63xx: Sync MIPS counters during CPU bringupJonas Gorski2014-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are using the mips counters as the clock source, so we need to ensure they are synced, else e.g. gettimeofday will return different values depending on which core it was run. Observed difference was about 8 seconds, causing ~8 seconds ping or time running backwards for some programs. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7265/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: clock framework integration of onchip clocksManuel Lauss2014-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces common clock framework integration for all configurable on-chip clocks on Alchemy chips: - 2 or 3 PLLs which generate integer multiples of the root rate 12MHz, - 6 dividers which take one of the 3 PLLs as input and divide their rate by either multiples of 2 or 1 (Au1300). - another bank of up to 6 muxes which take either one of the 6 above dividers or one of the PLLs directly and divide their rate further by 1, 2, 3 or 4. - a few other sources which are used by onchip peripherals and are informational. This implementation will take the clock tree as it was set up by boot firmware: all in-kernel boards should continue to work without having to set up the clock tree in board code. CLK_IGNORE_DISABLED will be removed once all drivers have been converted. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7466/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: ftrace: Remove check of obsolete variable function_trace_stopSteven Rostedt (Red Hat)2014-07-181-1/+0Star
|/ | | | | | | | | Nothing sets function_trace_stop to disable function tracing anymore. Remove the check for it in the arch code. Cc: Ralf Baechle <ralf@linux-mips.org> Tested-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
* MIPS: Lasat: Fix build error if CRC32 is not enabled.Ralf Baechle2014-06-261-0/+1
| | | | | | | | | | | | | | Kconfig doesn't select CRC32 so it's possible to build a Lasat kernel without CONFIG_CRC32 resulting in a build error: LD vmlinux arch/mips/built-in.o: In function `lasat_init_board_info': (.text+0x22c): undefined reference to `crc32_le' arch/mips/built-in.o: In function `lasat_write_eeprom_info': (.text+0x7fc): undefined reference to `crc32_le' make: *** [vmlinux] Error 1 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-06-101-71/+71
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: - three fixes for 3.15 that didn't make it in time - limited Octeon 3 support. - paravirtualization support - improvment to platform support for Netlogix SOCs. - add support for powering down the Malta eval board in software - add many instructions to the in-kernel microassembler. - add support for the BPF JIT. - minor cleanups of the BCM47xx code. - large cleanup of math emu code resulting in significant code size reduction, better readability of the code and more accurate emulation. - improvments to the MIPS CPS code. - support C3 power status for the R4k count/compare clock device. - improvments to the GIO support for older SGI workstations. - increase number of supported CPUs to 256; this can be reached on certain embedded multithreaded ccNUMA configurations. - various small cleanups, updates and fixes * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (173 commits) MIPS: IP22/IP28: Improve GIO support MIPS: Octeon: Add twsi interrupt initialization for OCTEON 3XXX, 5XXX, 63XX DEC: Document the R4k MB ASIC mini interrupt controller DEC: Add self as the maintainer MIPS: Add microMIPS MSA support. MIPS: Replace calls to obsolete strict_strto call with kstrto* equivalents. MIPS: Replace obsolete strict_strto call with kstrto MIPS: BFP: Simplify code slightly. MIPS: Call find_vma with the mmap_sem held MIPS: Fix 'write_msa_##' inline macro. MIPS: Fix MSA toolchain support detection. mips: Update the email address of Geert Uytterhoeven MIPS: Add minimal defconfig for mips_paravirt MIPS: Enable build for new system 'paravirt' MIPS: paravirt: Add pci controller for virtio MIPS: Add code for new system 'paravirt' MIPS: Add functions for hypervisor call MIPS: OCTEON: Add OCTEON3 to __get_cpu_type MIPS: Add function get_ebase_cpunum MIPS: Add minimal support for OCTEON3 to c-r4k.c ...
| * MIPS: Enable build for new system 'paravirt'David Daney2014-06-021-0/+19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7015/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: paravirt: Add pci controller for virtioDavid Daney2014-06-021-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7011/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Move system level config items from CPU_CAVIUM_OCTEON to CAVIUM_OCTEON_SOCDavid Daney2014-05-301-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | They are a property of the SoC not the CPU itself. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Malta: add suspend state entry codePaul Burton2014-05-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces code which will enter a suspend state via the PIIX4. This can only be done when PCI support is enabled since it requires access to PCI I/O space and the generation of a special cycle on the PCI bus. In cases where PCI is disabled the mips_pm_suspend function will simply always return an error. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6905/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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