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* MIPS: Abstract CPU core & VP(E) ID access through accessor functionsPaul Burton2017-08-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | We currently have fields in struct cpuinfo_mips for the core & VP(E) ID of a particular CPU, and various pieces of code directly access those fields. This patch abstracts such access by introducing accessor functions cpu_core(), cpu_set_core(), cpu_vpe_id() & cpu_set_vpe_id() and having code that needs to access these values call those functions rather than directly accessing the struct cpuinfo_mips fields. This prepares us for changes to the way in which those values are stored in later patches. The cpu_vpe_id() function is introduced even though we already had a cpu_vpe_id() macro for a couple of reasons: 1) It's more consistent with the core, and future cluster, accessors. 2) It ensures a sensible return type without explicit casts. 3) It's generally preferable to use functions rather than macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix MIPS I ISA /proc/cpuinfo reportingMaciej W. Rozycki2017-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct a commit 515a6393dbac ("MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo") regression that caused MIPS I systems to show no ISA levels supported in /proc/cpuinfo, e.g.: system type : Digital DECstation 2100/3100 machine : Unknown processor : 0 cpu model : R3000 V2.0 FPU V2.0 BogoMIPS : 10.69 wait instruction : no microsecond timers : no tlb_entries : 64 extra interrupt vector : no hardware watchpoint : no isa : ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 0 VCED exceptions : not available VCEI exceptions : not available and similarly exclude `mips1' from the ISA list for any processors below MIPSr1. This is because the condition to show `mips1' on has been made `cpu_has_mips_r1' rather than newly-introduced `cpu_has_mips_1'. Use the correct condition then. Fixes: 515a6393dbac ("MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo") Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 3.19+ Patchwork: https://patchwork.linux-mips.org/patch/16758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfoMaciej W. Rozycki2017-07-111-0/+1
| | | | | | | | | | | | | Only now that both feature determination and unaligned emulation is in place add reporting to /proc/cpuinfo, so that the presence of "mips16e2" there not only indicates our recognition of the hardware feature, but correct unaligned emulation as well. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16757/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move identification of VP(E) into proc.c from smp-mt.cMatt Redfearn2016-10-041-0/+7
| | | | | | | | | | | | | | | | | | | The addition of VPE information to /proc/cpuinfo used to be in smp-mt.c. This file is not used by MIPS r6 kernels, so the Virtual Processor information was not present for these CPU types. Move the code to print VPE information into proc.c, add a case for MIPS r6 CPUS, and remove the block from smp-mt.c. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13847/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Detect DSP v3 supportZubair Lutfullah Kakakhel2016-05-131-0/+1
| | | | | | | | | | | | | | | | DSPv3 is supported on all MIPSr6 systems which indicate support for DSPv2. This doesn't require any changes to the kernel's handling of DSP resources. The patch is to detect support and indicate it in /proc/cpuinfo DSP v3 introduces a new instruction BPOSGE32C Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12918/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support for XPA.Steven J. Hill2015-03-191-0/+1
| | | | | | | | | | | | | | | | | | Add support for extended physical addressing (XPA) so that 32-bit platforms can access equal to or greater than 40 bits of physical addresses. NOTE: 1) XPA and EVA are not the same and cannot be used simultaneously. 2) If you configure your kernel for XPA, the PTEs and all address sizes become 64-bit. 3) Your platform MUST have working HIGHMEM support. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfoMarkos Chandras2015-02-171-1/+7
| | | | | | | Print 'mips64r6' and/or 'mips32r6' if the kernel is running on a MIPS R6 core. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: cpu: Add new cpu option for Hardware Table Walker.Markos Chandras2014-08-021-0/+1
| | | | | | | | | | Moreover, report hardware page table walker support as 'htw' in the ASE list of /proc/cpuinfo, if the core implements this feature. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support CPU topology files in sysfsHuacai Chen2014-07-301-0/+1
| | | | | | | | | | | | | | | | | This patch is prepared for Loongson's NUMA support, it offer meaningful sysfs files such as physical_package_id, core_id, core_siblings and thread_siblings in /sys/devices/system/cpu/cpu?/topology. Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7184/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Revert "MIPS: MT: proc: Add support for printing VPE and TC ids"Ralf Baechle2014-05-131-8/+1Star
| | | | | | | Reverts commit 795038a6910937fa167d47f6f6183db0eb8fb706 because d6d3c9afaab47418ab2d7f874fb8aeac1f067104 provides the same functionality in a more generic way. Both patches applied however means that the VPE and TC IDs get printed twice currently.
* MIPS: MT: proc: Add support for printing VPE and TC idsRalf Baechle2014-03-311-0/+23
| | | | | | | | | | | | | | And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6066/
* MIPS: kernel: proc: Add EVA to the list of CPU featuresMarkos Chandras2014-03-261-0/+1
| | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Detect the MSA ASEPaul Burton2014-03-261-0/+1
| | | | | | | | | | | | | This patch adds support for probing the MSAP bit within the Config3 register in order to detect the presence of the MSA ASE. Presence of the ASE will be indicated in /proc/cpuinfo. The value of the MSA implementation register will be displayed at boot to aid debugging and verification of a correct setup, as is done for the FPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: /proc/cpuinfo: always print the supported ISAAaro Koskinen2014-01-241-20/+19Star
| | | | | | | | | Currently the supported ISA is only printed on the latest architectures. Print it also on legacy platforms. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6295/
* MIPS: MT: proc: Add support for printing VPE and TC idsMarkos Chandras2014-01-221-1/+8
| | | | | | | | | | Add support for including VPE and TC ids in /proc/cpuinfo output as appropriate when MT/SMTC is enabled. Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6065/
* MIPS: Get rid of MIPS I flag and test macros.Ralf Baechle2013-07-011-3/+1Star
| | | | | | | | | | | | | | | | | | | | | | MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5551/
* MIPS: Idle: Consolidate all declarations in <asm/idle.h>.Ralf Baechle2013-05-221-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'mti-next' of ↵Ralf Baechle2013-05-091-0/+4
|\ | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * MIPS: microMIPS: Add configuration option for microMIPS kernel.Steven J. Hill2013-05-091-0/+4
| | | | | | | | | | | | | | | | This adds the option to build the Linux kernel using only the microMIPS ISA. The resulting kernel binary is, at a minimum, 20% smaller than using the MIPS32R2 ISA. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
* | MIPS: move mips_{set,get}_machine_name() to a more generic placeJohn Crispin2013-05-081-1/+1
|/ | | | | | | | Previously this functionality was only available to users of the mips_machine api. Moving the code to prom.c allows us to also add a OF wrapper. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5164/
* MIPS: Fix inconsistent formatting inside /proc/cpuinfoJohn Crispin2013-03-131-1/+1
| | | | | | | | | | | | | | | There is a missing " " inside /proc/cpuinfo. The bad commit was: commit a96102be700f87283f168942cd09a2b30f86f324 Author: Steven J. Hill <sjhill@mips.com> Date: Fri Dec 7 04:31:36 2012 +0000 MIPS: Add printing of ISA version in cpuinfo. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4988/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'mips-next-3.9' of ↵Ralf Baechle2013-02-211-0/+2
|\ | | | | | | git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
| * MIPS: Probe for and report hardware virtualization support.David Daney2013-02-191-0/+1
| | | | | | | | | | | | | | | | | | | | The presence of the MIPS Virtualization Application-Specific Extension is indicated by CP0_Config3[23]. Probe for this and report it in /proc/cpuinfo. Signed-off-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4904/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * MIPS: Add support for the M14KEc core.Steven J. Hill2013-02-171-0/+1
| | | | | | | | | | | | Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
* | MIPS: Add printing of ISA version in cpuinfo.Steven J. Hill2013-02-151-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display the MIPS ISA version release in the /proc/cpuinfo file. [ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture revisions. Also differenciate between MIPS32 and MIPS64 versions instead of lumping them together as just r1 and r2. Note to application programmers: this indicates the CPU's ISA level It does not imply the current execution environment does support it. For example an O32 application seeing "mips64r2" would still be restricted by by the execution environment to 32-bit - but the kernel could run mips64r2 code. The same for a 32-bit kernel running on a 64-bit processor. This field doesn't include ASEs or optional architecture modules nor other detailed flags such as the availability of an FPU.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/4714/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-1/+1
|/ | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: proc: Cleanup printing of ASEs.Ralf Baechle2012-10-111-9/+11
| | | | | | The number of %s was just getting ridiculous. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill2012-10-111-0/+1
| | | | | | | | | | | [ralf@linux-mips.org: This patch really only detects the ASE and passes its existence on to userland via /proc/cpuinfo. The DSP ASE Rev 2. adds new resources but no resources that would need management by the kernel.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4165/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Code formatting fixes.Steven J. Hill2012-05-151-13/+13
| | | | | | Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* remove references to cpu_*_map in arch/Rusty Russell2012-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | This has been obsolescent for a while; time for the final push. In adjacent context, replaced old cpus_* with cpumask_*. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Acked-by: David S. Miller <davem@davemloft.net> (arch/sparc) Acked-by: Chris Metcalf <cmetcalf@tilera.com> (arch/tile) Cc: user-mode-linux-devel@lists.sourceforge.net Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Cc: Richard Kuo <rkuo@codeaurora.org> Cc: linux-hexagon@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Kyle McMartin <kyle@mcmartin.ca> Cc: Helge Deller <deller@gmx.de> Cc: sparclinux@vger.kernel.org
* MIPS: Probe for presence of KScratch registers.David Daney2011-01-181-0/+2
| | | | | | | | | Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1877/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add generic support for multiple machines within a single kernelGabor Juhos2011-01-181-1/+6
| | | | | | | | | | | | | | | | | | This patch adds a generic solution to support multiple machines based on a given SoC within a single kernel image. It is implemented already for several other architectures but MIPS has no generic support for that yet. [Ralf: This competes with DT but DT is a much more complex solution and this code has been used by OpenWRT for a long time so for now DT is a bad reason to stop the merge but longer term this should be migrated to DT.] Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: kaloz@openwrt.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Eleminate filenames from commentsRalf Baechle2009-08-031-2/+0Star
| | | | | | | | | | They tend to get not updated when files are moved around or copied and lack any obvious use. While at it zap some only too obvious comments and as per Shinya's suggestion, add a copyright header to extable.c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Acked-by: Thadeu Lima de Souza Cascardo <cascardo@holoscopio.com>
* MIPS: Outline udelay and fix a few issues.Ralf Baechle2009-06-081-1/+1
| | | | | | | | | | | | | | | Outlining fixes the issue were on certain CPUs such as the R10000 family the delay loop would need an extra cycle if it overlaps a cacheline boundary. The rewrite also fixes build errors with GCC 4.4 which was changed in way incompatible with the kernel's inline assembly. Relying on pure C for computation of the delay value removes the need for explicit. The price we pay is a slight slowdown of the computation - to be fixed on another day. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: show_cpuinfo prints the type of the calling CPUJohannes Dickgreber2008-10-151-1/+1
| | | | | | | It should print the type of the Nth processor. Signed-off-by: Johannes Dickgreber <tanzy@gmx.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Probe watch registers and report configuration.David Daney2008-10-111-2/+11
| | | | | | | Probe for watch register characteristics, and report them in /proc/cpuinfo. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS]: constify function pointer tablesJan Engelhardt2008-01-291-1/+1
| | | | | Signed-off-by: Jan Engelhardt <jengelh@computergmbh.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Scheduler support for SMTRalf Baechle2008-01-291-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-161-0/+2
| | | | | | | | | | | | | Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle2007-10-121-74/+1Star
| | | | | | | So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add support for BCM47XX CPUs.Aurelien Jarno2007-10-121-0/+2
| | | | | | | | | | | | | | Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-101-0/+1
| | | | | Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove unused watchpoint support and arch/mips/lib-{32,64}Atsushi Nemoto2007-07-101-1/+0Star
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Whitespace cleanups.Ralf Baechle2007-02-061-4/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make sure cpu_has_fpu is used only in atomic contextAtsushi Nemoto2006-10-101-1/+1
| | | | | | | | Make sure cpu_has_fpu (which uses smp_processor_id()) is used only in atomic context. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Show actual CPU information in /proc/cpuinfoKarl-Johan Karlsson2006-10-081-5/+5
| | | | | | | | | | Currently, /proc/cpuinfo contains several copies of the information for whatever processor we happen to be scheduled on. This patch makes it contain the proper information for each CPU, which is particularly useful on mixed R12k/R10k IP27 machines. Signed-off-by: Karl-Johan Karlsson <creideiki@lysator.liu.se> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0Star
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [MIPS] Treat R14000 like R10000.Kumba2006-06-011-0/+1
| | | | | Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix detection and handling of the 74K processor.Chris Dearman2006-06-011-0/+1
| | | | | | | | Nothing exciting; Linux just didn't know it yet so this is most adding a value to a case statement. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Separate CPU entries in /proc/cpuinfo with a blank line.Martin Michlmayr2006-03-211-0/+1
| | | | | | | | | | Put in a blank line between CPU entries in /proc/cpuinfo, just like most other architectures (i386, ia64, x86_64) do. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
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