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* MIPS: ralink: mt7620: Add spi clock definitionJohn Crispin2013-09-041-0/+1
| | | | | | | | | | | | | Register a clock device for the SPI block of the MT7620 SoC. The clock device will be used by the SPI host controller driver to determine the base clock of the controller. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: mt7620: Add wdt clock definitionJohn Crispin2013-09-041-0/+1
| | | | | | | | | | | | | | | | | | | The watchdog driver of the SoC uses the clk API to get the clock associated with the watchdog device. However the MT7620 specific setup code does not register a clock for the watchdog device yet which leads to the following error: rt2880_wdt: probe of 10000120.watchdog failed with error -2 Register a clock device for the watchdog in order to avoid the error and make the watchdog usable. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5756/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: mt7620: Improve clock frequency detectionGabor Juhos2013-09-042-33/+207
| | | | | | | | | | | | | | | | | | | | | The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: mt7620: This SoC has EHCI and OHCI hostsJohn Crispin2013-09-041-0/+2
| | | | | | | | | Select the the EHCI and OHCI symbols. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5675/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: mt7620: Add verbose ram infoJohn Crispin2013-09-041-0/+3
| | | | | | | | | Make the code print which of SDRAM, DDR1 or DDR2 was detected. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/5671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Probe clocksources from OFJohn Crispin2013-09-041-0/+1
| | | | | | | | | | Make plat_time_init() call clocksource_of_init() allowing the systick cevt to load. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/5670/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Add support for systick timer found on newer ralink SoCJohn Crispin2013-09-043-0/+154
| | | | | | | | | | | Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent of the SoC master clock. If we want to automatic frequency scaling to work we need to use the systick timer as the clock source. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5669/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Add support for periodic timer irqJohn Crispin2013-09-042-1/+186
| | | | | | | | | Adds a driver for the periodic timer found on Ralink SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5682/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Built-in DTB for XLP2xx SoC boardsGanesan Ramalingam2013-09-034-1/+135
| | | | | | | | | | | Add a default built-in device tree for XLP2xx SoC. The new file xlp_fvp.dts has updated entries for I2C and memory. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Add support for USB on XLP2xxGanesan Ramalingam2013-09-036-20/+270
| | | | | | | | | | | | | Add USB intialization code to handle the new XLP2XX USB 3.0 block. This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h and xlp/nlm_hal.c is also updated for the new USB block. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5744/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: XLP2xx update for I2C controllerGanesan Ramalingam2013-09-033-7/+21
| | | | | | | | | | | XLP2xx has a new I2C controller which has 4 buses connected to it. Update the IO offset and IRQ mapping code to reflect this. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Core wakeup changes for XLP2XXJayachandran C2013-09-031-4/+6
| | | | | | | | | | On XLP2xx, wakeup code does not need to enable clock on the core. Update xlp/wakeup.c to handle this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: XLP2XX CPU and PIC frequencyGanesan Ramalingam2013-09-035-11/+153
| | | | | | | | | | | | | Add code to calculate the CPU and PIC frequency for XLP2XX SoCs. Since the PIC frequency on XLP2XX can be configured, add a new macro pic_timer_freq() to be used in netlogic/common/time.c. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Ganesan Ramalingam <ganesanr@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Call xlp_mmu_init on all threadsJayachandran C2013-09-031-3/+1Star
| | | | | | | | | | The config7/config4 register has to be written on all the threads. This does not cause any problems in XLP, but is needed for XLPII Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Add support for XLP2XXJayachandran C2013-09-034-7/+33
| | | | | | | | | | | | | | XLP2XX is first in the series of 28nm XLPII processors. The changes are to: * Add processor ID for XLP2XX to asm/cpu.h and kernel/cpu-probe.c. * Add a cpu_is_xlpii() function to check for XLPII processors. * Update xlp_mmu_init() to use config4 to enable extended TLB. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5698/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Fix DT flash size parameterJayachandran C2013-09-032-2/+2
| | | | | | | | | | The flash chipselects can span 32MB, fix this in the built-in device tree. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Remove memory section from built-in DTJayachandran C2013-09-032-14/+0Star
| | | | | | | | | | Do not pass a memory section in the built-in DTB, and let the boot code use the values from the DRAM BARs. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Read memory from DRAM BARsJayachandran C2013-09-034-0/+65
| | | | | | | | | | | Read the memory from the Bridge DRAM BARs, if it is not passed in from the device tree. This will allow us to remove memory configuration from built in device trees. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5743/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Switch to the clkdev frameworkGabor Juhos2013-09-033-72/+55Star
| | | | | | | | | | | | | | | | | | | | | | | | | The ath79 code uses static clock devices and provides its own clk_{get,put} implementations. Change the code to use dynamically allocated clock devices and register the clocks within the clkdev framework. Additionally, remove the local clk_{get,put} implementation. The clkdev framework has a common implementation of those. Also move the call of ath79_clock_init() from plat_mem_init() to plat_time_init(). Otherwise it would not be possible to use memory allocation functions from ath79clock_init() becasuse the memory subsystem is not yet initialized when plat_mem_init() runs. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5780/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use local variables for clock ratesGabor Juhos2013-09-031-52/+106
| | | | | | | | | | | | | | Use local variables for ref, cpu, ddr and ahb rates in SoC specific clock init functions. The patch has no functional changes, it is an interim change in preparation of the next patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use ath79_get_sys_clk_rate to get basic clock ratesGabor Juhos2013-09-032-11/+12
| | | | | | | | | | | | | | | | | | | | Instead of accessing the rate field of the static clock devices directly, use the recently introduced helper function to get the rate of the basic clocks. The static ath79_{ahb,cpu,ddr,ref}_clk variables will be removed by a subsequent patch. The actual change is in preparation of that. Also move the clock frequency printing code into the plat_time_init function. We are getting the cpu clock rate there already so we can save an extra call of the helper. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5782/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use a helper function to get system clock ratesGabor Juhos2013-09-034-11/+25
| | | | | | | | | | | | The ath79 platform uses similar code to get the rate of various clocks during init. Separate the similar code into a new helper function and use that to avoid code duplication. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5778/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use local ref clock rate in ar934x_get_pll_freqGabor Juhos2013-09-031-2/+2
| | | | | | | | | | | The reference clock rate is passed in the first argument of the function. Use that instead of the rate of the global ath79_ref_clk variable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5779/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Fix ar933x watchdog clockFelix Fietkau2013-09-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The watchdog device on the AR933x is connected to the AHB clock, however the current code uses the reference clock. Due to the wrong rate, the watchdog driver can't calculate correct register values for a given timeout value and the watchdog unexpectedly restarts the system. The code uses the wrong value since the initial commit 04225e1d227c8e68d685936ecf42ac175fec0e54 (MIPS: ath79: add AR933X specific clock init) The patch fixes the code to use the correct clock rate to avoid the problem. Cc: stable@vger.kernel.org Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5777/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Don't hardwire cpu_has_dsp{2} to 0Gabor Juhos2013-09-031-2/+0Star
| | | | | | | | | | | | | | | | | The ath79 code supports various SoCs which are using either a 24Kc or a 74Kc core. The 74Kc core has DSP support, so don't hardwire the values to zero. Commit 00dc5ce2a653a332190aa29b2e1f3bceaa7d5b8d (MIPS: ath79: don't hardcode the unavailability of the DSP ASE) has fixed this already, but that change got reverted by 475032564ed96c94c085e3e7a90e07d150a7cec9 (MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.) Reported-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5750/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add defconfig for xway SoCJohn Crispin2013-09-031-0/+159
| | | | | | | | | This add a default config for the Lantiq XWAY SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5796/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Falcon: fix asc clock definitionThomas Langer2013-09-031-1/+4
| | | | | | | | | | The clocks of the serial ports were not setup properly. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5659/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Falcon: add cpu-feature-override.hThomas Langer2013-09-031-0/+58
| | | | | | | | | | Add cpu-feature-override.h for the GPON SoC Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5658/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Adds minimal dcdc driverJohn Crispin2013-09-032-1/+64
| | | | | | | | | This driver so far only reads the core voltage. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5677/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move declaration of Octeon function fixup_irqs() to header.Ralf Baechle2013-09-033-4/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add uImage build targetJames Hogan2013-09-033-0/+22
| | | | | | | | | | | | | | | | | | | Add a uImage build target for MIPS, which builds uImage.gz (a U-Boot image of vmlinux.bin.gz), and then symlinks it to uImage. This allows for the use of other compression algorithms in future, and is how a few other architectures do it. It's enabled conditionally on load-y >= 0xffffffff80000000 which hopefully allows 64bit kernels to also work as long as the load and entry address can be represented by the 32bit addresses in the U-Boot image format. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5795/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Refactor load/entry address calculationsJames Hogan2013-09-033-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | The vmlinux load address and entry address is calculated in multiple places: - arch/mips/Makefile defines load-y from CONFIG_PHYSICAL_START (or defined by the platform) and passes it to arch/mips/boot/compressed/Makefile. - arch/mips/boot/compressed/Makefile calculates kernel entry using nm. - arch/mips/lasat/image/Makefile calculates both load and entry address using nm. Lets combine these in the main Makefile and then pass them as Make parameters to each of the three boot image Makefiles (in boot/, boot/compressed, lasat/image/). The boot/ Makefile doesn't currently use them, but will soon need to for U-Boot image targets. The existing load-y definition is used in preference to calculating the load address using nm. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5794/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Refactor boot and boot/compressed rulesJames Hogan2013-09-031-2/+13
| | | | | | | | | | | | | Split out the arch/mips/boot/ and arch/mips/boot/compressed/ targets into boot-y and bootz-y variables. This makes it slightly cleaner to add new targets. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5793/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: add <dt-bindings/> symlinkJames Hogan2013-09-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add symlink to include/dt-bindings from arch/mips/boot/dts/include/ to match the ones in ARM and Meta architectures so that preprocessed device tree files can include various useful constant definitions. See commit c58299a (kbuild: create an "include chroot" for DT bindings) merged in v3.10-rc1 for details. MIPS structures it's dts files a little differently to other architectures, having a separate dts directory for each SoC/platform, but most of the definitions in the dt-bindings/ directory are common so for now lets just have a single "include chroot" for all MIPS platforms. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Steven. J. Hill <steven.hill@imgtec.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Ian Campbell <ian.campbell@citrix.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kbuild@vger.kernel.org Acked-by: Stephen Warren <swarren@nvidia.com> Patchwork: http://patchwork.linux-mips.org/patch/5745/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Discard .eh_frame sections in linker script.David Daney2013-08-261-0/+1
| | | | | | | | | | Some toolchains (including Cavium OCTEON SDK) are emitting .eh_frame sections by default. Discard them as they are useless in the kernel. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5684/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIBDavid Daney2013-08-262-0/+22
| | | | | | | | | | | | | | | ... and create asm/mach-cavium-octeon/gpio.h so that things continue to build. This allows us to use the existing I2C connected GPIO expanders. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5632/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove unreachable break statements from cp1emu.cDavid Daney2013-08-261-27/+0Star
| | | | | | | | | | | | | | | There were many cases of: return something; break; All those break statements are unreachable and thus redundant. Signed-off-by: David Daney <david.daney@cavium.com> Reviewed-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Fix compilation for BMIPS5000Ralf Baechle2013-08-261-33/+22Star
| | | | | | | | | | | | | | | | | | | | Commit 02b849f7613003fe5f9e58bf233d49b0ebd4a5e8 ("MIPS: Get rid of the use of .macro in C code.") replaced the macro usage but missed the accessors in bmips.h, causing the following build error: CC arch/mips/kernel/smp-bmips.o {standard input}: Assembler messages: {standard input}:951: Error: Unrecognized opcode `_ssnop' {standard input}:952: Error: Unrecognized opcode `_ssnop' (...) make[6]: *** [arch/mips/kernel/smp-bmips.o] Error 1 Fix by rewriting the inline assembler using existing inline functions. The generated code should stay unchanged. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5644/ Reviewed-by: Jonas Gorski <jogo@openwrt.org>
* MIPS: cavium-octeon: fix I/O space setup on non-PCI systemsAaro Koskinen2013-08-262-4/+33
| | | | | | | | | | | | | | | | | | | Fix I/O space setup, so that on non-PCI systems using inb()/outb() won't crash the system. Some drivers may try to probe I/O space and for that purpose we can just allocate some normal memory initially. Drivers trying to reserve a region will fail early as we set the size to 0. If a real I/O space is present, the PCI/PCIe support code will re-adjust the values accordingly. Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused the originally reported crash. Reported-by: Faidon Liambotis <paravoid@debian.org> Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5626/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS:Netlogic: Remove redundant value in operation.Alexandru Juncu2013-08-261-2/+1Star
| | | | | | | | | | | | Removed parameters checked twice in logical OR operation. Suggested by coccinelle and manually verified. Signed-off-by: Alexandru Juncu <alexj@rosedu.org> Cc: jchandra@broadcom.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5627/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.David Daney2013-08-261-0/+14
| | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5638/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.David Daney2013-08-261-0/+2
| | | | | | | | | OCTEON2 need the same code. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5637/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use r4k_wait for OCTEON3 CPUs.David Daney2013-08-261-0/+1
| | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5636/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Probe for new OCTEON CPU/SoC types.David Daney2013-08-261-0/+7
| | | | | | | | | Add probing for CNF71XX, CN78XX and CN70XX. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5635/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CPU identifiers for more OCTEON family members.David Daney2013-08-261-1/+4
| | | | | | | | | Needed to support new SOCs. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5634/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: use generic-y where possibleJames Hogan2013-08-2617-58/+16Star
| | | | | | | | | | | | | | | | | | | | | | | | Use generic-y and remove headers in arch/mips/include/[uapi/]asm/Kbuild where the header just includes or is identical to the corresponding <asm-generic/*.h>. We can't do the same for uapi/asm/kvm_para.h because it's presence is explicitly checked in include/uapi/linux/Kbuild to decide whether to add kvm_para.h to header-y. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Christoph Lameter <cl@linux-foundation.org> Cc: Tejun Heo <tj@kernel.org> Cc: Dave Jones <davej@redhat.com> Cc: David Howells <dhowells@redhat.com> Cc: David Sharp <dhsharp@google.com> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: tlbex: Guard tlbmiss_handler_setup_pgdTony Wu2013-08-261-0/+2
| | | | | | | | | | | tlbmiss_handler_setup_pgd* are only referenced when CONFIG_MIPS_PGD_C0_CONTEXT is defined. Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: Jayachandran C. <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5601/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Handle OCTEON BBIT instructions in FPU emulator.David Daney2013-08-201-0/+26
| | | | | | | | | | The branch emulation needs to handle the OCTEON BBIT instructions, otherwise we get SIGILL instead of emulation. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: fix hardware interrupt routing for boot CPU != 0Florian Fainelli2013-08-051-2/+8
| | | | | | | | | | | | | | | | The hardware interrupt routing for boot CPU != 0 is wrong because it will route all the hardware interrupts to TP0 which is not the one we booted from. Fix this by properly checking which boot CPU we are booting from and updating the right interrupt mask for the boot CPU. This fixes booting on BCM3368 with bmips_smp_emabled = 0. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: jogo@openwrt.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5650/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: oprofile: Fix BUG due to smp_processor_id() in preemptible code.Ralf Baechle2013-08-052-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | current_cpu_type() is not preemption-safe. If CONFIG_PREEMPT is enabled then mipsxx_reg_setup() can be called from preemptible state. Added get_cpu()/put_cpu() pair to make it preemption-safe. This was found while testing oprofile with CONFIG_DEBUG_PREEMPT enable. /usr/zntestsuite # opcontrol --init /usr/zntestsuite # opcontrol --setup --event=L2_CACHE_ACCESSES:500 --event=L2_CACHE_MISSES:500 --no-vmlinux /usr/zntestsuite # opcontrol --start Using 2.6+ OProfile kernel interface. BUG: using smp_processor_id() in preemptible [00000000] code: oprofiled/1362 caller is mipsxx_reg_setup+0x11c/0x164 CPU: 0 PID: 1362 Comm: oprofiled Not tainted 3.10.4 #18 Stack : 00000006 70757465 00000000 00000000 00000000 00000000 80b173f6 00000037 80b10000 00000000 80b21614 88f5a220 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 89c49c00 89c49c2c 80721254 807b7927 8012c1d0 80b10000 80721254 00000000 00000552 88f5a220 80b1335c 807b78e6 89c49ba8 ... Call Trace: [<801099a4>] show_stack+0x64/0x7c [<80665520>] dump_stack+0x20/0x2c [<803a2250>] debug_smp_processor_id+0xe0/0xf0 [<8052df24>] mipsxx_reg_setup+0x11c/0x164 [<8052cd70>] op_mips_setup+0x24/0x4c [<80529cfc>] oprofile_setup+0x5c/0x12c [<8052b9f8>] event_buffer_open+0x78/0xf8 [<801c3150>] do_dentry_open.isra.15+0x2b8/0x3b0 [<801c3270>] finish_open+0x28/0x4c [<801d49b8>] do_last.isra.41+0x2cc/0xd00 [<801d54a0>] path_openat+0xb4/0x4c4 [<801d5c44>] do_filp_open+0x3c/0xac [<801c4744>] do_sys_open+0x110/0x1f4 [<8010f47c>] stack_done+0x20/0x44 Bug reported and original patch by Jerin Jacob <jerinjacobk@gmail.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Jerin Jacob <jerinjacobk@gmail.com>
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