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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-07-199-29/+7Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS fixes from Ralf Baechle: "Another round of MIPS fixes for 4.2. Things are looking quite decent at this stage but the recent work on the FPU support took its toll: - fix an incorrect overly restrictive ifdef - select O32 64-bit FP support for O32 binary compatibility - remove workarounds for Sibyte SB1250 Pass1 parts. There are rare fixing the workarounds is not worth the effort. - patch up an outdated and now incorrect comment" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6 CPU MIPS: SB1: Remove support for Pass 1 parts. MIPS: Require O32 FP64 support for MIPS64 with O32 compat MIPS: asm-offset.c: Patch up various comments refering to the old filename.
| * MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6 CPUMarkos Chandras2015-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6134d94923d0 ("MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6") added support for 64-bit FPU on a 32-bit MIPS R6 processor but it missed the 64-bit CPU case leading to FPU failures when requesting FR=1 mode (which is always the case for MIPS R6 userland) when running a 32-bit kernel on a 64-bit CPU. We also fix the MIPS R2 case. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: 6134d94923d0 ("MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6") Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: <stable@vger.kernel.org> # 4.0+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10734/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: SB1: Remove support for Pass 1 parts.Ralf Baechle2015-07-146-25/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass 1 parts had a number of significant erratas and were only available in small numbers and under NDA. Full support also required the use of a special toolchain that kept branches properly aligned. These workarounds were never upstreamed and the only toolchain known to have them is Montavista's GCC 3.0-based toolchain which completly obsoleted if not useless these days. So now that automated testing has tripped over the user of the -msb1-pass1-workarounds option, rather than fixing it remove support for pass 1 parts. Probably nobody will notice. I seem to own the last know pass 1 board and I haven't noticed another one in the wild in the past decade, at least. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Require O32 FP64 support for MIPS64 with O32 compatPaul Burton2015-07-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS32r6 code requires FP64 (ie. FR=1) support. Building a kernel with support for MIPS32r6 binaries but without support for O32 with FP64 is therefore a problem which can lead to incorrectly executed userland. CONFIG_MIPS_O32_FP64_SUPPORT is already selected when the kernel is configured for MIPS32r6, but not when the kernel is configured for MIPS64r6 with O32 compat support. Select CONFIG_MIPS_O32_FP64_SUPPORT in such configurations to prevent building kernels which execute MIPS32r6 userland incorrectly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v4.0- Cc: linux-mips@linux-mips.org Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: stable@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10674/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: asm-offset.c: Patch up various comments refering to the old filename.Ralf Baechle2015-07-142-3/+3
| | | | | | | | | | | | | | arch/mips/tools/offset.c was renamed to arch/mips/kernel/asm-offsets.c for v2.6.14. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | mm: clean up per architecture MM hook header filesLaurent Dufour2015-07-182-15/+1Star
|/ | | | | | | | | | | | | | | | | | | | | Commit 2ae416b142b6 ("mm: new mm hook framework") introduced an empty header file (mm-arch-hooks.h) for every architecture, even those which doesn't need to define mm hooks. As suggested by Geert Uytterhoeven, this could be cleaned through the use of a generic header file included via each per architecture asm/include/Kbuild file. The PowerPC architecture is not impacted here since this architecture has to defined the arch_remap MM hook. Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com> Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Vineet Gupta <vgupta@synopsys.com> Cc: Oleg Nesterov <oleg@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* MIPS: O32: Use compat_sys_getsockopt.Ralf Baechle2015-07-101-1/+1
| | | | | | | | | | | We were using the native syscall and that results in subtle breakage. This is the same issue as fixed in 077d0e65618f27b2199d622e12ada6d8f3dbd862 (MIPS: N32: Use compat getsockopt syscall) but that commit did fix it only for N32. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=100291
* MIPS: c-r4k: Extend way_string arrayPaul Burton2015-07-101-1/+3
| | | | | | | | | | | | | | The L2 cache in the I6400 core has 16 ways, so extend the way_string array to take such caches into account. [ralf@linux-mips.org: Other already supported CPUs are free to support more than 8 ways of cache as well.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10640/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Pistachio: Support CDMM & Fast Debug ChannelJames Hogan2015-07-102-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | Implement the mips_cdmm_phys_base() platform callback to provide a default Common Device Memory Map (CDMM) physical base address for the Pistachio SoC. This allows the CDMM in each VPE to be configured and probed for devices, such as the Fast Debug Channel (FDC). The physical address chosen is just below the default CPC address, which appears to also be unallocated. The FDC IRQ is also usable on Pistachio, and is routed through the GIC, so implement the get_c0_fdc_int() platform callback using gic_get_c0_fdc_int(), so the FDC driver doesn't have to fall back to polling. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Cc: linux-mips@linux-mips.org Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Patchwork: http://patchwork.linux-mips.org/patch/9749/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Make GIC FDC IRQ workaround Malta specificJames Hogan2015-07-101-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | Wider testing reveals that the Fast Debug Channel (FDC) interrupt is routed through the GIC just fine on Pistachio SoC, even though it contains interAptiv cores. Clearly the FDC interrupt routing problems previously observed on interAptiv and proAptiv cores are specific to the Malta FPGA bitstreams. Move the workaround for interAptiv and proAptiv out of gic_get_c0_fdc_int() in the GIC irqchip driver into Malta's get_c0_fdc_int() platform callback, to allow the Pistachio SoC to use the FDC interrupt. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/9748/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: c-r4k: Fix cache flushing for MT coresMarkos Chandras2015-07-103-4/+55
| | | | | | | | | | | | | | | | | | | | | MT_SMP is not the only SMP option for MT cores. The MT_SMP option allows more than one VPE per core to appear as a secondary CPU in the system. Because of how CM works, it propagates the address-based cache ops to the secondary cores but not the index-based ones. Because of that, the code does not use IPIs to flush the L1 caches on secondary cores because the CM would have done that already. However, the CM functionality is independent of the type of SMP kernel so even in non-MT kernels, IPIs are not necessary. As a result of which, we change the conditional to depend on the CM presence. Moreover, since VPEs on the same core share the same L1 caches, there is no need to send an IPI on all of them so we calculate a suitable cpumask with only one VPE per core. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10654/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Revert "MIPS: Kconfig: Disable SMP/CPS for 64-bit"Markos Chandras2015-07-091-1/+1
| | | | | | | | | | | | | | This reverts commit 6ca716f2e5571d25a3899c6c5c91ff72ea6d6f5e. SMP/CPS is now supported on 64bit cores. Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10592/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cps-vec: Use macros for various arithmetics and memory operationsMarkos Chandras2015-07-091-16/+16
| | | | | | | | | | | | | Replace lw/sw and various arithmetic instructions with macros so the code can work on 64-bit kernels as well. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10591/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0Markos Chandras2015-07-091-2/+2
| | | | | | | | | | | | | In preparation for 64-bit CPS support, we replace KSEG0 with CKSEG0 so 64-bit kernels can be supported. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10590/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bitMarkos Chandras2015-07-091-21/+21
| | | | | | | | | | | | | | The cps-vec code assumes O32 ABI and uses t4-t7 in quite a few places. This breaks the build on 64-bit. As a result of which, use the pseudo-registers ta0-ta3 to make the code compatible with 64-bit. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10589/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2Markos Chandras2015-07-091-2/+2
| | | | | | | | | | | | | mips32r2 is a subset of mips64r2, so we replace mips32r2 with mips64r2 in preparation for 64-bit CPS support. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10588/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LAMarkos Chandras2015-07-091-10/+10
| | | | | | | | | | | | | | | | | | | | The PTR_LA macro will pick the correct "la" or "dla" macro to load an address to a register. This gets rids of the following warnings (and others) when building a 64-bit CPS kernel: arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address [...] Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10587/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer castingMarkos Chandras2015-07-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") added hotplug support in the SMP/CPS implementation but it introduced a few build problems on 64-bit kernels due to pointer being casted to and from 'int' C types. We fix this problem by using 'unsigned long' instead which should match the size of the pointers in 32/64-bit kernels. Finally, we fix the comment since the CM base address is loaded to v1($3) instead of v0. Fixes the following build problems: arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt': arch/mips/kernel/smp-cps.c:366:17: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] [...] arch/mips/kernel/smp-cps.c: In function 'cps_cpu_die': arch/mips/kernel/smp-cps.c:427:13: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] cc1: all warnings being treated as errors Fixes: 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10586/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix erroneous JR emulation for MIPS R6Markos Chandras2015-07-091-1/+1
| | | | | | | | | | | | | | | | | | Commit 5f9f41c474befb4ebbc40b27f65bb7d649241581 ("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") added support for emulating the JR instruction on MIPS R6 cores but that introduced a bug which could be triggered when hitting a JALR opcode because the code used the wrong field in the 'r_format' struct to determine the instruction opcode. This lead to crashes because an emulated JALR instruction was treated as a JR one when the R6 emulator was turned off. Fixes: 5f9f41c474be ("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") Cc: <stable@vger.kernel.org> # 4.0+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10583/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix branch emulation for BLTC and BGEC instructionsMarkos Chandras2015-07-092-4/+4
| | | | | | | | | | | | | | | | | | | | Commits f1b44067c19258b7614e3cd09dfe8d8e12ff5895 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") and commit a8ff66f52d3f17b5ae793955270675c197f73d6c ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions") added support for emulating various branch compact instructions. However, it missed the case for those which use the old BLEZL and BGTZL opcodes leading to random crashes when the R6 emulator is disabled. We fix this by ensuring that the 'rt' field is not zero which is always true for these branch compact instructions. Fixes: f1b44067c192 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") Fixes: a8ff66f52d3f ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions") Cc: <stable@vger.kernel.org> # 4.0+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10582/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: kernel: traps: Fix broken indentationMarkos Chandras2015-07-091-4/+4
| | | | | | | | | | | | Fix broken indentation caused by the SMTC removal commit b633648c5ad3cfbda0b3daea50d2135d44899259 ("MIPS: MT: Remove SMTC support") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: b633648c5ad3c ("MIPS: MT: Remove SMTC support") Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: bootmem: Don't use memory holes for page bitmapAlexander Sverdlin2015-07-091-8/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f9a7febd leads to a fact that mapstart and therefore a page bitmap for bootmem allocator immediately follows initrd_end. This doesn't always work well on Octeon, where there are holes in PFN ranges (refer to 5b3b1688 and 4MB-aligned PFN allocation). Depending on the inird location it could happen, that mapstart would be in an area not allocated by plat_mem_setup() in arch/mips/cavium-octeon/setup.c, but in the alignment hole between initrd and the next PFN area. Later on this memory will be unconditionally made available to buddy allocator at the end of free_all_bootmem_core() (mm/bootmem.c). All of this results in Linux using the memory not designated for Linux in Octeon's plat_mem_setup(), which in turn means corruption of the memory used by another OS/baremetal code on the same SoC. It doesn't look to me as a problem of Octeon platform code, but rather as an inability of f9a7febd to deal correctly with the fragmented memory-mappings. Proposed fix moves the check for initrd address to the same calculation-loop in bootmem_init() (arch/mips/kernel/setup.c), which also accounts for kernel code location. This should result in mapstart located starting from the first PFN area after kernel code AND initrd. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Cc: linux-mips@linux-mips.org Cc: David Daney <david.daney@cavium.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: Joe Perches <joe@perches.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Yusuf Khan <yusuf.khan@nokia.com> Cc: Michael Kreuzer <michael.kreuzer@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Patchwork: https://patchwork.linux-mips.org/patch/10594/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: O32: Do not handle require 32 bytes from the stack to be readable.Ralf Baechle2015-07-082-18/+52
| | | | | | | | | | | | | | | | | | Commit 46e12c07b3b9603c60fc1d421ff18618241cb081 (MIPS: O32 / 32-bit: Always copy 4 stack arguments.) change the O32 syscall handler to always load four arguments from the userspace stack even for syscalls that require fewer or no arguments to be copied. This removes a large table from kernel space and need to maintain it. It appeared that it was ok the implementation chosen requires 16 bytes of readable stack space above the user stack pointer. Turned out a few threading implementations munmap the user stack before the thread exits resulting in errors due to the unreadable stack. We now treat any failed load as a if the loaded value was zero and let the actual syscall deal with the situation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS, CPUFREQ: Fix spelling of Institute.Ralf Baechle2015-07-0710-10/+10
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lemote 2F: Fix build caused by recent mass rename.Ralf Baechle2015-07-071-1/+1
| | | | | | | | | | CC arch/mips/loongson64/lemote-2f/clock.o /home/ralf/src/linux/linux-mips/arch/mips/loongson64/lemote-2f/clock.c:18:40: fatal error: asm/mach-loongson/loongson.h: No such file or directory #include <asm/mach-loongson/loongson.h> ^ compilation terminated. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge tag 'devicetree-for-linus' of ↵Linus Torvalds2015-07-022-5/+0Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux Pull devicetree updates from Grant Likely: "A whole lot of bug fixes. Nothing stands out here except the ability to enable CONFIG_OF on every architecture, and an import of a newer version of dtc" * tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux: (22 commits) of/irq: Rename "intc_desc" to "of_intc_desc" to fix OF on sh of/irq: Fix pSeries boot failure Documentation: DT: Fix a typo in the filename "lantiq,<chip>-pinumx.txt" of: define of_find_node_by_phandle for !CONFIG_OF of/address: use atomic allocation in pci_register_io_range() of: Add vendor prefix for Zodiac Inflight Innovations dt/fdt: add empty versions of early_init_dt_*_memory_arch of: clean-up unnecessary libfdt include paths of: make unittest select OF_EARLY_FLATTREE instead of depend on it of: make CONFIG_OF user selectable MIPS: prepare for user enabling of CONFIG_OF of/fdt: fix argument name and add comments of unflatten_dt_node() of: return NUMA_NO_NODE from fallback of_node_to_nid() tps6507x.txt: Remove executable permission of/overlay: Grammar s/an negative/a negative/ of/fdt: Make fdt blob input parameters of unflatten functions const of: add helper function to retrive match data of: Grammar s/property exist/property exists/ of: Move OF flags to be visible even when !CONFIG_OF scripts/dtc: Update to upstream version 9d3649bd3be245c9 ...
| * Merge remote-tracking branch 'robh/for-next' into devicetree/nextGrant Likely2015-06-304-6/+2Star
| |\
| | * of: clean-up unnecessary libfdt include pathsRob Herring2015-06-052-5/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the libfdt include fixups to use "" instead of <> in the latest dtc import in commit 4760597 (scripts/dtc: Update to upstream version 9d3649bd3be245c9), it is no longer necessary to add explicit include paths to use libfdt. Remove these across the kernel. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Acked-by: Michael Ellerman <mpe@ellerman.id.au> Acked-by: Grant Likely <grant.likely@linaro.org> Cc: linux-mips@linux-mips.org Cc: linuxppc-dev@lists.ozlabs.org
| | * MIPS: prepare for user enabling of CONFIG_OFRob Herring2015-06-052-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to allow users to enable DeviceTree without arch or machine selecting it, we need to fix build errors on MIPS. When CONFIG_OF is enabled, device_tree_init cannot be resolved. This is trivially fixed by using CONFIG_USE_OF instead of CONFIG_OF for prom.h. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Grant Likely <grant.likely@lianro.org> Cc: linux-mips@linux-mips.org
* | | Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2015-07-024-8/+7Star
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Thomas Gleixner: "This contains: - a series of fixes for interrupt drivers to prevent a potential race when installing a chained interrupt handler - a fix for cpumask pointer misuse - a fix for using the wrong interrupt number from struct irq_data - removal of unused code and outdated comments - a few new helper functions which allow us to cleanup the interrupt handling code further in 4.3 I decided against doing the cleanup at the end of this merge window and rather do the preparatory steps for 4.3, so we can run the final ABI change at the end of the 4.3 merge window with less risk" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits) ARM/LPC32xx: Use irq not hwirq for __irq_set_handler_locked() genirq: Implement irq_set_handler_locked()/irq_set_chip_handler_name_locked() genirq: Introduce helper irq_desc_get_irq() genirq: Remove irq_node() genirq: Clean up outdated comments related to include/linux/irqdesc.h mn10300: Fix incorrect use of irq_data->affinity MIPS/ralink: Fix race in installing chained IRQ handler MIPS/pci: Fix race in installing chained IRQ handler MIPS/ath25: Fix race in installing chained IRQ handler MIPS/ath25: Fix race in installing chained IRQ handler m68k/psc: Fix race in installing chained IRQ handler avr32/at32ap: Fix race in installing chained IRQ handler sh/intc: Fix race in installing chained IRQ handler sh/intc: Fix potential race in installing chained IRQ handler pinctrl/sun4i: Fix race in installing chained IRQ handler pinctrl/samsung: Fix race in installing chained IRQ handler pinctrl/samsung: Fix race in installing chained IRQ handler pinctrl/exynos: Fix race in installing chained IRQ handler pinctrl/st: Fix race in installing chained IRQ handler pinctrl/adi2: Fix race in installing chained IRQ handler ...
| * | | MIPS/ralink: Fix race in installing chained IRQ handlerThomas Gleixner2015-06-251-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org
| * | | MIPS/pci: Fix race in installing chained IRQ handlerThomas Gleixner2015-06-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: linux-mips@linux-mips.org
| * | | MIPS/ath25: Fix race in installing chained IRQ handlerThomas Gleixner2015-06-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: linux-mips@linux-mips.org
| * | | MIPS/ath25: Fix race in installing chained IRQ handlerThomas Gleixner2015-06-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: linux-mips@linux-mips.org
* | | | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-06-27239-2694/+3000
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: - Improvements to the tlb_dump code - KVM fixes - Add support for appended DTB - Minor improvements to the R12000 support - Minor improvements to the R12000 support - Various platform improvments for BCM47xx - The usual pile of minor cleanups - A number of BPF fixes and improvments - Some improvments to the support for R3000 and DECstations - Some improvments to the ATH79 platform support - A major patchset for the JZ4740 SOC adding support for the CI20 platform - Add support for the Pistachio SOC - Minor BMIPS/BCM63xx platform support improvments. - Avoid "SYNC 0" as memory barrier when unlocking spinlocks - Add support for the XWR-1750 board. - Paul's __cpuinit/__cpuinitdata cleanups. - New Malta CPU board support large memory so enable ZONE_DMA32. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits) MIPS: spinlock: Adjust arch_spin_lock back-off time MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA MIPS: BCM47xx: Simplify handling SPROM revisions MIPS: Cobalt Don't use module_init in non-modular MTD registration. MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/ MIPS: use for_each_sg() MIPS: BCM47xx: Don't select BCMA_HOST_PCI MIPS: BCM47xx: Add helper variable for storing NVRAM length MIPS: IRQ/IP27: Move IRQ allocation API to platform code. MIPS: Replace smp_mb with release barrier function in unlocks. MIPS: i8259: DT support MIPS: Malta: Basic DT plumbing MIPS: include errno.h for ENODEV in mips-cm.h MIPS: Define GCR_GIC_STATUS register fields MIPS: BPF: Introduce BPF ASM helpers MIPS: BPF: Use BPF register names to describe the ABI MIPS: BPF: Move register definition to the BPF header MIPS: net: BPF: Replace RSIZE with SZREG MIPS: BPF: Free up some callee-saved registers MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers ...
| * | | | MIPS: spinlock: Adjust arch_spin_lock back-off timeMarkos Chandras2015-06-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it similar to the trylock and R10000_LLSC_WAR cases. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9789/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: asmmacro: Ensure 64-bit FP registers are used with MSAMarkos Chandras2015-06-241-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This silences warnings like the following one when building with the latest binutils: arch/mips/kernel/genex.S: Assembler messages: arch/mips/kernel/genex.S:438: Warning: the `msa' extension requires 64-bit FPRs [ralf@linux-mips.org: Markos says binutils 2.25 and some 2.24 snapshots are affected.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9745/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: BCM47xx: Simplify handling SPROM revisionsRafał Miłecki2015-06-211-44/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the big SPROM cleanup moving code to the bcm47xx_sprom_fill_auto we ended up with few tiny functions, two of them being identical. Let's get rid of these [12]-liners. This also stops extracting higher SPROM revisions as revision 1. Now we have that function nicely handling revisions we don't need it. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/10569/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Cobalt Don't use module_init in non-modular MTD registration.Paul Gortmaker2015-06-211-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit 34b1252bd91851f77f89fbb6829a04efad900f41 ("MIPS: Cobalt: Do not build MTD platform device registration code as module.") this file became built-in instead of modular. So we should also stop using module_init as an alias for __initcall as that can be rather misleading. Fix this up now, so that we can relocate module_init from init.h into module.h in the future. If we don't do this, we'd have to add module.h to obviously non-modular code, and that would be a worse thing. Direct use of __initcall is discouraged, vs prioritized ones. Use of device_initcall is consistent with what __initcall maps onto, and hence does not change the init order, making the impact of this change zero. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10549/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/Rafał Miłecki2015-06-213-247/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After Broadcom switched from MIPS to ARM for their home routers we need to have NVRAM driver in some common place (not arch/mips/). As explained in Kconfig, this driver is responsible for parsing SoC configuration data that is passed to the kernel in flash from the bootloader firmware called "CFE". We were thinking about putting it in bus directory, however there are two possible buses for MIPS: drivers/ssb/ and drivers/bcma/. So this won't fit there and this is why I would like to move this driver to the drivers/firmware/. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Seiji Aguchi <seiji.aguchi@hds.com> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Mike Waychison <mikew@google.com> Cc: Roy Franz <roy.franz@linaro.org> Cc: Matt Fleming <matt.fleming@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Patchwork: https://patchwork.linux-mips.org/patch/10544/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: use for_each_sg()Akinobu Mita2015-06-211-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replaces the plain loop over the sglist array with for_each_sg() macro which consists of sg_next() function calls. Since MIPS doesn't select ARCH_HAS_SG_CHAIN, it is not necessary to use for_each_sg() in order to loop over each sg element. But this can help find problems with drivers that do not properly initialize their sg tables when CONFIG_DEBUG_SG is enabled. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Cc: akpm@linux-foundation.org Cc: linux-mips@linux-mips.org Cc: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9930/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: BCM47xx: Don't select BCMA_HOST_PCIRafał Miłecki2015-06-211-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SoC may have non-Broadcom PCI device attached or one may want to use totally different PCI driver. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/10537/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: BCM47xx: Add helper variable for storing NVRAM lengthRafał Miłecki2015-06-211-21/+16Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simplifies code just a bit (also maybe makes it a bit more intuitive?) and will allow us to stop storing header. Right now we copy whole NVRAM including its header to the internal buffer. It is not needed to store a header as we don't access all these details like CRC, flags, etc. The next improvement that should follow is copying only the real contents. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: Arend van Spriel <arend@broadcom.com> Cc: Hante Meuleman <meuleman@broadcom.com> Patchwork: https://patchwork.linux-mips.org/patch/10535/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: IRQ/IP27: Move IRQ allocation API to platform code.Ralf Baechle2015-06-213-41/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allocate_irqno, free_irqno and alloc_legacy_irqno are a simple allocator for interrupt numbers from the days when the numer of interrupts was still fixed to NR_IRQS. This was necessary for the SGI IP27 architecture which with its flexible architecture and possibly large number of interrupts doesn't easily fit into the old pattern. These days there are better alternatives. Move the allocation code from the arch generic code to the only platform using it, the SGI IP27 aka Origin 200/2000, Onyx 2. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Replace smp_mb with release barrier function in unlocks.Leonid Yegoshin2015-06-212-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Repleace smp_mb() in arch_write_unlock() and __clear_bit_unlock() to smp_mb__before_llsc() call which does "release" barrier functionality. It seems like it was missed in commit f252ffd50c97dae87b45f1dbad24f71358ccfbd6 during introduction of "acquire" and "release" semantics. [ralf@linux-mips: The original patch submission was labelled a fix but actually it replaces a barrier with another less restrictive type of barrier so it doesn't fix any ill behaviour but rather squeezes out a tad better performance. Further improvments will be possible once smp_release() has been merged.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: benh@kernel.crashing.org Cc: will.deacon@arm.com Cc: linux-kernel@vger.kernel.org Cc: markos.chandras@imgtec.com Cc: macro@linux-mips.org Cc: Steven.Hill@imgtec.com Cc: alexander.h.duyck@redhat.com Cc: davem@davemloft.net Patchwork: https://patchwork.linux-mips.org/patch/10507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: i8259: DT supportPaul Burton2015-06-212-2/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support probing the i8259 programmable interrupt controller, as found on the Malta board, and using its interrupts via device tree. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/10114/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Malta: Basic DT plumbingPaul Burton2015-06-216-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Build a DT for the Malta platform into the kernel, load it & probe devices from it. The DT is essentially empty at this point, devices will be added in further patches. [ralf@linux-mips.org: Fixed conflicts.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/10119/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: include errno.h for ENODEV in mips-cm.hPaul Burton2015-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A later patch in this series will include mips-cm.h but does not require errno.h. This leads to a build failure with ENODEV undeclared. Include errno.h from mips-cm.h to pull in the appropriate definition and avoid the build failure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/10113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Define GCR_GIC_STATUS register fieldsPaul Burton2015-06-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add definitions for the GICEX field in the GCR_GIC_STATUS register to mips-cm.h for use in a later patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/10112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: BPF: Introduce BPF ASM helpersMarkos Chandras2015-06-214-145/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces BPF ASM helpers for MIPS and MIPS64 kernels. The purpose of this patch is to twofold: 1) We are now able to handle negative offsets instead of either falling back to the interpreter or to simply not do anything and bail out. 2) Optimize reads from the packet header instead of calling the C helpers Because of this patch, we are now able to get rid of quite a bit of code in the JIT generation process by using MIPS optimized assembly code. The new assembly code makes the test_bpf testsuite happy with all 60 test passing successfully compared to the previous implementation where 2 tests were failing. Doing some basic analysis in the results between the old implementation and the new one we can obtain the following summary running current mainline on an ER8 board (+/- 30us delta is ignored to prevent noise from kernel scheduling or IRQ latencies): Summary: 22 tests are faster, 7 are slower and 47 saw no improvement with the most notable improvement being the tcpdump tests. The 7 tests that seem to be a bit slower is because they all follow the slow path (bpf_internal_load_pointer_neg_helper) which is meant to be slow so that's not a problem. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: netdev@vger.kernel.org Cc: "David S. Miller" <davem@davemloft.net> Cc: Alexei Starovoitov <ast@plumgrid.com> Cc: Daniel Borkmann <dborkman@redhat.com> Cc: Hannes Frederic Sowa <hannes@stressinduktion.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/10530/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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