summaryrefslogtreecommitdiffstats
path: root/arch/mips
Commit message (Collapse)AuthorAgeFilesLines
* MIPS/EDAC: Improve OCTEON EDAC support.David Daney2012-12-133-14/+58
| | | | | | | | | Some initialization errors are reported with the existing OCTEON EDAC support patch. Also some parts have more than one memory controller. Fix the errors and add multiple controllers if present. Signed-off-by: David Daney <david.daney@cavium.com>
* MIPS: OCTEON: Add definitions for OCTEON memory contoller registers.David Daney2012-12-131-0/+3457
| | | | Signed-off-by: David Daney <david.daney@cavium.com>
* MIPS: OCTEON: Add OCTEON family definitions to octeon-model.hDavid Daney2012-12-131-0/+6
| | | | | | Used by follow-on EDAC patches. Signed-off-by: David Daney <david.daney@cavium.com>
* MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree.David Daney2012-12-134-111/+0Star
| | | | | | | | | | | | | The patch needs to eliminate the definition of OCTEON_IRQ_BOOTDMA so that the device tree code can map the interrupt, so in order to not temporarily break things, we do a single patch to both the interrupt registration code and the pata_octeon_cf driver. Also rolled in is a conversion to use hrtimers and corrections to the timing calculations. Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David Daney <david.daney@cavium.com>
* MIPS: Remove usage of CEVT_R4K_LIB config option.Ralf Baechle2012-12-133-8/+2Star
| | | | | | | | | | | | | | | | | | Manuel Lauss <manuel.lauss@gmail.com> writes: I introduced it as a fallback because early revisions of Alchemy hardware we shipped had a non-functional 32kHz timer and had to rely on the r4k timer instead. Previously the r4k timer was initialized regardless, but it's useless with the "wait" instruction. So long story short: I need either the on-chip 32kHz timer OR the r4k timer if the 32kHz one is unusable, but not both, and r4k timer is useless when au1k_idle is in use. The current in-kernel Alchemy boards all work with the 32kHz timer, so I'm not against removing R4K_LIB symbols. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove usage of CSRC_R4K_LIB config option.Steven J. Hill2012-12-133-7/+3Star
| | | | | | | | | | | | | | | | | | | Manuel Lauss <manuel.lauss@gmail.com> writes: I introduced it as a fallback because early revisions of Alchemy hardware we shipped had a non-functional 32kHz timer and had to rely on the r4k timer instead. Previously the r4k timer was initialized regardless, but it's useless with the "wait" instruction. So long story short: I need either the on-chip 32kHz timer OR the r4k timer if the 32kHz one is unusable, but not both, and r4k timer is useless when au1k_idle is in use. The current in-kernel Alchemy boards all work with the 32kHz timer, so I'm not against removing R4K_LIB symbols. Signed-off-by: Steven J. Hill <sjhill@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: use part_probe_types to specificy the partition parser to useFlorian Fainelli2012-12-131-0/+3
| | | | | | | | | | | | This patch changes the physmap-flash platform data on AR7 to pass the correct partition parser: ar7part to used by the "physmap-flash" mapping driver so we get the partitions probed correctly. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: blogic@openwrt.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4654/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Fix typo in "endianness" in dma.cMasanari Iida2012-12-131-3/+3
| | | | | | | | | | Correct spelling typo ENDIANESS to ENDIANNESS in arc/mips/lantiq/xway/dma.c Signed-off-by: Masanari Iida <standby24x7@gmail.com> Cc: trivial@kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4613/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig: Rename several firmware related config symbols.Ralf Baechle2012-12-137-34/+34
| | | | | | | | | | | | With the upcoming merge of the ARC architecture there is a small likelyhood of conflicting use for the CONFIG_ARC config symbol. Rename it to CONFIG_FW_ARC. Also rename CONFIG_ARC32 to CONFIG_FW_ARC32, CONFIG_ARC64 to CONFIG_FW_ARC64. For consistence also rename CONFIG_SNIPROM to CONFIG_FW_SNIPROM and CONFIG_CFE to CONFIG_FW_CFE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Add kexec and kdump supportRalf Baechle2012-12-136-9/+335
| | | | | | | | | | | | [ralf@linux-mips.org: Original patch by Maxim Uvarov <muvarov@gmail.com> with plenty of further shining, polishing, debugging and testing by me.] Signed-off-by: Maxim Uvarov <muvarov@gmail.com> Cc: linux-mips@linux-mips.org Cc: kexec@lists.infradead.org Cc: horms@verge.net.au Patchwork: https://patchwork.linux-mips.org/patch/1026/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: kdump: Add supportRalf Baechle2012-12-1311-9/+396
| | | | | | | | | | | | [ralf@linux-mips.org: Original patch by Maxim Uvarov <muvarov@gmail.com> with plenty of further shining, polishing, debugging and testing by me.] Signed-off-by: Maxim Uvarov <muvarov@gmail.com> Cc: linux-mips@linux-mips.org Cc: kexec@lists.infradead.org Cc: horms@verge.net.au Patchwork: https://patchwork.linux-mips.org/patch/1025/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig: Enable drivers/firmware/KconfigRalf Baechle2012-12-121-0/+2
| | | | | | | | This allows the use of /sys/firmware/memmap for MIPS platforms. kexec-tools may use /sys/firmware/memmap though current versions parse /proc/iomem. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix harmlessly missing else statement.Ralf Baechle2012-12-121-5/+8
| | | | | | | | | | | | | The actual bug is a missing else statement - but really this should be expressed using a switch() statement. Found by Al Viro who writes "the funny thing is, it *does* work only because r2 is syscall number and syscall number around 512 => return value being ENOSYS and not one of ERESTART... so we really can't hit the first if and emerge from it with ERESTART_RESTARTBLOCK. still wrong to write it that way..." Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove leftovers from the IRIX binary compat code.Ralf Baechle2012-12-122-8/+0Star
| | | | | | | | | 2957c9e61ee9c37e7ebf2c8acab03e073fe942fd (kernel.org) rsp. b934da913f236bca00c41d9e386e980586000461 (lmo) [[MIPS] IRIX: Goodbye and thanks for all the fish] left two fields in struct thread_struct which were only being used for the IRIX compat code. Remove them. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Simplify code by assuming CONFIG_64BIT is always set.Ralf Baechle2012-12-122-33/+0Star
| | | | | | No 32-bit kernels supported on Octeon. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Remove use of CONFIG_64BIT_PHYS_ADDR.Ralf Baechle2012-12-121-1/+1
| | | | | | | Only supporting 64-bit kernels there is no point in depending on this symbol. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Remove highmem code.Ralf Baechle2012-12-121-4/+0Star
| | | | | | | On Cavium hardware only 64-bit kernels are supported so CONFIG_HIGHMEM is never set. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cavium: Update defconfigDavid Daney2012-12-121-17/+81
| | | | | | | | | | | Turn on support for most hardware present on OCTEON development boards as well as some filesystems and SATA controllers so we can boot off of a disk or CF Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4426/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Transparent Huge Pages supportRalf Baechle2012-12-128-6/+243
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cavium: Add EDAC support.Ralf Baechle2012-12-124-23/+58
| | | | | | | | | | | | | | | | | | Drivers for EDAC on Cavium. Supported subsystems are: o CPU primary caches. These are parity protected only, so only error reporting. o Second level cache - ECC protected, provides SECDED. o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will will only initialize if ECC is enabled on a system so is safe to run on non-ECC memory. o PCI: Parity error reporting Since it is very hard to test this sort of code the implementation is very conservative and uses polling where possible for now. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
* MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORTDavid Daney2012-12-127-20/+23
| | | | | | | | We need Huge TLBs for HUGETLB_PAGE, or the soon to follow TRANSPARENT_HUGEPAGE. collect this information under a single Kconfig symbol. Signed-off-by: David Daney <david.daney@cavium.com>
* MIPS: page.h: Provide more readable definition for PAGE_MASK.Ralf Baechle2012-12-121-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: tlbex: Better debug output.Ralf Baechle2012-11-262-48/+124
| | | | | | | | | | | | Pgtable bits are assigned dynamically depending on processor feature and statically based on kernel configuration. To make sense out of the disassembled TLB exception handlers a list of the actual assignments used for a particular configuration and hardware setup can be very useful. Output the actual TLB exception handlers in a format that simplifies their post processsing from dmesg output. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: N32: Remove unused defines.Ralf Baechle2012-11-261-6/+0Star
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: pgtable.h: Remove commented out debugging printk.Ralf Baechle2012-11-261-1/+0Star
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove R5000A.Ralf Baechle2012-11-262-5/+3Star
| | | | | | | From a software perspective R5000 and R5000A are the same thing which is why the symbol CPU_R5000A never got used, so finally delete it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix crash that occurs when function tracing is enabledAl Cooper2012-11-231-4/+4
| | | | | | | | | | | | | | A recent patch changed some irq routines from inlines to functions. These routines are called by the tracer code. Now that they're functions, if they are compiled for function tracing they will call the tracer and crash the system due to infinite recursion. The fix disables tracing in these functions by using "notrace" in the function definition. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: David Daney <david.daney@cavium.com> Pathchwork: https://patchwork.linux-mips.org/patch/4564/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Merge overlapping bootmem rangesRalf Baechle2012-11-231-6/+20
| | | | | | | | | | | | | | | Without this, we may end up with something like this in /proc/iomem: 01100000-014fffff : System RAM 01100000-013bf48f : Kernel code 013bf490-0149e01f : Kernel data 01500000-0c0fffff : System RAM but the two System RAM ranges should be one single range. This particular case will result in kexec failure on Octeon systems if the kernel being loaded by kexec is bigger than the already running kernel. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips, arc: fix build failureDavid Rientjes2012-11-161-0/+1
| | | | | | | | | | | | | | | Using a cross-compiler to fix another issue, the following build error occurred for mips defconfig: arch/mips/fw/arc/misc.c: In function 'ArcHalt': arch/mips/fw/arc/misc.c:25:2: error: implicit declaration of function 'local_irq_disable' Fix it up by including irqflags.h. Signed-off-by: David Rientjes <rientjes@google.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* MIPS: Malta: Fix interupt number of CBUS UART.Ralf Baechle2012-11-131-1/+2
| | | | | | | | | | | | | | | | The CBUS UART's interrupt number was wrong conflicting with the interrupt being tied to the Intel PIIX4. Since the PIIX4's interrupt is registered before the CBUS UART which is not being used on most systems this would not be noticed. Attempts to open the ttyS2 CBUS UART would result in: genirq: Flags mismatch irq 18. 00000000 (serial) vs. 00010000 (XT-PIC cascade) serial_link_irq_chain: request failed: -16 for irq: 18 Qemu was written to match the kernel so will need to be fixed also. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpusJim Quinlan2012-11-093-133/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | For non MIPSr2 processors, such as the BMIPS 5000, calls to arch_local_irq_disable() and others may be preempted, and in doing so a stale value may be restored to c0_status. This fix disables preemption for such processors prior to the call and enables it after the call. Those functions that needed this fix have been "outlined" to mips-atomic.c, as they are no longer good candidates for inlining. This bug was observed in a BMIPS 5000, occuring once every few hours in a continuous reboot test. It was traced to the write_lock_irq() function which was being invoked in release_task() in exit.c. By placing a number of "nops" inbetween the mfc0/mtc0 pair in arch_local_irq_disable(), which is called by write_lock_irq(), we were able to greatly increase the occurance of this bug. Similarly, the application of this commit silenced the bug. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove irqflags.h dependency from bitops.hJim Quinlan2012-11-095-83/+214
| | | | | | | | | | | | | | | The "else clause" of most functions in bitops.h invoked raw_local_irq_{save,restore}() and in doing so had a dependency on irqflags.h. This fix moves said code to bitops.c, removing the dependency. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: bitops.h: Change use of 'unsigned short' to 'int'Jim Quinlan2012-11-091-7/+7
| | | | | | | | | | | | | [ralf@linux-mips.org: No functional change but it's consistent with how use types elsewhere in the code.] Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4319/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: compat: Delete now unused TIF_32BIT.Ralf Baechle2012-11-091-6/+0Star
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: compat: Implement is_compat_task() by testing for 32-bit address space.Ralf Baechle2012-11-091-1/+1
| | | | | | | | | | | | So far is_compat_task() was testing for 32-bit registers if O32 support was enabled and if O32 support was disabled but N32 enabled it was testing for 32-bit address space. So if both O32 and N32 were enabled a N32 task was not considered a compat task, whops. This still leaves potential cases where O32 and N32 need different treatment unsolved. But that's another commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: compat: Fix use of TIF_32BIT_ADDR vs _TIF_32BIT_ADDRRalf Baechle2012-11-091-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-10-188-25/+68
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS fixes from Ralf Baechle: "Random small fixes across the MIPS code." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: CMP: Fix physical core number calculation logic MIPS: JZ4740: Forward declare struct uart_port in header. MIPS: JZ4740: Fix '#include guard' in serial.h MIPS: hugetlbfs: Fix hazard between tlb write and pagemask restoration. MIPS: Restore pagemask after dumping the TLB. MIPS: Hugetlbfs: Handle huge pages correctly in pmd_bad() MIPS: R5000: Fix TLB hazard handling. MIPS: tlbex: Deal with re-definition of label MIPS: Make __{,n,u}delay declarations match definitions and generic delay.h
| * MIPS: CMP: Fix physical core number calculation logicjerin jacob2012-10-181-1/+1
| | | | | | | | | | | | | | | | | | | | The CPUNum Field in EBase register is 10bit wide, so after 1 bit right shift, the mask value should be 0x1ff. Signed-off-by: jerin jacob <jerinjacobk@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4420/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: JZ4740: Forward declare struct uart_port in header.Ralf Baechle2012-10-171-0/+2
| | | | | | | | | | | | | | | | | | As suggested by Geert Uytterhoeven <geert@linux-m68k.org>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: linux-mips@linux-mips.org Cc: Lars-Peter Clausen <lars@metafoo.de>
| * MIPS: JZ4740: Fix '#include guard' in serial.hAntony Pavlov2012-10-171-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Cc: linux-mips@linux-mips.org Cc: Lars-Peter Clausen <lars@metafoo.de> Patchwork: https://patchwork.linux-mips.org/patch/4424/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: hugetlbfs: Fix hazard between tlb write and pagemask restoration.Ralf Baechle2012-10-171-0/+1
| | | | | | | | | | | | | | On some CPU the write to pagemask might complete before the TLB write instruction reads from the pagemask register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Restore pagemask after dumping the TLB.Ralf Baechle2012-10-171-1/+3
| | | | | | | | | | | | Or bad things might happen if the last TLB entry isn't a basic size page. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Hugetlbfs: Handle huge pages correctly in pmd_bad()Ralf Baechle2012-10-171-1/+14
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: R5000: Fix TLB hazard handling.Ralf Baechle2012-10-161-15/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and RM5271) are basically the same CPU core and all are documented to require two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0, c0_entrylo1 or c0_index. So far we were only providing on cycle before / after a TLBR/TLBWI for R5000 but 3 cycles before and 1 cycles after for the Nevadas. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: tlbex: Deal with re-definition of labelRalf Baechle2012-10-161-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The microassembler used in tlbex.c does not notice if a label is redefined resulting in relocations against such labels silently missrelocated. The issues exists since commit add6eb04776db4189ea89f596cbcde31b899be9d [Synthesize TLB exception handlers at runtime.] in 2.6.10 and went unnoticed for so long because the relocations for the affected branches got computed to do something *almost* sensible. The issue affects R4000, R4400, QED/IDT RM5230, RM5231, RM5260, RM5261, RM5270 and RM5271 processors. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Make __{,n,u}delay declarations match definitions and generic delay.hDavid Daney2012-10-162-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At some recent point arch/mips/include/asm/delay.h has started being included into csrc-octeon.c where the __?delay() functions are defined. This causes a compile failure due to conflicting declarations and definitions of the functions. It turns out that the generic definitions in arch/mips/lib/delay.c also conflict. Proposed fix: Declare the functions to take unsigned long parameters just like asm-generic (and x86) does. Update __delay to agree (__ndelay and __udelay need no change). Bonus: Get rid of 'inline' from __delay() definition, as it is globally visible, and the compiler should be making this decision itself (it does in fact inline the function without being told to). Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | UAPI: Place comments in empty arch Kbuilds to make them non-emptyDavid Howells2012-10-171-0/+1
|/ | | | | | | | | | | | | | | | | | | | | Place comments in: arch/mips/include/asm/Kbuild arch/tile/include/arch/Kbuild to make them non-empty so that the patch program doesn't remove them when it reduces them to nothing. Possibly they should be just deleted, but it's possible that they'll acquire generic-y or genhdr-y lines in future, so I'm keeping them around for the moment. Note that MIPS will compile happily if the file is deleted instead. I haven't tested TILE, but I suspect it will be the same there. Signed-off-by: David Howells <dhowells@redhat.com> cc: Ralf Baechle <ralf@linux-mips.org> cc: Chris Metcalf <cmetcalf@tilera.com>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-10-14106-4493/+2886Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS update from Ralf Baechle: "Cleanups and fixes for breakage that occured earlier during this merge phase. Also a few patches that didn't make the first pull request. Of those is the Alchemy work that merges code for many of the SOCs and evaluation boards thus among other code shrinkage, reduces the number of MIPS defconfigs by 5." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (22 commits) MIPS: SNI: Switch RM400 serial to SCCNXP driver MIPS: Remove unused empty_bad_pmd_table[] declaration. MIPS: MT: Remove kspd. MIPS: Malta: Fix section mismatch. MIPS: asm-offset.c: Delete unused irq_cpustat_t struct offsets. MIPS: Alchemy: Merge PB1100/1500 support into DB1000 code. MIPS: Alchemy: merge PB1550 support into DB1550 code MIPS: Alchemy: Single kernel for DB1200/1300/1550 MIPS: Optimize TLB refill for RI/XI configurations. MIPS: proc: Cleanup printing of ASEs. MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required. MIPS: Add detection of DSP ASE Revision 2. MIPS: Optimize pgd_init and pmd_init MIPS: perf: Add perf functionality for BMIPS5000 MIPS: perf: Split the Kconfig option CONFIG_MIPS_MT_SMP MIPS: perf: Remove unnecessary #ifdef MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt) MIPS: perf: Change the "mips_perf_event" table unsupported indicator. MIPS: Align swapper_pg_dir to 64K for better TLB Refill code. vmlinux.lds.h: Allow architectures to add sections to the front of .bss ...
| * Merge tag 'disintegrate-mips-20121009' of ↵Ralf Baechle2012-10-1146-1706/+1846
| |\ | | | | | | | | | | | | | | | | | | | | | git://git.infradead.org/users/dhowells/linux-headers into mips-for-linux-next UAPI Disintegration 2012-10-09 Patchwork: https://patchwork.linux-mips.org/patch/4414/
| | * UAPI: (Scripted) Disintegrate arch/mips/include/asmDavid Howells2012-10-0946-1706/+1846
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Michael Kerrisk <mtk.manpages@gmail.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-10-14 19:30:31 +0200