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* MIPS: vdso: Allow clang's --target flag in VDSO cflagsPaul Burton2018-08-071-0/+5
| | | | | | | | | | | | | | The MIPS VDSO code filters out a subset of known-good flags from KBUILD_CFLAGS to use when building VDSO libraries. When we build using clang we need to allow the --target flag through, otherwise we'll generally attempt to build the VDSO for the architecture of the build machine rather than for MIPS. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20154/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: genvdso: Remove GOT checksPaul Burton2018-08-071-51/+0Star
| | | | | | | | | | | | | | | | | | | | | | | Our genvdso tool performs some rather paranoid checking that the VDSO library isn't attempting to make use of a GOT by constraining the number of entries that the GOT is allowed to contain to the minimum 2 entries that are always generated by binutils. Unfortunately lld prior to revision 334390 generates a third entry, which is unused & thus harmless but falls foul of genvdso's checks & causes the build to fail. Since we already check that the VDSO contains no relocations it seems reasonable to presume that it also doesn't contain use of a GOT, which would involve relocations. Thus rather than attempting to work around this issue by allowing 3 GOT entries when using lld, simply remove the GOT checks which seem overly paranoid. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20152/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: Remove obsolete MIPS checks for DST node "chosen@0"Robert P. J. Day2018-08-061-4/+0Star
| | | | | | | | | | | | | | | | | As there is precious little left in any DTS files referring to the node "/chosen@0" as opposed to "/chosen", remove the two checks for the former node name. [paul.burton@mips.com: The modified yamon-dt code only operates on arch/mips/boot/dts/mti/sead3.dts right now, and that uses chosen rather than chosen@0 anyway, so this should have no behavioural effect.] Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20131/ Cc: linux-mips@linux-mips.org
* MIPS: generic: Remove input symbols from defconfigPaul Burton2018-08-021-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generic_defconfig explicitly disables CONFIG_INPUT_MOUSEDEV, CONFIG_INPUT_KEYBOARD & CONFIG_INPUT_MOUSE which results in warnings when merging board config fragments if any of them require these options. This is the case for the ranchu board, which means we've had the following warning when configuring for generic platform targets since commit f2d0b0d5c171 ("MIPS: ranchu: Add Ranchu as a new generic-based board"): $ make ARCH=mips 32r2el_defconfig Using ./arch/mips/configs/generic_defconfig as base Merging arch/mips/configs/generic/32r2.config Merging arch/mips/configs/generic/el.config Merging ./arch/mips/configs/generic/board-sead-3.config Merging ./arch/mips/configs/generic/board-ranchu.config Value of CONFIG_INPUT_KEYBOARD is redefined by fragment ./arch/mips/configs/generic/board-ranchu.config: Previous value: # CONFIG_INPUT_KEYBOARD is not set New value: CONFIG_INPUT_KEYBOARD=y Merging ./arch/mips/configs/generic/board-ni169445.config Merging ./arch/mips/configs/generic/board-boston.config Merging ./arch/mips/configs/generic/board-ocelot.config Merging ./arch/mips/configs/generic/board-xilfpga.config scripts/kconfig/conf --olddefconfig Kconfig # # configuration written to .config # Resolve this by removing mention of the CONFIG_INPUT_* Kconfig symbols from generic_defconfig, allowing them to take their default values & allowing board config fragments to enable them without warnings. This may be problematic if CONFIG_ARCH_MIGHT_HAVE_PC_SERIO is ever enabled for CONFIG_MIPS_GENERIC=y configurations, but for now that isn't the case so we can worry about that if & when it happens. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20109/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: Delete unused code in linux32.cPaul Burton2018-08-011-19/+0Star
| | | | | | | | | | | | | | | | | The A() & AA() macros have been unused since commit 05e4396651ca ("[MIPS] Use SYSVIPC_COMPAT to fix various problems on N32"), which switched to the more standard compat_ptr(). RLIM_INFINITY32, RESOURCE32() & struct rlimit32 have been present but unused since the beginning of the git era. Remove the dead code. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20108/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: Remove unused sys_32_mmap2Paul Burton2018-08-011-10/+0Star
| | | | | | | | | | | | | | | The sys_32_mmap2 function has been unused since we started using syscall wrappers in commit dbda6ac08976 ("MIPS: CVE-2009-0029: Enable syscall wrappers."), and is indeed identical to the sys_mips_mmap2 function that replaced it in sys32_call_table. Remove the dead code. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20107/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: Remove nabi_no_regargsPaul Burton2018-08-014-37/+35Star
| | | | | | | | | | | | | | | | | | | | Our sigreturn functions make use of a macro named nabi_no_regargs to declare 8 dummy arguments to a function, forcing the compiler to expect a pt_regs structure on the stack rather than in argument registers. This is an ugly hack which unnecessarily causes these sigreturn functions to need to care about the calling convention of the ABI the kernel is built for. Although this is abstracted via nabi_no_regargs, it's still ugly & unnecessary. Remove nabi_no_regargs & the struct pt_regs argument from sigreturn functions, and instead use current_pt_regs() to find the struct pt_regs on the stack, which works cleanly regardless of ABI. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20106/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123Alexandre Belloni2018-07-311-0/+10
| | | | | | | | | | | | | | | | Ocelot PCB123 has a SPI NOR connected on its SPI bus. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20103/ Cc: Mark Brown <broonie@kernel.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-spi@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Allan Nielsen <allan.nielsen@microsemi.com>
* mips: dts: mscc: Add spi on OcelotAlexandre Belloni2018-07-311-0/+11
| | | | | | | | | | | | | | | | Add support for the SPI controller Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20101/ Cc: Mark Brown <broonie@kernel.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-spi@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Allan Nielsen <allan.nielsen@microsemi.com>
* MIPS: Loongson: Merge load addresses谢致邦 (XIE Zhibang)2018-07-311-2/+1Star
| | | | | | | | | | | | | | Systems based upon the Loongson 1B & 1C CPUs share the same load address, as do those based upon Loongson 1A. Unify the definition of this load address to reduce duplication & avoid the need for an extra Loongson 1A case in future. [paul.burton@mips.com: Rewrite commit message.] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/14927/ Cc: linux-mips@linux-mips.org
* MIPS: Loongson: Set Loongson32 to MIPS32R1谢致邦 (XIE Zhibang)2018-07-312-7/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS232 (Loonson 2-issue 32-bit, also called GS232 (Godson 2-issue 32-bit)) is the CPU core (microarchitecture) of Loongson 1A/1B/1C. According to "LS232 用户手册 (LS232 User Manual)", LS232 implements the MIPS32 Release 1 instruction set, and part of the MIPS32 Release 2 instruction set. In the manual, LS232 implements all of the MIPS32R2 instruction set except the FPU instructions, and LS232 also implements 5 FPU instructions of the MIPS32R2 instruction set: CEIL.L.fmt, CVT.L.fmt, FLOOR.L.fmt, TRUNC.L.fmt, and ROUND.L.fmt. But a bug of the DI instruction has been found during tests, the DI instruction can not disable interrupts in arch_local_irq_disable() with CONFIG_PREEMPT_NONE=y and CFLAGS='-mno-branch-likely' in some cases. [paul.burton@mips.com: - Remove the _MIPS_ISA redefinition to match the change made for the generic MIPSr1 CPUs by commit 344ebf09949c ("MIPS: Always use -march=<arch>, not -<arch> shortcuts").] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/16155/ Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org
* MIPS: mscc: ocelot: add interrupt controller properties to GPIO controllerQuentin Schulz2018-07-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | The GPIO controller also serves as an interrupt controller for events on the GPIO it handles. An interrupt occurs whenever a GPIO line has changed. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20015/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
* MIPS: generic: Select MIPS_AUTO_PFN_OFFSETPaul Burton2018-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_MIPS_AUTO_PFN_OFFSET for the generic platform, allowing it to avoid wasted book-keeping for pages with addresses lower than the physical base address of memory. This has a minimal impact on kernel text size, with 64r6el_defconfig gaining 0.1% in size as reported by bloat-o-meter: add/remove: 4/1 grow/shrink: 345/13 up/down: 9017/-392 (8625) Function old new delta pcpu_setup_first_chunk 1444 1780 +336 pcpu_alloc_first_chunk 864 1136 +272 start_kernel 1064 1288 +224 initcall_blacklist 224 372 +148 try_fill_recv 2088 2184 +96 ... Total: Before=8457273, After=8465898, chg +0.10% The gain for systems with large offsets to physical memory & the ability to continue using generic kernels on such systems seems well worth this small cost. Signed-off-by: Paul Burton <paul.burton@mips.com> Suggested-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com> Patchwork: https://patchwork.linux-mips.org/patch/20049/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: Allow auto-dection of ARCH_PFN_OFFSET & PHYS_OFFSETPaul Burton2018-07-304-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On systems where physical memory begins at a non-zero address, defining PHYS_OFFSET (which influences ARCH_PFN_OFFSET) can save us time & memory by avoiding book-keeping for pages from address zero to the start of memory. Some MIPS platforms already make use of this, but with the definition of PHYS_OFFSET being compile-time constant it hasn't been possible to enable this optimization for a kernel which may run on systems with varying physical memory base addresses. Introduce a new Kconfig option CONFIG_MIPS_AUTO_PFN_OFFSET which, when enabled, makes ARCH_PFN_OFFSET a variable & detects it from the boot memory map (which for example may have been populated from DT). The relationship with PHYS_OFFSET is reversed, with PHYS_OFFSET now being based on ARCH_PFN_OFFSET. This is because ARCH_PFN_OFFSET is used far more often, so avoiding the need for runtime calculation gives us a smaller impact on kernel text size (0.1% rather than 0.15% for 64r6el_defconfig). Signed-off-by: Paul Burton <paul.burton@mips.com> Suggested-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com> Patchwork: https://patchwork.linux-mips.org/patch/20048/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: Fix ISA virt/bus conversion for non-zero PHYS_OFFSETPaul Burton2018-07-301-4/+4
| | | | | | | | | | | | | | | | | isa_virt_to_bus() & isa_bus_to_virt() claim to treat ISA bus addresses as being identical to physical addresses, but they fail to do so in the presence of a non-zero PHYS_OFFSET. Correct this by having them use virt_to_phys() & phys_to_virt(), which consolidates the calculations to one place & ensures that ISA bus addresses do indeed match physical addresses. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20047/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
* MIPS: Make (UN)CAC_ADDR() PHYS_OFFSET-agnosticPaul Burton2018-07-305-8/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Converting an address between cached & uncached (typically addresses in (c)kseg0 & (c)kseg1 or 2 xkphys regions) should not depend upon PHYS_OFFSET in any way - we're converting from a virtual address in one unmapped region to a virtual address in another unmapped region. For some reason our CAC_ADDR() & UNCAC_ADDR() macros make use of PAGE_OFFSET, which typically includes PHYS_OFFSET. This means that platforms with a non-zero PHYS_OFFSET typically have to workaround miscalculation by these 2 macros by also defining UNCAC_BASE to a value that isn't really correct. It appears that an attempt has previously been made to address this with commit 3f4579252aa1 ("MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET") which was later undone by commit ed3ce16c3d2b ("Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"") which also introduced the ar7 workaround. That attempt at a fix was roughly equivalent, but essentially caused the CAC_ADDR() & UNCAC_ADDR() macros to cancel out PHYS_OFFSET by adding & then subtracting it again. In his revert Leonid is correct that using PHYS_OFFSET makes no sense in the context of these macros, but appears to have missed its inclusion via PAGE_OFFSET which means PHYS_OFFSET actually had an effect after the revert rather than before it. Here we fix this by modifying CAC_ADDR() & UNCAC_ADDR() to stop using PAGE_OFFSET (& thus PHYS_OFFSET), instead using __pa() & __va() along with UNCAC_BASE. For UNCAC_ADDR(), __pa() will convert a cached address to a physical address which we can simply use as an offset from UNCAC_BASE to obtain an address in the uncached region. For CAC_ADDR() we can undo the effect of UNCAC_ADDR() by subtracting UNCAC_BASE and using __va() on the result. With this change made, remove definitions of UNCAC_BASE from the ar7 & pic32 platforms which appear to have defined them only to workaround this problem. Signed-off-by: Paul Burton <paul.burton@mips.com> References: 3f4579252aa1 ("MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET") References: ed3ce16c3d2b ("Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"") Patchwork: https://patchwork.linux-mips.org/patch/20046/ Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
* MIPS: generic: fix missing of_node_put()Nicholas Mc Guire2018-07-281-0/+1
| | | | | | | | | | | | | | | | of_find_compatible_node() returns a device_node pointer with refcount incremented and must be decremented explicitly. As this code is using the result only to check presence of the interrupt controller (!NULL) but not actually using the result otherwise the refcount can be decremented here immediately again. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19820/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: Octeon: add missing of_node_put()Nicholas Mc Guire2018-07-281-0/+2
| | | | | | | | | | | | | | The call to of_find_node_by_name returns a node pointer with refcount incremented thus it must be explicitly decremented here after the last usage. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19558/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: VDSO: Prevent use of smp_processor_id()Paul Burton2018-07-282-2/+13
| | | | | | | | | | | | | | | | | | VDSO code should not be using smp_processor_id(), since it is executed in user mode. Introduce a VDSO-specific path which will cause a compile-time or link-time error (depending upon support for __compiletime_error) if the VDSO ever incorrectly attempts to use smp_processor_id(). [Matt Redfearn <matt.redfearn@imgtec.com>: Move before change to smp_processor_id in series] Signed-off-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Matt Redfearn <matt.redfearn@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/17932/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org
* MIPS: ath79: Use the IRQ based GPIO key driver for the buttonsAlban Bedel2018-07-285-14/+9Star
| | | | | | | | | | | | | | | | Now that the GPIO driver support interrupts we don't need to poll the buttons. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/15283/ Cc: linux-mips@linux-mips.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org
* MIPS: remove mips_swiotlb_opsChristoph Hellwig2018-07-283-64/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | mips_swiotlb_ops differs from the generic swiotlb_dma_ops only in that it contains a mb() barrier after each operations that maps or syncs dma memory to the device. The dma operations are defined to not be memory barriers, but instead the write* operations to kick the DMA off are supposed to contain them. For mips this handled by war_io_reorder_wmb(), which evaluates to the stronger wmb() instead of the pure compiler barrier barrier() for just those platforms that use swiotlb, so I think we are covered properly. [paul.burton@mips.com: - Include linux/swiotlb.h to fix build failures for configs with CONFIG_SWIOTLB=y.] Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20038/ Cc: David Daney <ddaney@caviumnetworks.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: iommu@lists.linux-foundation.org Cc: linux-kernel@vger.kernel.org
* MIPS: WARN_ON invalid DMA cache maintenance, not BUG_ONPaul Burton2018-07-261-2/+4
| | | | | | | | | | | | If a driver causes DMA cache maintenance with a zero length then we currently BUG and kill the kernel. As this is a scenario that we may well be able to recover from, WARN & return in the condition instead. Signed-off-by: Paul Burton <paul.burton@mips.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/14623/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: ath79: Fix the USB PHY reset namesAlban Bedel2018-07-262-2/+2
| | | | | | | | | | | | | | | | | | | The binding for the USB PHY went thru before the driver. However the new version of the driver now use the PHY core support for reset, and this expect the reset to be named "phy". So remove the "usb-" prefix from the the reset names. Signed-off-by: Alban Bedel <albeu@free.fr> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/15282/ Cc: linux-kernel@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org
* MIPS: mscc: ocelot: add MIIM1 busQuentin Schulz2018-07-261-0/+16
| | | | | | | | | | | | | | | | | | | | | | There is an additional MIIM (MDIO) bus in this SoC so let's declare it in the dtsi. This bus requires GPIO 14 and 15 pins that need to be muxed. There is no support for internal PHY reset on this bus on the contrary of MIIM0 so there is only one register address space and not two. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20014/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
* MIPS: mscc: ocelot: fix length of memory address space for MIIMQuentin Schulz2018-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | The length of memory address space for MIIM0 is from 0x7107009c to 0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in hexadecimal and not 0x36. Fixes: 49b031690abe ("MIPS: mscc: Add switch to ocelot") Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20013/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
* MIPS: TXx9: remove useless RTC definitionsAlexandre Belloni2018-07-261-29/+0Star
| | | | | | | | | | | | | | | | | The RTC definitions were moved to the driver, remove them from the platform header. [paul.burton@mips.com: - Also remove the unused tx4939_rtcptr which would use struct tx4939_rtc_reg if it were ever expanded.] Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20024/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org
* MIPS: ath79: get PCIe controller out of resetMathias Kresin2018-07-251-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ar724x pci driver expects the PCIe controller to be brought out of reset by the bootloader. At least the AVM Fritz 300E bootloader doesn't take care of releasing the different PCIe controller related resets which causes an endless hang as soon as either the PCIE Reset register (0x180f0018) or the PCI Application Control register (0x180f0000) is read from. Do the full "PCIE Root Complex Initialization Sequence" if the PCIe host controller is still in reset during probing. The QCA u-boot sleeps 10ms after the PCIE Application Control bit is set to ready. It has been shown that 10ms might not be enough time if PCIe should be used right after setting the bit. During my tests it took up to 20ms till the link was up. Giving the link up to 100ms should work for all cases. Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19916/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: ath79: enable uart during early_prinkGabor Juhos2018-07-251-1/+43
| | | | | | | | | | | | | | | | | This patch ensures, that the pinmux register is properly setup for the boot console UART when early_printk is enabled. [paul.burton@mips.com: - s/poinmux/pinmux/ - s/uart/UART/ - Drop extraneous parentheses.] Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: ath79: finetune cpu-overridesFelix Fietkau2018-07-251-0/+6
| | | | | | | | | | | | | This patch adds a few additional cpu feature overrides so that they do not need to be probed at runtime. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19914/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: ath79: fix system restartFelix Fietkau2018-07-252-0/+2
| | | | | | | | | | | | | This patch disables irq on reboot to fix hang issues that were observed due to pending interrupts. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19913/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: ath79: select the PINCTRL subsystemJohn Crispin2018-07-251-0/+1
| | | | | | | | | | | | | The pinmux on QCA SoCs is controlled by a single register. The "pinctrl-single" driver can be used but requires the target to select PINCTRL. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19909/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: ath79: add support for QCA953x QCA956x TP9343Matthias Schiffer2018-07-255-3/+269
| | | | | | | | | | | | | | This patch adds support for 2 new types of QCA silicon. TP9343 is essentially the same as the QCA956X but is licensed by TPLink. Signed-off-by: Weijie Gao <hackpascal@gmail.com> Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19911/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: ath79: add lots of missing registersGabor Juhos2018-07-251-1/+770
| | | | | | | | | | | | | | | | | | This patch adds many new registers for various QCA MIPS SoCs. The patch is an aggragate of many contributions made to OpenWrt. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Henryk Heisig <hyniu@o2.pl> Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: Weijie Gao <hackpascal@gmail.com> Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Julien Dusser <julien.dusser@free.fr> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19910/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* mips: mscc: build FIT image for OcelotAlexandre Belloni2018-07-254-3/+35
| | | | | | | | | | | | | Ocelot now has a u-boot port, allow building FIT images instead of relying on the legacy detection and builtin DTB. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: James Hogan <jhogan@kernel.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19632/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: Octeon: Remove extern declarations.Steven J. Hill2018-07-2512-34/+30Star
| | | | | | | | | | Get rid of extern declarations in .c functions and included the necessary header file. Also remove unused UART declares. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19477/ Cc: linux-mips@linux-mips.org
* MIPS: memset.S: Add comments to fault fixup handlersMatt Redfearn2018-07-251-0/+18
| | | | | | | | | | | | | | | It is not immediately obvious what the expected inputs to these fault handlers is and how they calculate the number of unset bytes. Having stared deeply at this in order to fix some corner cases, add some comments to assist those who follow. Signed-off-by: Matt Redfearn <matt.redfearn@mips.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19339/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: <linux-mips@linux-mips.org> Cc: <linux-kernel@vger.kernel.org>
* MIPS: memset.S: Fix byte_fixup for MIPSr6Matt Redfearn2018-07-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __clear_user function is defined to return the number of bytes that could not be cleared. From the underlying memset / bzero implementation this means setting register a2 to that number on return. Currently if a page fault is triggered within the MIPSr6 version of setting of initial unaligned bytes, the value loaded into a2 on return is meaningless. During the MIPSr6 version of the initial unaligned bytes block, register a2 contains the number of bytes to be set beyond the initial unaligned bytes. The t0 register is initally set to the number of unaligned bytes - STORSIZE, effectively a negative version of the number of unaligned bytes. This is then incremented before each byte is saved. The label .Lbyte_fixup\@ is jumped to on page fault. Currently the value in a2 is incorrectly replaced by 0 - t0 + 1, effectively the number of unaligned bytes remaining. This leads to the failures being reported by the following test code: static int __init test_clear_user(void) { int j, k; pr_info("\n\n\nTesting clear_user\n"); for (j = 0; j < 512; j++) { if ((k = clear_user(NULL+3, j)) != j) { pr_err("clear_user (NULL %d) returned %d\n", j, k); } } return 0; } late_initcall(test_clear_user); Which reports: [ 3.965439] Testing clear_user [ 3.973169] clear_user (NULL 8) returned 6 [ 3.976782] clear_user (NULL 9) returned 6 [ 3.980390] clear_user (NULL 10) returned 6 [ 3.984052] clear_user (NULL 11) returned 6 [ 3.987524] clear_user (NULL 12) returned 6 Fix this by subtracting t0 from a2 (rather than $0), effectivey giving: unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1 a2 = a2 - t0 + 1 This fixes the value returned from __clear user when the number of bytes to set is > LONGSIZE and the address is invalid and unaligned. Unfortunately, this breaks the fixup handling for unaligned bytes after the final long, where register a2 still contains the number of bytes remaining to be set and the t0 register is to 0 - the number of unaligned bytes remaining. Because t0 is now is now subtracted from a2 rather than 0, the number of bytes unset is reported incorrectly: static int __init test_clear_user(void) { char *test; int j, k; pr_info("\n\n\nTesting clear_user\n"); test = vmalloc(PAGE_SIZE); for (j = 256; j < 512; j++) { if ((k = clear_user(test + PAGE_SIZE - 254, j)) != j - 254) { pr_err("clear_user (%px %d) returned %d\n", test + PAGE_SIZE - 254, j, k); } } return 0; } late_initcall(test_clear_user); [ 3.976775] clear_user (c00000000000df02 256) returned 4 [ 3.981957] clear_user (c00000000000df02 257) returned 6 [ 3.986425] clear_user (c00000000000df02 258) returned 8 [ 3.990850] clear_user (c00000000000df02 259) returned 10 [ 3.995332] clear_user (c00000000000df02 260) returned 12 [ 3.999815] clear_user (c00000000000df02 261) returned 14 Fix this by ensuring that a2 is set to 0 during the set of final unaligned bytes. Signed-off-by: Matt Redfearn <matt.redfearn@mips.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support") Patchwork: https://patchwork.linux-mips.org/patch/19338/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v4.0+
* MIPS: Hardcode cpu_has_* where known at compile time due to ISAPaul Burton2018-07-241-69/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many architectural features have over time moved from being optional to either be required or removed by newer architecture releases. This means that in many cases we can know at compile time whether a feature will be supported or not purely due to the knowledge we have about the ISA the kernel build is targeting. This patch introduces a bunch of utility macros for checking for supported options, ASEs & combinations of those with ISA revisions. It then makes use of these in the default definitions of cpu_has_* macros. The result is that many of the macros become compile-time constant, allowing more optimisation opportunities for the compiler - particularly with kernels built for later ISA revisions. To demonstrate the effect of this patch, the following table shows the size in bytes of the kernel binary as reported by scripts/bloat-o-meter for v4.12-rc4 maltasmvp_defconfig kernels with & without this patch. A variant of maltasmvp_defconfig with CONFIG_CPU_MIPS32_R6 selected is also shown, to demonstrate that MIPSr6 systems benefit more due to extra features becoming required by that architecture revision. Builds of pistachio_defconfig are also shown, as although this is a MIPSr2 platform it doesn't hardcode any features in a machine-specific cpu-feature-overrides.h, which allows it to gain more from this patch than the equivalent Malta r2 build. Config | Before | After | Change ----------------|---------|---------|--------- maltasmvp | 7248316 | 7247714 | -602 maltasmvp + r6 | 6955595 | 6950777 | -4818 pistachio | 8650977 | 8363898 | -287079 Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/16360/ Cc: Joshua Kinard <kumba@gentoo.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
* MIPS: jz4780: DTS: Probe the spi-gpio driver from devicetreeMathieu Malaterre2018-07-241-0/+19
| | | | | | | | | | | | | | | | | | | | Make use of the spi-gpio driver to provide SPI support on the Ingenic JZ4780 SoC using the pins that can be used with the SSI0 device as GPIOs, until such time as we have support for the Ingenic SPI/SSI controller. [paul.burton@mips.com: Rewrite commit message.] Signed-off-by: Mathieu Malaterre <malat@debian.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19489/ Cc: James Hogan <jhogan@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: Ci20: Enable SPI/GPIO driverMathieu Malaterre2018-07-241-0/+2
| | | | | | | | | | | | | | | | | | Enable CONFIG_SPI_GPIO in ci20_defconfig, in order to make use of the spi-gpio driver in a further commit. [paul.burton@mips.com: Rewrite commit message.] Signed-off-by: Mathieu Malaterre <malat@debian.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19488/ Cc: James Hogan <jhogan@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: Octeon: Select HAS_RAPIDIOAlexander Sverdlin2018-07-241-0/+1
| | | | | | | | | | | | | | All Octeons starting with Octeon II have RAPIDIO controller which can function even with PCI disabled. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Acked-by: Alexandre Bounine <alex.bou9@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19988/ Cc: linux-mips@linux-mips.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Matt Porter <mporter@kernel.crashing.org>
* MIPS: Introduce HAS_RAPIDIO Kconfig optionAlexander Sverdlin2018-07-241-2/+5
| | | | | | | | | | | | | | Introduce the same option as PPC and ARM already have because RAPIDIO can function in the absence of PCI. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Acked-by: Alexandre Bounine <alex.bou9@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19987/ Cc: linux-mips@linux-mips.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Matt Porter <mporter@kernel.crashing.org>
* mips: use asm-generic version of msi.hThomas Petazzoni2018-07-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is necessary to be able to include <linux/msi.h> when CONFIG_GENERIC_MSI_IRQ_DOMAIN is enabled. Without this, a build with CONFIG_GENERIC_MSI_IRQ_DOMAIN fails with: In file included from include/linux/kvm_host.h:20:0, from arch/mips/kernel/asm-offsets.c:24: >> include/linux/msi.h:197:10: fatal error: asm/msi.h: No such file or directory #include <asm/msi.h> ^~~~~~~~~~~ compilation terminated. make[2]: *** [arch/mips/kernel/asm-offsets.s] Error 1 make[2]: Target '__build' not remade because of errors. make[1]: *** [prepare0] Error 2 make[1]: Target 'prepare' not remade because of errors. make: *** [sub-make] Error 2 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19986/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Hanna Hawa <hannah@marvell.com>
* MIPS: Loongson64: Define and use some CP0 registersHuacai Chen2018-07-242-12/+14
| | | | | | | | | | | | | | | Defines CP0_CONFIG3, CP0_CONFIG6, CP0_PAGEGRAIN and use them in kernel-entry-init.h for Loongson64. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19264/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <james.hogan@mips.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
* MIPS: Loongson: Add Loongson-3A R3.1 basic supportHuacai Chen2018-07-244-28/+32
| | | | | | | | | | | | | | | | | | | | | | | | Loongson-3A R3.1 is the bugfix revision of Loongson-3A R3. All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19263/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <james.hogan@mips.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
* MIPS: jz4740: Bump zload addressPaul Cercueil2018-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Having the zload address at 0x8060.0000 means the size of the uncompressed kernel cannot be bigger than around 6 MiB, as it is deflated at address 0x8001.0000. This limit is too small; a kernel with some built-in drivers and things like debugfs enabled will already be over 6 MiB in size, and so will fail to extract properly. To fix this, we bump the zload address from 0x8060.0000 to 0x8100.0000. This is fine, as all the boards featuring Ingenic JZ SoCs have at least 32 MiB of RAM, and use u-boot or compatible bootloaders which won't hardcode the load address but read it from the uImage's header. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19787/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: lantiq: Use dma_zalloc_coherent() in dma codeHauke Mehrtens2018-07-231-2/+1Star
| | | | | | | | | | | | | | Instead of using dma_alloc_coherent() and memset() directly use dma_zalloc_coherent(). Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19962/ Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: john@phrozen.org Cc: linux-mips@linux-mips.org Cc: dev@kresin.me
* MIPS: Change definition of cpu_relax() for Loongson-3Huacai Chen2018-07-231-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux expects that if a CPU modifies a memory location, then that modification will eventually become visible to other CPUs in the system. Loongson 3 CPUs include a Store Fill Buffer (SFB) which sits between a core & its L1 data cache, queueing memory accesses & allowing for faster forwarding of data from pending stores to younger loads from the core. Unfortunately the SFB prioritizes loads such that a continuous stream of loads may cause a pending write to be buffered indefinitely. This is problematic if we end up with 2 CPUs which each perform a store that the other polls for - one or both CPUs may end up with their stores buffered in the SFB, never reaching cache due to the continuous reads from the poll loop. Such a deadlock condition has been observed whilst running qspinlock code. This patch changes the definition of cpu_relax() to smp_mb() for Loongson-3, forcing a flush of the SFB on SMP systems which will cause any pending writes to make it as far as the L1 caches where they will become visible to other CPUs. If the kernel is not compiled for SMP support, this will expand to a barrier() as before. This workaround matches that currently implemented for ARM when CONFIG_ARM_ERRATA_754327=y, which was introduced by commit 534be1d5a2da ("ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore"). Although the workaround is only required when the Loongson 3 SFB functionality is enabled, and we only began explicitly enabling that functionality in v4.7 with commit 1e820da3c9af ("MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT"), existing or future firmware may enable the SFB which means we may need the workaround backported to earlier kernels too. [paul.burton@mips.com: - Reword commit message & comment. - Limit stable backport to v3.15+ where we support Loongson 3 CPUs.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> References: 534be1d5a2da ("ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore") References: 1e820da3c9af ("MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT") Patchwork: https://patchwork.linux-mips.org/patch/19830/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com> Cc: stable@vger.kernel.org # v3.15+
* mips: mm: Discard ioremap_cacheable_cow() methodSerge Semin2018-07-211-7/+0Star
| | | | | | | | | | | | | | | | | | | This macro substitution is the shortcut to map cacheable IO memory with coherent and write-back attributes. Since it is entirely unused by kernel, lets just remove it. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Suggested-by: Christoph Hellwig <hch@infradead.org> Patchwork: https://patchwork.linux-mips.org/patch/19937/ CC: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Sinan Kaya <okaya@codeaurora.org> Cc: Huacai Chen <chenhc@lemote.com> Cc: Sergey.Semin@t-platforms.ru Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: Add FP_MODE regset supportMaciej W. Rozycki2018-07-191-0/+63
| | | | | | | | | | | | | | | | | | | | Define an NT_MIPS_FP_MODE core file note and implement a corresponding regset holding the state handled by PR_SET_FP_MODE and PR_GET_FP_MODE prctl(2) requests. This lets debug software correctly interpret the contents of floating-point general registers both in live debugging and in core files, and also switch floating-point modes of a live process. [paul.burton@mips.com: - Changed NT_MIPS_FP_MODE to 0x801 to match first nibble of NT_MIPS_DSP, which was also changed to avoid a conflict.] Signed-off-by: Maciej W. Rozycki <macro@mips.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19331/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-23 19:06:52 +0200