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* [POWREPC] Fixup a number of modpost warnings on ppc32Kumar Gala2007-07-261-1/+1
| | | | | | | | | | | | | | Fixed the following warnings: WARNING: vmlinux.o(.text+0x2934): Section mismatch: reference to .init.text:__alloc_bootmem (between 'irq_alloc_host' and 'irq_set_default_host') WARNING: vmlinux.o(.text+0xb2aa): Section mismatch: reference to .init.data:boot_command_line (between 'register_early_udbg_console' and 'udbg_printf') WARNING: vmlinux.o(.text+0xb2b2): Section mismatch: reference to .init.data:boot_command_line (between 'register_early_udbg_console' and 'udbg_printf') WARNING: vmlinux.o(.text+0xe354): Section mismatch: reference to .init.text:__alloc_bootmem (between 'pcibios_alloc_controller' and 'pci_domain_nr') WARNING: vmlinux.o(.text+0x12768): Section mismatch: reference to .init.text:update_bridge_resource (between 'quirk_fsl_pcie_transparent' and 'indirect_read_config') WARNING: vmlinux.o(.text+0x127a8): Section mismatch: reference to .init.text:update_bridge_resource (between 'quirk_fsl_pcie_transparent' and 'indirect_read_config') WARNING: vmlinux.o(.text+0x17566c): Section mismatch: reference to .init.text:pcibios_fixup_bus (between 'pci_scan_child_bus' and 'pci_scan_bus_parented') Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Fix PCI indirect for big-endian cfg_addrKumar Gala2007-07-252-1/+2
| | | | | | | | | | | We didn't actually propogate the flag we pass into setup_indirect_pci() to set indirect_type and thus were getting the wrong endianness if PPC_INDIRECT_TYPE_BIG_ENDIAN was set. Also, we need to or in additional flags rather than just doing a direct assignment. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 85xx: Added needed MPC85xx PCI device IDsKumar Gala2007-07-241-13/+13
| | | | | | | | Added the MPC85xx PCI device IDs that we need for the quirks we have. Also, fixed the MPC8567E, MPC8567 device IDs which had the wrong value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDsJon Loeliger2007-07-241-2/+2
| | | | | | | | | | | Also add 8641/8641D device IDs as well. All of which already exist or have been submitted to The Linux PCI ID Repository at: http://pci-ids.ucw.cz/ CC-to: pci-ids@ucw.cz Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] FSL: Add support for PCI-X controllersKumar Gala2007-07-241-1/+12
| | | | | | | | | | Some set of 85xx platforms have PCI-X controllers. The old arch/ppc code setup these controllers and we haven't moved it over to arch/powerpc. We use the PCI-X Capabilties to know if we are in PCI-X mode instead of the Global Utilities PORDEVSR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHBKumar Gala2007-07-241-0/+14
| | | | | | | | For the Freescale PCIe PHBs Not all firmwares setup the virtual P2P bridge registers properly. Make sure they get setup based on what the struct pci_controller got from the device tree. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add basic PCI/PCI Express support for 8544DS boardRoy Zang2007-07-241-0/+2
| | | | | | | | Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Make endianess of cfg_addr for indirect pci ops runtimeKumar Gala2007-07-244-16/+17
| | | | | | | | Make it so we do a runtime check to know if we need to write cfg_addr as big or little endian. This is needed if we want to allow 86xx support to co-exist in the same kernel as other 6xx PPCs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Removed setup_indirect_pci_nomapKumar Gala2007-07-231-13/+4Star
| | | | | | | We don't use setup_indirect_pci_nomap in arch/powerpc and it appears the users that needed it from arch/ppc are now using setup_indirect_pci. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 85xx: Added 8568 PCIe supportKumar Gala2007-07-231-0/+4
| | | | | | Added the PCIe device node to the 8568 dts and the needed quirk entries. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connectedKumar Gala2007-07-232-0/+15
| | | | | | | | | On the 85xx/86xx PCIe controllers if there is no device connected to the PHB we will still allocate a pci_bus for downstream bus of the virtual P2P bridge. However the resources allocated to the downstream bus are not correct and so we just mimic the resources from the upstream pci_bus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Use Freescale pci/pcie common code for 85xx boardsRoy Zang2007-07-231-0/+7
| | | | | | | | Switch the 85xx platform over to using the FSL generic PCI code. This gets ups PCIe support in addition to base PCI support. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] FSL: Cleanup how we detect if we are a PCIe controllerKumar Gala2007-07-231-9/+9
| | | | | | | | | Use the PCI capabilities to determine if we are PCIe PHB. Also use PPC_INDIRECT_TYPE_NO_PCIE_LINK since the Freescale PCIe controllers will lock the system if they don't have link and you try to do a config access to anything but the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no linkKumar Gala2007-07-231-1/+15
| | | | | | | | | Added PPC_INDIRECT_TYPE_NO_PCIE_LINK flag to the indirect pci handling code to ensure that we don't talk to any device other than the PHB if we don't have PCIe link. Some controllers will lockup if they try to do a config cycle to any device on the bus except the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3,5,6}xxZang Roy-r619112007-07-232-215/+174Star
| | | | | | | | Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and PCIe on 85xx/86xx. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Create common fsl pci/e files based on 86xx platformsRoy Zang2007-07-233-0/+239
| | | | | | | | | | | | | Move arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h as the base to unify 83xx/85xx/86xx pci and pcie. Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option. The code still works for 86xx platforms. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] MPIC protected sourcesBenjamin Herrenschmidt2007-07-221-0/+32
| | | | | | | | | | | | | | | | | | Some HW platforms, such as the new cell blades, requires some MPIC sources to be left alone by the operating system. This implements support for a "protected-sources" property in the mpic controller node containing a list of source numbers to be protected against operating system interference. For those interested in the gory details, the MPIC on the southbridge of those blades has some of the processor outputs routed to the cell, and at least one routed as a GPIO to the service processor. It will be used in the GA product for routing some of the southbridge error interrupts to the service processor which implements some of the RAS stuff, such as checkstopping when fatal errors occurs before they can propagate. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [CELL] driver for DDR2 memory on AXONMaxim Shchetynin2007-07-202-0/+382
| | | | | | | | | | | | | | | | | | The Axon bridge chip used on new Cell/B.E. based blade servers comes with a DDR2 memory controller that can be used to attach cheap memory modules, as opposed to the high-speed XDR memory that is used by the CPU itself. Since the memory controller does not participate in the cache coherency protocol, we can not use the memory direcly for Linux applications, but by providing a block device it can be used for swap space, temporary file storage and through the use of the direct_access block device operation for mapping into user addresses, when it is mounted with an appropriate file system. Signed-off-by: Maxim Shchetynin <maxim@de.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [CELL] pmi: remove support for mutiple devices.Christian Krafft2007-07-201-29/+22Star
| | | | | | | | | | | | | | | | | The pmi driver got simplified by removing support for multiple devices. As there is no more than one pmi device per maschine, there is no need to specify the device for listening and sending messages. This way the caller (cbe_cpufreq) doesn't need to scan the device tree. When registering the handler on a board without a pmi interface, pmi.c will just return -ENODEV. The patch that fixed the breakage of cell_defconfig has been broken out of the earlier version of this patch. So this is the version that applies cleanly on top of it. Signed-off-by: Christian Krafft <krafft@de.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* Fix RGMII-ID handling in gianfarAndy Fleming2007-07-191-0/+9
| | | | | | | | | | | The TSEC/eTSEC can detect the interface to the PHY automatically, but it isn't able to detect whether the RGMII connection needs internal delay. So we need to detect that change in the device tree, propagate it to the platform data, and then check it if we're in RGMII. This fixes a bug on the 8641D HPCN board where the Vitesse PHY doesn't use the delay for RGMII. Signed-off-by: Andy Fleming <afleming@freescale.com>
* [POWERPC] Create add_rtc() function to enable the RTC CMOS driverWade Farnsworth2007-07-112-0/+50
| | | | | | | | | | | | In order to use the RTC CMOS driver, each architecture must register a platform device for the RTC. This creates a function to register the platform device based on the RTC device node and verifies that the RTC port against the hard-coded value in asm/mc146818rtc.h. Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] 8xx: mpc885ads pcmcia supportVitaly Bordug2007-07-102-2/+22
| | | | | | | | | | | | | | | | | | | | Adds support for PowerQuicc on-chip PCMCIA. The driver is implemented as of_device, so only arch/powerpc stuff is capable to use it, which now implies only mpc885ads reference board. To cope with the code that should be hooked inside driver, but is really board specific (like set_voltage), global structure mpc8xx_pcmcia_ops holds necessary function pointers that are filled in the BSP code. [akpm@linux-foundation.org: whitespace diddles] Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] qe_lib: export symbols for QE driver to compile as moduleLi Yang2007-07-032-0/+10
| | | | | | | | Export symbols of qe_lib to be used by QE driver. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Selvamuthukumar V <vsmkumar.84@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Merge ppc32 and ppc64 pcibios_alloc_controller() prototypesKumar Gala2007-06-292-5/+2Star
| | | | | | | Make the ppc32 pcibios_alloc_controller take a device node to match the ppc64 prototypes and have it set arch_data. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 86xx: Workaround PCI_PRIMARY_BUS usageKumar Gala2007-06-291-0/+6
| | | | | | | | | | | | | | | The Freescale PCI-e controllers have an issue in that they use the PCI_PRIMARY_BUS register in the virtual P2P bridge to determine which bus number to match on when generating a type 0 config cycle. The issue is if we are renumbering bus numbers to match Linux we will try setting the PCI_PRIMARY_BUS and will not know which bus number to use for generating type 0 config cycles. We surpress writing the register in the P2P bridge and always keep it at zero. In the future when proper PCI domain support is working we should be able to remove this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Added indirect_type to handle variants of PCI opsKumar Gala2007-06-291-6/+16
| | | | | | | | | | | | The generic PCI config ops indirect support for ppc32 covers only two cases (implicit vs explicit) type 0/1 config cycles via set_cfg_type. Added a indirect_type bit mask to handle other variants. Added support for PCI-e extended registers and moved the cfg_type handling into the bit mask for ARCH=powerpc. We can also use this to handle indirect quirks. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Remove PCI-e errata for MPC8641 silicon ver 1.0Zhang Wei2007-06-292-172/+0Star
| | | | | | | | | Remove errata for PCI-e support of Rev 1.0 of MPC8641 since its considered obselete and is not production level silicon from Freescale. Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Removed remnants of bus_offsetKumar Gala2007-06-292-3/+3
| | | | | | | | | | | Removed the remants of bus_offset and use self_busno in the mv64x60 case and use pci_assign_all_buses on 83xx/85xx. 83xx/85xx have multiple PHBs and the firmwares on these devices tend not to handle topologies with P2P bridges well so we let Linux just reassign the bus numbers to match. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Added self_busno to indicate which bus number the PHB isKumar Gala2007-06-291-2/+10
| | | | | | | | | Added self_busno to pci_controller and indirect PCI ops to be set by board code to indicate which bus number to use when talking to the PHB. By default we use zero since the majority of controllers that have implicit mechanisms to talk to the PHBs use a bus number of zero. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Remove bus_offset in places its not really usedKumar Gala2007-06-291-4/+4
| | | | | | | | The user of the fsl_pcie code doesn't set bus_offset and 82xx doesn't require it either. Remove the places in the code that reference it so we can remove it all together. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Pass the pci_controller into pci_exclude_deviceKumar Gala2007-06-294-9/+11
| | | | | | | | | | There are times that we need to know which controller we are on to decide how to exclude devices properly. We now pass the pci_controller that we are going to use down to the pci_exclude_device function. This will greatly simplify being able to exclude the PHBs in multiple controller setups. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Remove set_cfg_type for PCI indirect users that don't need itKumar Gala2007-06-292-2/+0Star
| | | | | | | | | | | The Freescale and Marvell PCI controllers dont require explicit setting for type 1 config cycles. They handle producing them by implicitly looking at the bus, devfn. The TSI108 and 52xx don't use the generic PCI indirect code and thus don't bother with set_cfg_type. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Call add_preferred_console when MPSC is consoleMark A. Greer2007-06-251-0/+28
| | | | | | | | | | When a Marvell MPSC (serial controller) port is the specified /chosen/stdout-path device, call 'add_preferred_console()' so the user doesn't have to specify a 'console=ttyMMx' cmdline argument. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Acked-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Don't link timer.o for powerpc systems using generic rtcGuennadi Liakhovetski2007-06-251-0/+2
| | | | | | | | | | | | | | | | | With both generic rtc and powerpc timer suspend / resume code now in the (powerpc.git) tree, powerpc platforms using the generic timer and enabling power management will have timer.o linked in the kernel, which they don't need. Moreover, it will likely WARN_ON(!ppc_md.get_rtc_time), save zero-time and return no error on suspend... As a possible solution we can choose not to build timer.o when RTC_CLASS is enabled. However, I can imagine systems with 2 rtc's, one served by the ppc-rtc, another one generic built as a module, in which case using the ppc-rtc for suspend / resume will be impossible. Not to say, that such a configuration would be ugly... Signed-off-by: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Use mktime in timer sysdevJohannes Berg2007-06-251-2/+12
| | | | | | | | | This makes the timer sysdev use mktime instead of rtc_tm_to_time, since rtc_tm_to_time just calls mktime anyway, and this means we don't have a dependency on rtc-lib. Signed-off-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Fix problems with device tree representation of TSI-1xx bridgesDavid Gibson2007-06-141-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes some problems with the way the some things represented in the device tree for the Holly and Taiga boards. This means changes both to the dts files, and to the code which instantiates the tsi108 ethernet platform devices based on the device tree. - First, and most importantly, the ethernet PHYs are given with an identical 'reg' property. This reg currently encodes the accessible register used to initiate mdio interaction with the PHYs, rather than a meaningful address on the parent bus (mdio in this case), which is incorrect. Instead we give the address of these registers as 'reg' in the mdio node itself, and encode the ID of each phy in their 'reg' propertyies. - Currently the platform device constructor enables a workaround in the tsi108 ethernet driver based on the compatible property of the PHY. This is incorrect, because the workaround in question is necessary due to the board's wiring of the PHY, not the model of PHY itself. This patch alters the constructor to instead enable the workaround based on a new special property in the PHY node. - The compatible properties on a number of nodes in the device tree are insufficiently precise. In particular the PHYs give only "bcm54xx", which is broken, since there are many bcm54xx PHY models, and they have differences which matter. The mdio had a compatible property of "tsi-ethernet" identical to the ethernet MAC nodes, which doesn't make sense. The ethernet, i2c, bridge and PCI nodes were given only as "tsi-*" which is somewhat inprecise, we replace with "tsi108-*" in the case of Taiga (which has a TSI108 bridge), and "tsi109-*", "tsi108-*" in the case of Holly (which has a TSI109 bridge). - We remove some "model" properties from the ethernets on Taiga board which were neither useful nor adequately precise. - On Holly we change to using a dtc label instead of a full path to reference the MPIC node, which makes the dts a little more readable. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] QE: fix Kconfig 'select' warning with UCC_FASTTimur Tabi2007-05-231-3/+1Star
| | | | | | | | | | | The UCC_GETH Kconfig option in drivers/net/Kconfig had a line to select the UCC_FAST option is arch/powerpc/sysdev/qe_lib/Kconfig, which is only used on PowerPC builds. On other architectures, this would generated a warning. The fix is to have UCC_FAST depend on UCC_GETH. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Remove warning in mpic.cOlof Johansson2007-05-171-3/+9
| | | | | | | | arch/powerpc/sysdev/mpic.c: In function 'mpic_request_ipis': arch/powerpc/sysdev/mpic.c:1445: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Add Marvell mv64x60 PCI bridge supportDale Farnsworth2007-05-123-1/+176
| | | | | | | | | | | This patch adds PCI bridge support for the Marvell mv64x60 chip. We also provide the ability to read/write the mv64x60 hotswap register via sysfs if the hs_reg_valid property is set in the device tree. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Create Marvell mv64x60 I2C platform_dataDale Farnsworth2007-05-121-0/+72
| | | | | | | | | | | | | | This patch creates platform_device entries for the Marvell mv64x60 I2C ports, based on information contained in device tree. This driver (like the other mv64x60 drivers) are unusual in that it works on both the MIPS and PowerPC architectures. Because of that, the drivers do not support the normal PowerPC of_platform_bus_type. They support platform_bus_type instead. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Create Marvell mv64x60 ethernet platform_dataDale Farnsworth2007-05-121-0/+129
| | | | | | | | | | | | | | | This patch creates platform_device entries for the Marvell mv64x60 ethernet controller ports, based on information contained in the device tree. This driver (like the other mv64x60 drivers) are unusual in that it works on both the MIPS and PowerPC architectures. Because of that, the drivers do not support the normal PowerPC of_platform_bus_type. They support platform_bus_type instead. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Create Marvell mv64x60 MPSC (serial) platform_dataDale Farnsworth2007-05-122-1/+222
| | | | | | | | | | | | | | | This patch creates platform_device entries for the Marvell mv64x60 MPSC (multi-protocol serial controller) ports, based on information contained in the device tree. This driver (like the other mv64x60 drivers) are unusual in that it works on both the MIPS and PowerPC architectures. Because of that, the drivers do not support the normal PowerPC of_platform_bus_type. They support platform_bus_type instead. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Add interrupt support for Marvell mv64x60 chipsDale Farnsworth2007-05-123-0/+315
| | | | | | | | | | | There are 3 interrupt groups each with its own status/mask registers. We use a separate struct irq_chip for each interrupt group and handle interrupts in two stages or levels: level 1 selects the appropriate struct irq_chip, and level 2 selects individual interrupts within that irq_chip. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Change rheap functions to use ulongs instead of pointersTimur Tabi2007-05-105-41/+41
| | | | | | | | | | | | | | | | | | | | The rheap allocation functions return a pointer, but the actual value is based on how the heap was initialized, and so it can be anything, e.g. an offset into a buffer. A ulong is a better representation of the value returned by the allocation functions. This patch changes all of the relevant rheap functions to use a unsigned long integers instead of a pointer. In case of an error, the value returned is a negative error code that has been cast to an unsigned long. The caller can use the IS_ERR_VALUE() macro to check for this. All code which calls the rheap functions is updated accordingly. Macros IS_MURAM_ERR() and IS_DPERR(), have been deleted in favor of IS_ERR_VALUE(). Also added error checking to rh_attach_region(). Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] fsl_soc: Make mac_addr const in fs_enet_of_init().Scott Wood2007-05-091-1/+1
| | | | | | | | of_get_mac_address() returns a const pointer, so the result should be stored in a const pointer. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Abolish powerpc_flash_init()David Gibson2007-05-082-33/+0Star
| | | | | | | | | | | | | | powerpc_flash_init() implements a broken way of probing for flash devices supported by the physmap_of driver. It finds all nodes in the device tree with device_type=="rom" and instantiates of_platform devices for them. This is fundamentally incompatible with the normal and correct way of probing for of_platform_bus_probe(). Platforms which relied on powerpc_flash_init()s behaviour (none are in-tree) will have to update their platform probing code to correctly probe busses containing flash devices. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] MPIC U3/U4 MSI backendMichael Ellerman2007-05-084-6/+205
| | | | | | | | | | | | | | | | MPIC U3/U4 MSI backend. Based on code from Segher, heavily hacked by me. This only deals with MSI on U3/U4 MPICs, aka. CPC 9x5. If we find a U3/U4 then we enable this backend, ie. take over the ppc_md MSI hooks. We might need more elaborate logic in future to decide which backend is enabled. We need our own irq_chip so that we can do MSI masking/unmasking on the device itself. We also need to mask explicitly on shutdown to make sure we don't get bitten by lazy-disable semantics. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] MPIC MSI allocatorMichael Ellerman2007-05-084-1/+217
| | | | | | | | | | | To support MSI on MPIC we need a way to reserve and allocate hardware irq numbers, this patch implements an allocator for that purpose. New firmware platforms must define a "msi-available-ranges" property on their MPIC node for MSI to work. For U3/U4 we do a best-guess setup. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Enable MSI mappings for MPICMichael Ellerman2007-05-081-0/+45
| | | | | | | | | | On some Apple machines the HT MSI mappings are not enabled by firmware, so we need to do it by hand. We can't use the pci routines as this code runs too early. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Generalize tsi108 PCI setupJosh Boyer2007-05-081-5/+6
| | | | | | | | | Generalize tsi108_setup_pci to take the config space physical address and primary bus designator as a parameter. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-12 09:57:32 +0200