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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-02-021-1/+0Star
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| * arch: Remove clkdev.h asm-generic from KbuildStephen Boyd2018-01-031-1/+0Star
* | Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2018-02-012-2/+1Star
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| * | riscv: use linux/uaccess.h, not asm/uaccess.h...Al Viro2017-12-052-2/+1Star
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* | Merge tag 'dma-mapping-4.16' of git://git.infradead.org/users/hch/dma-mappingLinus Torvalds2018-01-313-39/+2Star
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| * | dma-direct: rename dma_noop to dma_directChristoph Hellwig2018-01-151-1/+1
| * | dma-mapping: provide a generic asm/dma-mapping.hChristoph Hellwig2018-01-152-30/+1Star
| * | riscv: remove the unused dma_capable helperChristoph Hellwig2018-01-091-8/+0Star
* | | Merge tag 'init_task-20180117' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2018-01-291-2/+0Star
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| * | | Construct init thread stack in the linker script rather than by unionDavid Howells2018-01-101-2/+0Star
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* | | riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-086-17/+17
* | | riscv: remove CONFIG_MMU ifdefsChristoph Hellwig2018-01-084-24/+0Star
* | | RISC-V: Make __NR_riscv_flush_icache visible to userspacePalmer Dabbelt2018-01-085-30/+27Star
* | | RISC-V: Add a basic defconfigKarsten Merker2018-01-081-0/+75
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* | RISC-V: Remove unused CONFIG_HVC_RISCV_SBI codePalmer Dabbelt2017-12-111-11/+0Star
* | RISC-V: Resurrect smp_mb__after_spinlock()Palmer Dabbelt2017-12-111-0/+19
* | RISC-V: Logical vs Bitwise typoDan Carpenter2017-12-111-1/+1
* | bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program typeHendrik Brueckner2017-12-051-0/+1
* | RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt2017-12-0112-21/+39
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| * | RISC-V: Add missing includeOlof Johansson2017-11-301-0/+1
| * | RISC-V: Use define for get_cycles like other architecturesOlof Johansson2017-11-301-1/+2
| * | RISC-V: Provide stub of setup_profiling_timer()Olof Johansson2017-11-301-0/+7
| * | RISC-V: Export some expected symbols for modulesOlof Johansson2017-11-303-0/+6
| * | RISC-V: move empty_zero_page definition to C and export itOlof Johansson2017-11-302-3/+3
| * | RISC-V: io.h: type fixes for warningsOlof Johansson2017-11-302-8/+10
| * | RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macrosOlof Johansson2017-11-302-9/+9
| * | RISC-V: use generic serial.hOlof Johansson2017-11-301-0/+1
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* | RISC-V: __io_writes should respect the length argumentPalmer Dabbelt2017-12-011-1/+1
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| * | RISC-V: __io_writes should respect the length argumentPalmer Dabbelt2017-12-011-1/+1
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* | RISC-V: User-Visible ChangesPalmer Dabbelt2017-12-0119-34/+392
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| * | RISC-V: Clean up an unused includePalmer Dabbelt2017-11-301-1/+0Star
| * | RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman2017-11-308-0/+105
| * | RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-308-30/+174
| * | RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpuAndrew Waterman2017-11-276-1/+113
| * | RISC-V: Remove __vdso_cmpxchg{32,64} symbol versionsPalmer Dabbelt2017-11-271-2/+0Star
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* | RISC-V: remove spin_unlock_wait()Palmer Dabbelt2017-11-281-9/+0Star
* | RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt2017-11-281-1/+4
* | RISC-V: Add READ_ONCE in arch_spin_is_locked()Palmer Dabbelt2017-11-281-1/+1
* | RISC-V: __test_and_op_bit_ord should be strongly orderedPalmer Dabbelt2017-11-281-1/+1
* | RISC-V: Remove smb_mb__{before,after}_spinlock()Palmer Dabbelt2017-11-281-8/+0Star
* | RISC-V: Remove __smp_bp__{before,after}_atomicPalmer Dabbelt2017-11-281-15/+0Star
* | RISC-V: Comment on why {,cmp}xchg is ordered how it isPalmer Dabbelt2017-11-281-2/+7
* | RISC-V: Remove unused arguments from ATOMIC_OPPalmer Dabbelt2017-11-281-47/+47
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* Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...Linus Torvalds2017-11-151-14/+0Star
* RISC-V: Build InfrastructurePalmer Dabbelt2017-09-279-0/+579
* RISC-V: User-facing APIPalmer Dabbelt2017-09-2727-0/+1687
* RISC-V: Paging and MMUPalmer Dabbelt2017-09-278-0/+1192
* RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt2017-09-279-0/+566
* RISC-V: Task implementationPalmer Dabbelt2017-09-279-0/+1243
* RISC-V: ELF and module implementationPalmer Dabbelt2017-09-274-0/+187
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