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* [PATCH] ARM: 2655/1: ARM1136 SWP instruction abort handler fixGeorge G. Davis2005-04-291-0/+16
| | | | | | | | | Patch from George G. Davis As noted in http://www.arm.com/linux/patch-2.6.9-arm1.gz, the "Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR." So the v6_early_abort handler does not report the correct rd/wr direction for the SWP instruction which may result in SEGVS or hangs. In order to work around this problem, this patch merely updates the fix contained in the ARM Ltd. patch to use the macroised abort handler fixups. Signed-off-by: George G. Davis Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2659/1: do not assign PCI I/O address zero on IXP2000Lennert Buytenhek2005-04-291-2/+2
| | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek Assigning the address zero to a PCI device BAR causes some part of the PCI subsystem to believe that resource allocation for that BAR failed due to resource conflicts, which will make attempts to enable the device fail. Work around this by assigning I/O addresses starting from 00010000. While we're at it, make the PCI I/O resource end at 0001ffff, since we only have 64k of outbound I/O window on the IXP2000, and we don't do bank switching. Signed-off-by: Lennert Buytenhek Signed-off-by: Deepak Saxena Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2658/1: start ixp2000 pci memory resource at 0xe0000000Lennert Buytenhek2005-04-291-1/+1
| | | | | | | | | | | | | | | | Patch from Lennert Buytenhek On the IXDP2800, the bootloader does an awful job of configuring the PCI bus, so we make linux reconfigure everything. Having a 1:1 pci:phys address mapping generally simplifies everything, so try to allocate PCI addresses from the [e0000000..ffffffff] range, which is the physical address range of the outbound PCI window on the IXP2000. This does not affect any of the other IXP2000 platforms since they all use their bootloader's PCI resource assignment. Signed-off-by: Lennert Buytenhek Signed-off-by: Deepak Saxena Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2657/1: export ixp2000_pci_config_addrLennert Buytenhek2005-04-291-1/+1
| | | | | | | | | | | Patch from Lennert Buytenhek Export ixp2000_pci_config_addr, to be used by the IXDP2800 platform setup code to coordinate booting the master and slave NPU. Signed-off-by: Lennert Buytenhek Signed-off-by: Deepak Saxena Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] x86_64: fix PT_NOTE addition to IA32 vDSORoland McGrath2005-04-291-0/+2
| | | | | | | | The addition of the PT_NOTE didn't take in the x86_64 version of the i386 vDSO, because I forgot the linker script bit in that copy. Signed-off-by: Roland McGrath <roland@redhat.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] ppc64: Fix return value of some vDSO callsBenjamin Herrenschmidt2005-04-283-0/+5
| | | | | | | | | | | The ppc vDSO would not properly clear the return value for some calls, which will be a problem when interfacing those calls with glibc. This should be fixed before 2.6.12 is released (as it is the first kernel with the ppc vDSO) so that we don't have to play with symbol versioning and ugly workarounds. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Automatic merge of ↵Linus Torvalds2005-04-2735-479/+2308
|\ | | | | | | rsync://rsync.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6.git
| * From: jbarnes@sgi.comJesse Barnes2005-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [IA64] fix ia64 Kconfig to allow CONFIG_PM on sn2 This probably should have been fixed when I fixed up the generic build for discontig+numa machines, but oh well. CONFIG_PM is allowable for generic builds but not for sn2 builds, which doesn't make much sense, and in fact breaks the build if recent ACPI bits are added to the tree. It looks like the only arch that needs to prevent CONFIG_PM stuff is the ski simulator (though those options could probably use some cleanup as well), so remove the big conditional and replace it with a simple test for IA64_HP_SIM instead. Signed-off-by: Jesse Barnes <jbarnes@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] iosapic.c: typo ... s/spin_unlock_irq/spin_unlock/Kenji Kaneshige2005-04-251-1/+1
| | | | | | | | | | | | | | vector sharing patch had a typo ... mismatched spin_lock() with a spin_unlock_irq(). Fix from Kenji Kaneshige. Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] print "siblings" before {physical,core,thread} idTony Luck2005-04-251-1/+1
| | | | | | | | | | | | | | | | Rohit and Suresh changed their mind about the order to print things in /proc/cpuinfo, but didn't include the change in the version of the patch they sent to me. Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] vector sharing (Large I/O system support)Kenji Kaneshige2005-04-252-89/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current ia64 linux cannot handle greater than 184 interrupt sources because of the lack of vectors. The following patch enables ia64 linux to handle greater than 184 interrupt sources by allowing the same vector number to be shared by multiple IOSAPIC's RTEs. The design of this patch is besed on "Intel(R) Itanium(R) Processor Family Interrupt Architecture Guide". Even if you don't have a large I/O system, you can see the behavior of vector sharing by changing IOSAPIC_LAST_DEVICE_VECTOR to fewer value. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] multi-core/multi-thread identificationSuresh Siddha2005-04-252-2/+273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Version 3 - rediffed to apply on top of Ashok's hotplug cpu patch. /proc/cpuinfo output in step with x86. This is an updated MC/MT identification patch based on the previous discussions on list. Add the Multi-core and Multi-threading detection for IPF. - Add new core and threading related fields in /proc/cpuinfo. Physical id Core id Thread id Siblings - setup the cpu_core_map and cpu_sibling_map appropriately - Handles Hot plug CPU Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Gordon Jin <gordon.jin@intel.com> Signed-off-by: Rohit Seth <rohit.seth@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] __copy_user breaks on unaligned srcKeith Owens2005-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | memcpy_mck.S::__copy_user breaks in the prefetch code under these conditions :- * src is unaligned and * dst is near the end of a page and * the page after dst is unmapped. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] Need to handle lfetch in "no_context" case.Tony Luck2005-04-251-3/+6
| | | | | | | | | | | | | | Thanks to Mark for tracking down this one. Users of __copy_from_user_inatomic() will be sad if we don't handle lfetch faults for the "no_context" case. Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Altix SN add support for slots in geoid_t locatorMark Goodwin2005-04-251-47/+24Star
| | | | | | | | | | | | | | | | | | | | | | This patch against ia64-test-2.6.12 is needed for forthcoming Altix chipsets. It renames geoid_any_t to geoid_common_t and splits the 8bit 'slab' field into two 4bit fields for 'slab' and 'slot'. Similar changes in the Altix SAL will retain backward compatibility for old kernels. Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] fix syscall-optimization goofDavid Mosberger-Tang2005-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sadly, I goofed in this syscall-tuning patch: ChangeSet 1.1966.1.40 2005/01/22 13:31:05 davidm@hpl.hp.com [IA64] Improve ia64_leave_syscall() for McKinley-type cores. Optimize ia64_leave_syscall() a bit better for McKinley-type cores. The patch looks big, but that's mostly due to renaming r16/r17 to r2/r3. Good for a 13 cycle improvement. The problem is that the size of the physical stacked registers was loaded into the wrong register (r3 instead of r17). Since r17 by coincidence always had the value 1, this had the effect of turning rse_clear_invalid into a no-op. That poses the risk of leaking kernel state back to user-land and is hence not acceptable. The fix below is simple, but unfortunately it costs us about 28 cycles in syscall overhead. ;-( Unfortunately, there isn't much we can do about that since those registers have to be cleared one way or another. --david Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Shub2 BTE support - BTE recovery codeRuss Anderson2005-04-252-31/+54
| | | | | | | | | | | | | | | | | | | | patch 2: Shub2 BTE recovery code will be implemented in SAL. Define the SAL interface. Modify bte_error to call SAL for shub2. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Add new MMR definitions/Modify BTE initialiation&copy.Russ Anderson2005-04-251-9/+11
| | | | | | | | | | | | | | | | | | | | patch 1: Add new MMR definitions. Modify BTE initialiation. Modify BTE copy. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] disable TIOCA GART TLB prefetchingMark Maule2005-04-251-3/+3
| | | | | | | | | | | | | | Patch to disable SGI TIOCA GART TLB prefetching due to hw bug. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] MAX_PGT_FREES_PER_PASS must be 'L' to avoid warningTony Luck2005-04-251-1/+1
| | | | | | | | | | | | 'min' is very picky about types of arguments, make it happy Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] sba_iommu bug fixesAlex Williamson2005-04-251-40/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a couple of bugs in the zx1/sx1000 sba_iommu. These are all pretty low likelihood of hitting. The first problem is a simple off by one, deep in the sba_alloc_range() error path. Surrounding that was a lock ordering problem that could have potentially deadlocked with the order the locks are grabbed in sba_unmap_single(). I moved the resource locking into sba_search_bitmap() to prevent this. Finally, there's a potential race between unmapping pdir entries and marking incoming DMA pages clean. If you see any oddities, please let me know, but I've tested it pretty thoroughly here. Tony, please apply. Thanks, BTW, many of the options in this driver not on by default are becoming more and more broken. I'll be working on some patches to clean them out, but I wanted to get this bug fix out first. Signed-off-by: Alex Williamson <alex.williamson@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] Percpu quicklist for combined allocator for pgd/pmd/pte.Robin Holt2005-04-253-29/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces using the quicklists for pgd, pmd, and pte levels by combining the alloc and free functions into a common set of routines. This greatly simplifies the reading of this header file. This patch is simple but necessary for large numa configurations. It simply ensures that only pages from the local node are added to a cpus quicklist. This prevents the trapping of pages on a remote nodes quicklist by starting a process, touching a large number of pages to fill pmd and pte entries, migrating to another node, and then unmapping or exiting. With those conditions, the pages get trapped and if the machine has more than 100 nodes of the same size, the calculation of the pgtable high water mark will be larger than any single node so page table cache flushing will never occur. I ran lmbench lat_proc fork and lat_proc exec on a zx1 with and without this patch and did not notice any change. On an sn2 machine, there was a slight improvement which is possibly due to pages from other nodes trapped on the test node before starting the run. I did not investigate further. This patch shrinks the quicklist based upon free memory on the node instead of the high/low water marks. I have written it to enable preemption periodically and recalculate the amount to shrink every time we have freed enough pages that the quicklist size should have grown. I rescan the nodes zones each pass because other processess may be draining node memory at the same time as we are adding. Signed-off-by: Robin Holt <holt@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI]Bruce Losure2005-04-251-0/+548
| | | | | | | | | | | | | | Missed the "bk new" for this file in the last commit. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Altix: enable poweroffAaron J Young2005-04-251-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary "hook" to allow SGI/SN machines to perform a system power off upon a 'init 0', 'halt -p', 'poweroff' or 'shutdown -h'. The "hook" is to set the pm_power_off callback to ia64_sn_power_down(). pm_power_off is checked in machine_power_off()/do_poweroff() and, if set, is executed. ia64_sn_power_down() is a function already present (but not used currently) in the sn kernel. ia64_sn_power_down() makes a SAL call to execute the power off. Signed-off-by: Aaron J Young <ayoung@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Bus driver for the CX port of SGI's TIO chip.Bruce Losure2005-04-252-0/+3
| | | | | | | | | | | | | | | | This patch is to provide CX port infrastructure for SGI TIO-based h/w. Also a 'core services' driver for SGI FPGA-based h/w. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] perfmon: make pfm_sysctl a global, and other cleanupStephane Eranian2005-04-252-42/+30Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - make pfm_sysctl a global such that it is possible to enable/disable debug printk in sampling formats using PFM_DEBUG. - remove unused pfm_debug_var variable - fix a bug in pfm_handle_work where an BUG_ON() could be triggered. There is a path where pfm_handle_work() can be called with interrupts enabled, i.e., when TIF_NEED_RESCHED is set. The fix correct the masking and unmasking of interrupts in pfm_handle_work() such that we restore the interrupt mask as it was upon entry. signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Shub2 provides an addition of 2 External Interrupt events.Colin Ngam2005-04-251-13/+2Star
| | | | | | | | | | Signed-off-by: Colin Ngam <cngam@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Altix SN topology fix potential infinite loopMark Goodwin2005-04-251-5/+7
| | | | | | | | | | | | | | Fix infinite loop if sn_hwperf_location_to_bpos() fails. Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Altix SN topology support for new chipsets and pci topologyMark Goodwin2005-04-251-9/+124
| | | | | | | | | | | | | | | | | | | | | | please accept this patch to the Altix SN platform topology export interface to support new chipsets and to export PCI topology. This follows on top of Jack Steiner's patch dated March 1st ("New chipset support for SN platform"). Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] speed up syscall path a bit moreDavid Mosberger-Tang2005-04-251-6/+6
| | | | | | | | | | | | | | | | | | | | Recently I noticed that clearing ar.ssd/ar.csd right before srlz.d is causing significant stalling in the syscall path. The patch below fixes that by moving the register-writes after srlz.d. On a Madison, this drops break-based getpid() from 241 to 226 cycles (-15 cycles). Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] Tighten up unw_unwind_to_user checkKeith Owens2005-04-251-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect user space by the unwind frame with predicate PRED_USER_STACK set, instead of a user space IP. Tighten up the last ditch check for running off the top of the kernel stack. Based on a suggestion by David Mosberger, reworked to fit the current tree. This survives my stress test which used to break 2.6.9 kernels. Unlike 2.6.11, the stress test now unwinds to the correct point, so gdb can get the user space registers. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] add missing cpu_relax() in ITC syncing codeDavid Mosberger-Tang2005-04-251-4/+7
| | | | | | | | | | | | | | Call cpu_relax() in busy-waiting loops of the ITC-syncing code. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] altix: tioca chip driver (agp)Mark Maule2005-04-253-1/+671
| | | | | | | | | | | | | | | | Provide a driver for the altix TIOCA AGP chipset. An agpgart backend will be provided as a separate patch. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] sn2-move-pci-headers.patchMark Maule2005-04-259-123/+14Star
| | | | | | | | | | | | | | | | Move a couple of headers out of arch/ia64/sn/include/pci and into include/asm-ia64/sn. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] sn2-pci-dma-abstraction.patchMark Maule2005-04-257-79/+173
| | | | | | | | | | | | | | | | Provide an abstraction of the altix pci dma runtime layer so that multiple pci-based bridges can be supported. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [PATCH] ppc64: trivial user annotationsAl Viro2005-04-262-8/+8
| | | | | | | | | | Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | Automatic merge of kernel.org:/home/rmk/linux-2.6-rmk.gitLinus Torvalds2005-04-266-187/+124Star
|\ \
| * | [PATCH] ARM: make entry*.S includes more logicalRussell King2005-04-264-22/+12Star
| | | | | | | | | | | | | | | | | | | | | Move common includes to entry-header, and file specific includes to the relevant file. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * | [PATCH] ARM: Remove single-use user save/restore macrosRussell King2005-04-262-54/+25Star
| | | | | | | | | | | | | | | | | | | | | Assembly macros are pointless if they're only used once. Move them inline. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * | [PATCH] ARM: remove PT_TRACESYSRussell King2005-04-261-2/+0Star
| | | | | | | | | | | | | | | | | | PT_TRACESYS is unused, remove it. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * | [PATCH] ARM: Remove SVC_MODE definitionRussell King2005-04-262-5/+1Star
| | | | | | | | | | | | | | | | | | | | | SVC_MODE reflects the MODE_SVC definition in asm/ptrace.h. Use the asm/ptrace.h definition instead, and remove SVC_MODE. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * | [PATCH] ARM: Use __NR_SYSCALL_BASE and __ARM_NR_BASE in asm codeRussell King2005-04-262-27/+15Star
| | | | | | | | | | | | | | | | | | | | | Don't define our own local constants, but use those already defined in asm/unistd.h instead. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * | [PATCH] ARM: pt_regs offsetsRussell King2005-04-263-28/+30
| | | | | | | | | | | | | | | | | | | | | Generate pt_regs S_xx offsets from the structure itself instead of #defining them. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * | [PATCH] ARM: Remove argument for disable_irq/enable_irqRussell King2005-04-263-20/+16Star
| | | | | | | | | | | | | | | | | | | | | Since we do not require a register for these operations, we can remove this unnecessary argument. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * | [PATCH] ARM: remove some entry initialisation asm codeRussell King2005-04-262-31/+27Star
| | | | | | | | | | | | | | | | | | Convert the trivial vector entry initialisation code to C code. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* | | [PATCH] amd64 rt_sigframe user annotationAl Viro2005-04-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ->pretcode in struct rt_sigframe is a userland pointer (and already treated as such by code using that field). Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | [PATCH] ppc-opc NULL noise removalAl Viro2005-04-261-59/+60
| | | | | | | | | | | | | | | Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | Automated merge of kernel.org:/home/rmk/linux-2.6-rmk.gitLinus Torvalds2005-04-261-6/+50
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| * [PATCH] ARM: 2650/1: PXA27x sleep - workaround Errata 39 & 50 (Patch 2667)Jeff Lackey2005-04-261-6/+50
| | | | | | | | | | | | | | | | | | | | Patch from Jeff Lackey This patch updates arch/arm/mach-pxa/sleep.S to support the PXA270 CPU. It works around Errata 39 & 50 from the Intel(R) PXA27x Processor Family Specification Update. Signed-off-by: Jeff Lackey Signed-off-by: Russell King
* | [PATCH] ppc user annotations: debug_setconetext(2)Al Viro2005-04-251-1/+1
| | | | | | | | | | | | | | 3rd argument of sys_debug_setcontext() is also a userland pointer. Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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