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* MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill2014-01-224-0/+36
| | | | | | | | | | MIPS32R3 introduced a new set of Segmentation Control registers which increase the flexibility of the segmented-based memory scheme. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6131/
* MIPS: features: Add initial support for TLBINVF capable coresLeonid Yegoshin2014-01-223-0/+9
| | | | | | | | | | New Aptiv cores support the TLBINVF instruction for flushing the VTLB. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6130/
* MIPS: mm: Move UNIQUE_ENTRYHI macro to a header fileMarkos Chandras2014-01-223-8/+3Star
| | | | | | | | | | The UNIQUE_ENTRYHI definition was duplicated whenever there was the need to flush the TLB entries. We move this common definition to a header file. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6129/
* MIPS: Add missing bits for Config registersLeonid Yegoshin2014-01-221-2/+38
| | | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6128/
* MIPS: MT: proc: Add support for printing VPE and TC idsMarkos Chandras2014-01-221-1/+8
| | | | | | | | | | Add support for including VPE and TC ids in /proc/cpuinfo output as appropriate when MT/SMTC is enabled. Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6065/
* MIPS: Malta: Remove ttyS2 serial for CMP platformsLeonid Yegoshin2014-01-221-0/+2
| | | | | | | | | | | | | | | | | | Commit 225ae5fd9a320e22841410049c3bdb6cf14a5841 "MIPS: Malta: Fix interupt number of CBUS UART" fixed the IRQ number for the ttyS2 CBUS UART. However, this now conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta interrupt code arbitrarily binds IPIs to INT2 and INT3 and since ttyS2 uses the INT2 IRQ line, closing the device disables the INT2 interrupt and this effectively disables the IPI1 interrupt as well. This patch is mainly a workaround until the Malta code is fixed properly. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6045/
* MIPS: Add printing of ES bit for Imgtec cores when cache error occurs.Leonid Yegoshin2014-01-221-8/+21
| | | | | | | | | | | The cacheer register is always implemented in the same way in the MIPS32r2 Imgtec cores so print the ES bit when an cache error occurs. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6041/
* MIPS: GIC: Send IPIs using the GICSteven J. Hill2014-01-221-0/+27
| | | | | | | | | | | | | If GIC is present, then use it to send IPIs between the cores. Using GIC for IPIs is simpler and is usable for multicore systems compared to the existing way of doing IPIs where all VPEs had to be disabled for another VPE to access the Cause register in one of the TCs and enable all the VPEs back. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6040/
* MIPS: MT: Mark existing TCs as presentMarkos Chandras2014-01-221-0/+1
| | | | | | | | | | | According to Documentation/cpu-hotplug.txt, the cpu_present_mask should contain all the CPUs which are present in the system. Therefore, all the TCs currently present in the system should be marked as 'present' even if they will never be brought online. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6039/
* MIPS: mm: c-r4k: Panic if IL or DL fields have a reserved valueMarkos Chandras2014-01-221-8/+16
| | | | | | | | | | | According to MIPS32 and MIPS64 PRA documents, a value of 7 in IL and DL fields is marked as "Reserved" so panic if the core uses this value in the config1 register. Also simplify the code a little bit. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5861/
* MIPS: kernel: smp-cmp: MIPS MT code needs CONFIG_MIPS_MTMarkos Chandras2014-01-221-0/+3
| | | | | | | | | | | | | | | | The mips_mt_* symbols are only built and exported if CONFIG_MIPS_MT is enabled. Fixes the following build problem when CONFIG_SMP is enabled but CONFIG_MIPS_MT is not. arch/mips/built-in.o: In function `cmp_prepare_cpus': arch/mips/kernel/smp-cmp.c:197: undefined reference to `mips_mt_set_cpuoptions' Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5860/
* MIPS: BCM47XX: Fix some very confused types and data corruptionIlia Mirkin2014-01-221-9/+9
| | | | | | | | | | | Fix nvram_read_alpha2 copying too many bytes over the ssb_sprom structure. Also fix the arguments of the read_macaddr, although the code was technically not wrong before due to an extra dereference. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6211/
* MIPS: BCM47XX: add vectored interrupt supportHauke Mehrtens2014-01-222-0/+24
| | | | | | | | | This adds support for vectored interrupt which is supported by the SoC using a MIPS 74K CPU like the BCM4716 and BCM4706. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6290/
* MIPS: BCM47XX: add cpu-feature-overrides.hHauke Mehrtens2014-01-221-0/+82
| | | | | | | | | | | | | | | | The BCM47XX SoC code missed a cpu-feature-overrides.h header file, this patch adds it. This code supports a long line of SoCs with different features so for some features we still have to rely on the runtime detection. This was crated by checking the features of a BCM4712, BCM4704, BCM5354, BCM4716 and BCM4706 SoC and then tested on these SoCs. There are some SoCs missing but I hope they do not have any more or less features. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6289/
* MIPS: BCM47XX: move constant array from stackHauke Mehrtens2014-01-221-1/+1
| | | | | | | | Move the possible nvram sizes from the stack into the data segment Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6044/
* MIPS: BCM47XX: add asmlinkage to plat_irq_dispatch()Hauke Mehrtens2014-01-221-1/+1
| | | | | | | | plat_irq_dispatch() is called from asm code, add asmlinkage. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6043/
* MIPS: BCM47XX: update defconfigHauke Mehrtens2014-01-221-580/+43Star
| | | | | | | | | | | The defconfig for bcm47xx contained lots of driver which are not special for these SoCs and missed on the other side some some drivers for parts essential for these SoC and only found on here. The flash, usb and some Ethernet driver were missing. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5930/
* MIPS: BCM47XX: add EARLY_PRINTK_8250 supportHauke Mehrtens2014-01-222-0/+11
| | | | | | | | | | | | | The BCM47xx SoCs have a 8250 serial compatible console at address 0x18000300 and an other at 0x18000400. On most devices 0x18000300 is wired to some pins on the board, we should use that. This is the smae for the AI (bcma) and the SB (ssb) bus, this is some offset on the chip common core. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5889/
* MIPS: BCM47XX: Remove CFE supportHauke Mehrtens2014-01-222-93/+0Star
| | | | | | | | | | | | | | | | | bcm47xx only uses the CFE code for early print to a console, but that is also possible with a early print serial 8250 driver. The CFE api init causes hangs somewhere in prom_init_cfe() on some devices like the Buffalo WHR-HP-G54 and the Asus WL-520GU. This was reported in https://dev.openwrt.org/ticket/4061 and https://forum.openwrt.org/viewtopic.php?id=17063 This will remove all the CFE handling code from bcm47xx. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5888/
* MIPS: BCM47XX: only print SoC name in system type in cpuinfoHauke Mehrtens2014-01-223-22/+13Star
| | | | | | | | | | | Recently the output of "system type" in /proc/cpuinfo was changed to Broadcom BCM4730 (Some sample board), but it is better to just print the SoC name in the "system type" entry. The board name will be added in the machine entry later. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5865/
* MIPS: BCM63XX: drop SYS_HAS_CPU_MIPS32R1Jonas Gorski2014-01-221-1/+0Star
| | | | | | | | | | All MIPS cores on BCM63XX identify as Broadcom, not MIPS, so no need to support non-broadcom MIPS CPUs. This also ensures that CPU_BMIPS is always selected. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6246/
* MIPS: cpu-type: guard BMIPS variants with SYS_HAS_CPU_BMIPS*Jonas Gorski2014-01-221-3/+10
| | | | | | | | | BMIPS32 and BMIPS3300 also need to be available for MIPS32R1, as bcm47xx might not select BMIPS. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6245/
* MIPS: BCM47XX: select BMIPS CPUs for BCM47XX_SSBJonas Gorski2014-01-221-0/+1
| | | | | | | | | Let BCM47XX_SSB select the appropriate BMIPS CPUs enountered on those systems. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6244/
* MIPS: BCM63XX: let the individual SoCs select the appropriate CPUsJonas Gorski2014-01-222-1/+8
| | | | | | | | | | Let each supported chip select the appropirate SYS_HAS_CPU_BMIPS* option for its embedded processor, so support will be conditionally included. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6250/
* MIPS: BCM63XX: always register bmips smp opsJonas Gorski2014-01-221-4/+2Star
| | | | | | | | Use the return value for guarding further SMP setup. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6249/
* MIPS: BMIPS: add a smp ops registration helperJonas Gorski2014-01-223-1/+28
| | | | | | | | | Add a helper similar to the generic register_XXX_smp_ops() for bmips. Register SMP UP ops in case of BMIPS32/3300. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6248/
* MIPS: BMIPS: extend BMIPS3300 to include BMIPS32Jonas Gorski2014-01-221-4/+4
| | | | | | | | | | Codewise there is no difference between these two, so it does not make sense to treat them differently. Also chip families having one of these tend to have the other. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6247/
* MIPS: BMIPS: select CPU_HAS_PREFETCHJonas Gorski2014-01-221-0/+1
| | | | | | | | As they are MIPS32 CPUs they do support the prefetch opcode. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6243/
* MIPS: BMIPS: select CPU_SUPPORTS_HIGHMEMJonas Gorski2014-01-221-1/+1
| | | | | | | | All BMIPS CPUs support HIGHMEM, so it should be selected by CPU_BMIPS. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6242/
* MIPS: BMIPS: merge CPU options into one optionJonas Gorski2014-01-221-41/+39Star
| | | | | | | | | | | | | Instead of treating each flavour as an exclusive CPU to select, make BMIPS the only option and let SYS_HAS_CPU_BMIPS* decide for which flavours to include support. Run tested on BMIPS3300 and BMIPS4350, only build tested for BMIPS4380 and BMIPS5000. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6240/
* MIPS: BMIPS: change compile time checks to runtime checksJonas Gorski2014-01-224-137/+235
| | | | | | | | | | | | | | Allow building for all bmips cpus at the same time by changing ifdefs to checks for the cpu type, or adding appropriate checks to the assembly. Since BMIPS43XX and BMIPS5000 require different IPI implementations, split the SMP ops into one for each, so the runtime overhead is only at registration time for them. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6241/
* MIPS: allow asm/cpu.h to be included from assemblyJonas Gorski2014-01-221-0/+3
| | | | | | | | Add guards around the enum to allow including cpu.h from assembly. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6238/
* MIPS: BCM63XX: disable SMP also on BCM3368Jonas Gorski2014-01-221-4/+4
| | | | | | | | BCM3368 has the same shared TLB as BCM6358. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6239/
* MIPS: BCM63XX: add HSSPI platform device and register itJonas Gorski2014-01-224-2/+60
| | | | | | Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6180/
* MIPS: BCM63XX: add HSSPI IRQ and register offsetsJonas Gorski2014-01-221-0/+18
| | | | | | Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6179/
* MIPS: BCM63XX: setup the HSSPI clock rateJonas Gorski2014-01-221-0/+18
| | | | | | | | Properly set up the HSSPI clock rate depending on the SoC's PLL rate. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6177/
* MIPS: BCM63XX: expose the HSSPI clockJonas Gorski2014-01-221-0/+24
| | | | | | Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6178/
* MIPS: Support for 64-bit FP with O32 binariesPaul Burton2014-01-1319-236/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove unused {en,dis}able_fpu macrosPaul Burton2014-01-131-13/+0Star
| | | | | | | | | These macros are not used anywhere in the kernel. Remove them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6111/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: microMIPS: mfhc1 & mthc1 support for the FPU emulatorSteven J. Hill2014-01-132-1/+9
| | | | | | | | | | | | | This patch adds support for microMIPS encodings of the mfhc1 & mthc1 instructions introduced in release 2 of the mips32 & mips64 architectures, converting them to their mips32 equivalents for the FPU emulator. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add mfhc1 & mthc1 support.Leonid Yegoshin2014-01-132-2/+27
| | | | | | | | | | | | | | | | This patch adds support for the mfhc1 & mthc1 instructions to the FPU emulator. These instructions were introduced in release 2 of the MIPS32 & MIPS64 architectures and allow access to the most significant 32 bits of a 64-bit FP register. [ralf@linux-mips.org: Fix ifdef hell added by original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2014-01-101-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock fixes from Mike Turquette: "Late fixes for clock drivers. All of these fixes are for user-visible regressions, typically boot failures or other unsafe system configuration that causes badness" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: clk-divider: fix divisor > 255 bug clk: exynos: File scope reg_save array should depend on PM_SLEEP clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock ARM: dts: exynos5250: Fix MDMA0 clock number clk: samsung: exynos5250: Add MDMA0 clocks clk: samsung: exynos5250: Fix ACP gate register offset clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks clk: samsung: exynos4: Correct SRC_MFC register
| * Merge tag 'samsung-clk-fixes' of ↵Mike Turquette2014-01-061-1/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-fixes Samsung Clock fixes for 3.13-rc7 * Several patches fixing up incorrectly defined register addresses and bitfield offsets that could lead to undefined operation when accessing respective registers or bitfields. 1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks 2a) clk: samsung: exynos5250: Fix ACP gate register offset 2b) clk: samsung: exynos5250: Add MDMA0 clocks 2c) ARM: dts: exynos5250: Fix MDMA0 clock number 3) clk: samsung: exynos4: Correct SRC_MFC register All three issues have been present since Exynos5250 and Exynos4 clock drivers were added by commits 6e3ad26816b72 ("clk: exynos5250: register clocks using common clock framework") and e062b571777f5 ("clk: exynos4: register clocks using common clock framework") respectively. * Patch to fix automatic disabling of Exynos5250 sysreg clock that could cause undefined operation of several peripherals, such as USB, I2C, MIPI or display block. 4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock Present since Exynos5250 clock drivers was added by commits 6e3ad26816b72 ("clk: exynos5250: register clocks using common clock framework"). * Patch fixing compilation warning in clk-exynos-audss driver when CONFIG_PM_SLEEP is disabled. 5) clk: exynos: File scope reg_save array should depend on PM_SLEEP Present since the driver was added by commit 1241ef94ccc3 ("clk: samsung: register audio subsystem clocks using common clock framework").
| | * ARM: dts: exynos5250: Fix MDMA0 clock numberAbhilash Kesavan2013-12-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to incorrect clock specified in MDMA0 node, using MDMA0 controller could cause system failures, due to wrong clock being controlled. This patch fixes this by specifying correct clock. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Corrected commit message and description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* | | Merge tag 'fixes-for-linus' of ↵Linus Torvalds2014-01-103-5/+5
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A few fixes for Renesas platforms to fixup DMA masks (this started causing errors once the DMA API added checks for valid masks in 3.13)" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: shmobile: mackerel: Fix coherent DMA mask ARM: shmobile: kzm9g: Fix coherent DMA mask ARM: shmobile: armadillo: Fix coherent DMA mask
| * \ \ Merge tag 'renesas-fixes3-for-v3.13' of ↵Olof Johansson2014-01-023-5/+5
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes From Simon Horman: Third Round of Renesas ARM based SoC Fixes for v3.13 * sh7372 (SH-Mobile AP4) based Mackerel board r8a773a0 (SH-Mobile AG5) based kzm9g board r8a7740 (R-Mobile A1) based Armadillo board - Correct coherent DMA mask This resolves regressions introduced by 4dcfa60071b3d23f ("ARM: DMA-API: better handing of DMA masks for coherent allocations") in v3.12-rc1. * tag 'renesas-fixes3-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: mackerel: Fix coherent DMA mask ARM: shmobile: kzm9g: Fix coherent DMA mask ARM: shmobile: armadillo: Fix coherent DMA mask Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | ARM: shmobile: mackerel: Fix coherent DMA maskLaurent Pinchart2013-12-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4dcfa60071b3d23f0181f27d8519f12e37cefbb9 ("ARM: DMA-API: better handing of DMA masks for coherent allocations") added an additional check to the coherent DMA mask that results in an error when the mask is larger than what dma_addr_t can address. Set the LCDC coherent DMA mask to DMA_BIT_MASK(32) instead of ~0 to fix the problem. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | ARM: shmobile: kzm9g: Fix coherent DMA maskLaurent Pinchart2013-12-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4dcfa60071b3d23f0181f27d8519f12e37cefbb9 ("ARM: DMA-API: better handing of DMA masks for coherent allocations") added an additional check to the coherent DMA mask that results in an error when the mask is larger than what dma_addr_t can address. Set the LCDC coherent DMA mask to DMA_BIT_MASK(32) instead of ~0 to fix the problem. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | ARM: shmobile: armadillo: Fix coherent DMA maskLaurent Pinchart2013-12-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4dcfa60071b3d23f0181f27d8519f12e37cefbb9 ("ARM: DMA-API: better handing of DMA masks for coherent allocations") added an additional check to the coherent DMA mask that results in an error when the mask is larger than what dma_addr_t can address. Set the LCDC coherent DMA mask to DMA_BIT_MASK(32) instead of ~0 to fix the problem. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | | parisc: Ensure full cache coherency for kmap/kunmapJohn David Anglin2014-01-083-46/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Helge Deller noted a few weeks ago problems with the AIO support on parisc. This change is the result of numerous iterations on how best to deal with this problem. The solution adopted here is to provide full cache coherency in a uniform manner on all parisc systems. This involves calling flush_dcache_page() on kmap operations and flush_kernel_dcache_page() on kunmap operations. As a result, the copy_user_page() and clear_user_page() functions can be removed and the overall code is simpler. The change ensures that both userspace and kernel aliases to a mapped page are invalidated and flushed. This is necessary for the correct operation of PA8800 and PA8900 based systems which do not support inequivalent aliases. With this change, I have observed no cache related issues on c8000 and rp3440. It is now possible for example to do kernel builds with "-j64" on four way systems. On systems using XFS file systems, the patch recently posted by Mikulas Patocka to "fix crash using XFS on loopback" is needed to avoid a hang caused by an uninitialized lock passed to flush_dcache_page() in the page struct. Signed-off-by: John David Anglin <dave.anglin@bell.net> Cc: stable@vger.kernel.org # v3.9+ Signed-off-by: Helge Deller <deller@gmx.de>
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